CN218957729U - Alignment mark for overlay - Google Patents

Abstract

The application belongs to the integrated circuit field, specifically discloses an alignment mark is carved to cover, this alignment mark forms on the wafer to cover, includes at least: a first pattern formed on a first layer of the wafer as a part of the first layer pattern; a second pattern formed on a second layer of the wafer as a part of the second layer pattern and including two second sub-patterns symmetrically disposed about the first pattern in the first direction; the projection of the first pattern and the second pattern on the wafer forms a pattern with a rectangular external contour. The alignment mark reflects the error between the first layer alignment and the second layer alignment by whether the two second sub-patterns and the first pattern meet the symmetrical relation or not, and can further reflect the error between the first layer alignment and the second layer alignment by whether the external outline of the pattern formed by the first pattern and the second pattern is rectangular or not; the alignment accuracy of the overlay is improved by the comprehensive judgment mode.

Description

Alignment mark for overlay

Technical Field

The application belongs to the technical field of integrated circuits, and particularly relates to an alignment mark for alignment.

Background

With the rapid development of semiconductor processes, integrated circuits (Intergrated Circuit, IC) have evolved from small scale in the last century to very large scale today. In the current semiconductor manufacturing process, the photolithography process is the most important. Among the most important indicators in the lithography process are critical dimension (Critical Dimension), resolution, overlay error (Overlay), particle (Particle), and defect (defect) density. Ideally, the current layer alignment mark and the front layer alignment mark of the integrated circuit are completely aligned, i.e. the relative displacement is zero. There is always a certain alignment error in the actual semiconductor processing process, because the mask of the alignment mark of the current layer cannot be completely in perfect alignment with the mask of the alignment mark of the previous layer in the alignment and exposure steps. The influence of the mask overlay mark on the overlay accuracy is very important, and as the overlay layer number is increased and the key size is continuously reduced, the problem that the yield is continuously reduced in the photoetching process of the wafer in the yellow light area is solved, and the requirements of the photoetching process on the design of the overlay mark are higher and higher.

At present, frame-in-Frame, box-in-Box and Bar-in-Bar alignment marks are commonly adopted, and in a 28-130 nm process technology node, a larger alignment error occurs between a previous layer and a current layer, the alignment error exceeds a critical dimension allowable alignment error range, the electrical performance of a semiconductor device is directly affected, and the yield of semiconductor photoetching processing is reduced. The alignment precision of 28-130 nm process technology nodes is improved by adopting the cross photoetching alignment mark, so that the alignment error range is kept in a reasonable interval. However, the two alignment modes requiring long time for the cross-shaped mark are adopted, and the first step is coarse alignment, namely, two alignment marks in one area are selected on a wafer and two alignment marks on a mask are aligned. The second step is fine alignment, generally, alignment marks in a plurality of exposure areas are selected to be aligned with marks on the mask respectively, correction values are calculated and fed back to an exposure machine for correction, and alignment errors are reduced. In addition, the cross-shaped photoetching alignment mark occupies a larger area of the cutting path area, and is seriously deformed after chemical polishing and other processes, so that the alignment error of the multi-layer alignment is increased, the yield of finished products is reduced, and the manufacturing cost is increased.

Disclosure of Invention

The embodiment of the application provides an alignment mark for alignment, which aims to solve the technical problems of low alignment efficiency and large error in the prior art.

The alignment mark is aligned in the alignment that this embodiment provided, alignment mark forms on the wafer, and the wafer is including the first layer pattern that is arranged in the first layer of wafer and the second layer pattern that is arranged in the second layer of first layer top of wafer at least, its characterized in that alignment mark is aligned in the alignment mark at least includes:

a first pattern formed on a first layer of the wafer as a part of the first layer pattern;

a second pattern formed on a second layer of the wafer as a part of the second layer pattern and including two second sub-patterns symmetrically disposed about the first pattern in the first direction;

the projection of the first pattern and the second pattern on the wafer forms a pattern with a rectangular external contour.

According to an embodiment of the present application, the first pattern and the two second sub-patterns have the same abscissa or ordinate of the center coordinates under a preset coordinate system.

According to any of the preceding embodiments of the present application, the wafer further comprises a third layer pattern in a third layer above the second layer of the wafer, the overlay alignment mark further comprising

A third pattern formed on a third layer of the wafer as a part of the third layer pattern and including two third sub-patterns symmetrically disposed about the first pattern in a second direction perpendicular to the first direction;

the projections of the first pattern, the second pattern and the third pattern on the wafer form a pattern with a rectangular external contour.

According to any of the foregoing embodiments of the present application, in a preset coordinate system, the abscissa of the central coordinates of the first pattern and the two second sub-patterns is the same, and the ordinate of the central coordinates of the first pattern and the two third sub-patterns is the same; or (b)

Under a preset coordinate system, the ordinate of the central coordinates of the first pattern and the two second sub-patterns are the same, and the abscissa of the central coordinates of the first pattern and the two third sub-patterns are the same.

According to any of the foregoing embodiments of the present application, the outer contours of the first, second, and third sub-patterns include at least two of square, rectangular, and triangular.

According to any of the foregoing embodiments of the present application, the outer contours of the first pattern, the second sub-pattern and the third sub-pattern are all rectangular.

According to any of the foregoing embodiments of the present application, the outer contours of the first pattern and the second sub-pattern are square, and the outer contour of the third sub-pattern is rectangular; or (b)

The external contour of the first pattern and the third sub-pattern is square, and the external contour of the second sub-pattern is rectangular; or (b)

The external contour of the first pattern is square, and the external contour of the second sub pattern and the third sub pattern are rectangular; or (b)

The outer contour of the first pattern is rectangular, and the outer contour of the second sub-pattern and the third sub-pattern is rectangular or square.

According to any of the foregoing embodiments of the present application, the first pattern and/or the second sub-pattern and/or the third sub-pattern are ring-shaped patterns.

According to any of the foregoing embodiments of the present application, the first pattern, the second pattern and the third pattern are made of copper or an alloy with aluminum.

According to any of the foregoing embodiments of the present application, the projections of the first pattern, the second pattern, and the third pattern on the wafer constitute a pattern having a square outer contour.

The alignment mark reflects the error between the first layer alignment and the second layer alignment by whether the two second sub-patterns and the first pattern meet the symmetrical relation, and can further reflect the error between the first layer alignment and the second layer alignment by whether the external outline of the pattern formed by the first pattern and the second pattern is rectangular; the alignment precision of the overlay is improved by the layer-by-layer nesting mode.

Drawings

FIG. 1a is a schematic diagram of an overlay alignment mark according to an embodiment of the present disclosure;

FIG. 1b is a schematic diagram of an overlay alignment mark according to another embodiment of the present application;

fig. 2 is a schematic structural diagram of a preset coordinate system in an embodiment of the present application;

FIG. 3 is a schematic diagram of the alignment mark and scribe line structure according to an embodiment of the present application;

fig. 4a to 4f are schematic structural views of alignment marks according to other embodiments of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

The working process of the photoetching machine is as follows: the exposure process of the photoetching machine exposes all fields (fields) on the wafer W one by one, namely, steps are performed, and then the wafer W is replaced until all the wafers W are exposed; when the other process steps of the wafer W are finished, a photoresist coating process is performed, the mask is replaced by a photolithography machine, and then a second layer of pattern is exposed on the wafer W, that is, repeated exposure is performed. Wherein, the pattern of the second layer mask exposure must be exactly nested with the first layer mask exposure, so called overlay; overlay error refers to the positional error between two exposures.

The patterns on wafer W that are specially used to measure overlay errors are called overlay alignment marks, which have been placed in a designated area, typically on dicing lanes (a wafer W eventually needs to be diced into thousands of chips, the dicing lanes being reserved for chip dicing, typically only tens of microns) when designing a mask. Typically each layer will be assigned to be de-aligned to a previous layer.

Referring to fig. 1a and 1b, an alignment mark for alignment provided in an embodiment of the present application is formed on a wafer, where the wafer at least includes a first layer pattern (not shown) located in a first layer of the wafer and a second layer pattern (not shown) located in a second layer above the first layer of the wafer; the overlay alignment mark at least comprises a first pattern 1 and a second pattern 2; the first pattern 1 is formed on the first layer of the wafer and is part of a first layer pattern, the remaining part of the first layer pattern being a lithographic pattern (not shown in the figures); the second pattern 2 is formed on the second layer of the wafer and is part of a second layer pattern, the remaining part of the second layer pattern being a lithographic pattern (not shown in the figures), the second pattern 2 comprising two second sub-patterns 21 arranged symmetrically with respect to the first pattern 1 in the first direction; wherein, the projection of the first pattern 1 and the second pattern 2 on the wafer W forms a pattern with a rectangular external contour.

It will be appreciated that whether there is a deviation between the first layer pattern and the second layer pattern of the wafer can be reflected by the pattern formed by combining the first pattern 1 and the second pattern 2 of the two second sub-patterns 21 (i.e. the projection onto the wafer forms a pattern with a rectangular outer contour); if the pattern formed by combining the first pattern 1 and the second pattern 2 is in a preset rectangular shape, indicating that no deviation exists between the first layer pattern and the second layer pattern on the wafer or the deviation is within an acceptable threshold value range; if the pattern formed by combining the first pattern 1 and the second pattern 2 is not in the preset rectangular shape, it is indicated that the deviation between the first layer pattern and the second layer pattern on the wafer is unacceptable, and the position of the mask needs to be corrected by using an exposure machine (lithography machine). The overlay alignment mark on the wafer can be detected by a measuring instrument special for detecting overlay errors; if the measuring instrument detects that the pattern formed by combining the first pattern 1 and the second pattern 2 is not in the preset rectangular shape, the currently measured pattern and data related to the pattern are sent to an exposure machine (photoetching machine), and the exposure machine adjusts the position of the mask plate according to the obtained information to correct the position of the mask plate. The alignment mark for alignment in the structure can establish the relevance of the first pattern 1 and the second pattern 2 to the alignment error (caused by the relative position relation between the first pattern 1 and the second pattern 2), and also can establish the relevance of the pattern formed by combining the first pattern 1 and the second pattern 2 to the alignment error, so that the alignment error is detected from multiple dimensions, the detection precision of the alignment error is improved, and the stacking precision of multilayer alignment is ensured.

With continued reference to fig. 1a, in some embodiments, the first pattern 1 and the two second sub-patterns 21 have the same abscissa of the center coordinates under a predetermined coordinate system. Here, the preset coordinate system may be a coordinate system pre-stored in the exposure machine according to a position of a placing table on which the wafer W is placed and a position of the wafer W placed on the placing table, for example, as shown in fig. 2, after the wafer W is placed on the placing table, a preset coordinate system is constructed by taking a circle center of the wafer W as a coordinate axis dot, a direction in which a notch (notch) of the wafer W is located as a Y axis, and a direction perpendicular to the Y axis as an X axis. As shown in fig. 1a and 1b, in the process of generating the first pattern 1 and the second pattern 2, the first pattern 1 and the second pattern 2 are generated in an orientation in which the longitudinal direction and the width direction of the pattern formed by combining the first pattern 1 and the second pattern 2 are parallel to the directions of both coordinate axes, respectively. When the exposure machine exposes and develops the first layer pattern to the first layer of the wafer, the pattern on the current mask plate is projected to the wafer according to the built-in preset coordinate system, so that the center coordinate of the first pattern 1 is located at a preset position, for example, as shown in fig. 3, the first pattern 1 is located in the cutting channel CS, the exposure machine records the center coordinate parameter O1 (X1, Y1) of the first pattern 1, and the center of the first pattern 1 can reflect the position of the photoetching pattern in the first layer pattern; similarly, when the exposure machine exposes and develops the second layer pattern to the second layer of the wafer, the pattern on the current mask is projected to the wafer according to the built-in preset coordinate system, so that the central coordinates of the two second sub-patterns 21 are identical to the abscissa of the central coordinates of the first pattern 1, the pattern formed by combining the first pattern 1 and the second pattern 2 is ensured to be rectangular, the exposure machine records parameters O2 (X2, Y2) and O3 (X3, Y3) of the central coordinates of the two second sub-patterns 21, and the central coordinates of the two second sub-patterns 21 can reflect the position of the photoetching pattern in the second layer pattern. Then, detecting the positions of the first pattern 1 and the second pattern 2 on the wafer by using a measuring instrument, and judging whether the pattern formed by combining the first pattern 1 and the second pattern 2 is in a preset rectangular shape or not; specifically, the measuring instrument may collect the image information of the first pattern 1 and the second pattern 2, find the center of the first pattern 1 and the centers of the two second sub-patterns 21 according to the image information, calculate whether the difference (Δy1= |y1-y2= |y1-y3|) between the ordinate of the center coordinates of the first pattern 1 and the ordinate of the center coordinates of the two second sub-patterns 21 exceeds a threshold value, and if the difference exceeds the threshold value, feed the measured parameter information back to the exposure machine, and correct the bits of the current mask through the exposure machine. Since the two second sub-patterns 21 are symmetrically disposed with respect to the first pattern 1, a difference in the ordinate of the center coordinates of the first pattern 1 and the two second sub-patterns 21 may reflect the overlapping accuracy of the first layer pattern and the second layer pattern.

Similarly, please refer to fig. 1b, in some embodiments, the coordinates of the centers of the first pattern 1 and the two second sub-patterns 21 are the same under the preset coordinate system. When the exposure machine exposes and develops a first layer of patterns to a first layer of a wafer, the pattern on the current mask plate is projected to the wafer according to a built-in preset coordinate system, so that the central coordinate of the first pattern 1 is positioned at a preset position, the exposure machine records central coordinate parameters O1 (X1 and Y1) of the first pattern 1, and the center of the first pattern 1 can reflect the position of the photoetching pattern in the first layer of patterns; then, the exposure machine projects the pattern on the current mask onto the wafer according to the built-in preset coordinate system so that the central coordinates of the two second sub-patterns 21 are identical to the longitudinal coordinates of the central coordinates of the first pattern 1, and meanwhile, the combined pattern of the first pattern 1 and the second pattern 2 is ensured to be rectangular, the exposure machine records parameters O2 (X2, Y2) and O3 (X3, Y3) of the central coordinates of the two second sub-patterns 21, and the central coordinates of the two second sub-patterns 21 can reflect the position of the photoetching pattern in the second layer pattern. Then, detecting the positions of the first pattern 1 and the second pattern 2 on the wafer by using a measuring instrument, and judging whether the pattern formed by combining the first pattern 1 and the second pattern 2 is in a preset rectangular shape or not; specifically, the measuring instrument may collect the image information of the first pattern 1 and the second pattern 2, find the center of the first pattern 1 and the centers of the two second sub-patterns 21 according to the image information, calculate whether the difference (Δx1= |x1-x2= |x1-x3|) between the ordinate of the center coordinates of the first pattern 1 and the abscissa of the center coordinates of the two second sub-patterns 21 exceeds a threshold value, and if the difference exceeds the threshold value, feed the measured parameter information back to the exposure machine, and correct the bits of the current mask through the exposure machine.

Referring to fig. 4a and 4b, in some embodiments, the wafer further includes a third layer pattern (not shown) in a third layer above the second layer of the wafer; the overlay alignment mark further includes a third pattern 3 formed on and as a part of a third layer of the wafer, the remaining part of the third layer pattern being a photolithography pattern (not shown in the drawings), the third pattern 3 including two third sub-patterns 31 symmetrically arranged with respect to the first pattern 1 in a second direction, the second square being perpendicular to the first direction; the projections of the first pattern 1, the second pattern 2 and the third pattern 3 on the wafer form a pattern with a rectangular external contour.

It will be appreciated that the position error between the first layer exposure and the second layer exposure of the wafer, the position error between the second layer exposure and the third layer exposure, and the overall position error of the first layer exposure, the second layer exposure, and the third layer exposure can be reflected by the pattern formed by combining the first pattern 1, the second pattern 2, and the third pattern 3 (i.e., the pattern whose projection onto the wafer constitutes a rectangle in outline). In this embodiment, after the third pattern 3 is formed on the third layer of the wafer, it may be determined whether the position of the third pattern 3 meets the requirement by the symmetrical relevance of the two third sub-patterns 31 with respect to the first pattern 1 and the external contour that the pattern formed by combining the first pattern 1, the second pattern 2 and the third pattern 3 should have; if the measuring instrument detects that the pattern formed by combining the first pattern 1, the second pattern 2 and the third pattern 3 is not in the preset rectangular shape, the currently measured pattern and data related to the pattern are sent to the exposure machine, the exposure machine adjusts the position of the mask corresponding to the current layer according to the obtained information, and the position of the mask corresponding to the current layer is corrected. The alignment mark for alignment of the structure can establish the relevance of the first pattern 1, the second pattern 2 and the third pattern 3 with alignment errors (caused by the relative position relation between the first pattern 1 and the second pattern 2 and the relative position relation between the first pattern 1 and the third pattern 3), and also can establish the relevance of the patterns formed by combining the first pattern 1, the second pattern 2 and the third pattern 3 with the alignment errors, and detect the alignment errors from multiple dimensions, thereby improving the detection precision of alignment and ensuring the stacking precision of multilayer alignment.

Referring to fig. 4a, in some embodiments, in a preset coordinate system, the abscissa of the central coordinates of the first pattern 1 and the two second sub-patterns 21 are the same, and the ordinate of the central coordinates of the first pattern 1 and the two third sub-patterns 31 are the same. When the exposure machine exposes and develops the first layer pattern to the first layer of the wafer, the pattern on the current mask is projected to the wafer according to the built-in preset coordinate system, so that the center coordinate of the first pattern 1 is located at a preset position, for example, as shown in fig. 3, the first pattern 1 is located in a cutting path, the exposure machine records the center coordinate parameters O1 (X1, Y1) of the first pattern 1, and the center of the first pattern 1 can reflect the position of the lithography pattern (circuit pattern to be etched) in the first layer pattern. Similarly, when the exposure machine exposes and develops the second layer pattern to the second layer of the wafer, the pattern on the current mask is projected to the preset position of the wafer according to the built-in preset coordinate system, so that the central coordinates of the two second sub-patterns 21 are identical to the abscissa of the central coordinates of the first pattern 1; the exposure machine records parameters O2 (X2, Y2), O3 (X3, Y3) of the center coordinates of the two second sub-patterns 21, which may reflect the position of the lithographic pattern in the second layer pattern. Then, the positions of the first pattern 1 and the second pattern 2 on the wafer are detected by using the measuring instrument, specifically, the measuring instrument can acquire the image information of the first pattern 1 and the second pattern 2, find the center of the first pattern 1 and the centers of the two second sub-patterns 21 according to the image information, calculate whether the difference (Δy1= |y1-y2|= |y1-y3|) between the ordinate of the center coordinates of the first pattern 1 and the ordinate of the center coordinates of the two second sub-patterns 21 exceeds a threshold value, and if the difference exceeds the threshold value, feed the measured parameter information back to the exposure machine, and correct the position of the current mask through the exposure machine. Since the two second sub-patterns 21 are symmetrically disposed with respect to the first pattern 1, a difference in the ordinate of the center coordinates of the first pattern 1 and the two second sub-patterns 21 may reflect the overlapping accuracy of the first layer pattern and the second layer pattern. When the exposure machine exposes and develops the third layer pattern to the third layer of the wafer, the pattern on the current mask is projected to the preset position of the wafer according to the built-in preset coordinate system, so that the central coordinates of the two third sub-patterns 31 are identical to the ordinate of the central coordinates of the first pattern 1, the pattern formed by combining the first pattern 1, the second pattern 2 and the third pattern 3 is ensured to be rectangular, the exposure machine records parameters O4 (X4, Y4) and O5 (X5, Y5) of the central coordinates of the two third sub-patterns 31, and the central coordinates of the two third sub-patterns 31 can reflect the position of the photoetching pattern in the third layer pattern. Then, detecting the positions of the first pattern 1, the second pattern 2 and the third pattern 3 on the wafer by using a measuring instrument, and judging whether the combined pattern of the first pattern 1, the second pattern 2 and the third pattern 3 is in a preset rectangular shape or not; specifically, the measuring instrument may collect the image information of the first pattern 1, the second pattern 2 and the third pattern 3, find the center of the first pattern 1 and the centers of the two third sub-patterns 31 according to the image information, calculate whether the difference (Δx1= |x1-x4= |x1-x5|) between the ordinate of the center coordinates of the first pattern 1 and the abscissa of the center coordinates of the two second sub-patterns 21 exceeds a threshold value, and if the difference exceeds the threshold value, feed the measured parameter information back to the exposure machine, and correct the position of the current mask through the exposure machine. Since the two third sub-patterns 31 are symmetrically disposed with respect to the first pattern 1, a difference between the first pattern 1 and the abscissa of the center coordinates of the two third sub-patterns 31 may reflect the overlapping accuracy of the first layer pattern and the third layer pattern. Meanwhile, the measuring instrument may also determine whether the values of Δx1 and Δy1 satisfy a predetermined relationship, for example, whether the values satisfy a predetermined proportional relationship, whether the values are equal, and so on, depending on the shape of the combined pattern of the first pattern 1, the second pattern 2, and the third pattern 3.

Similarly, referring to fig. 4b, in some embodiments, the coordinates of the centers of the first pattern 1 and the two second sub-patterns 21 are the same, and the coordinates of the centers of the first pattern 1 and the two third sub-patterns 31 are the same. The exposure machine projects the pattern on the current mask plate to the wafer according to the built-in preset coordinate system, exposes and develops the first layer pattern to the first layer of the wafer, then records the central coordinate parameters O1 (X1, Y1) of the first pattern 1, and the center of the first pattern 1 can reflect the position of the photoetching pattern (circuit pattern to be etched) in the first layer pattern. Similarly, when the exposure machine exposes and develops the second layer pattern to the second layer of the wafer, the pattern on the current mask is projected to the preset position of the wafer according to the built-in preset coordinate system, and the central coordinates of the two second sub-patterns 21 are identical to the ordinate of the central coordinates of the first pattern 1; the exposure machine records parameters O2 (X2, Y2), O3 (X3, Y3) of the center coordinates of the two second sub-patterns 21, which may reflect the position of the lithographic pattern in the second layer pattern. Then, the positions of the first pattern 1 and the second pattern 2 on the wafer are detected by using the measuring instrument, specifically, the measuring instrument can acquire the image information of the first pattern 1 and the second pattern 2, find the center of the first pattern 1 and the centers of the two second sub-patterns 21 according to the image information, calculate the difference (Δx1= |x 1-x2|= |x 1-x3|) between the ordinate of the center coordinates of the first pattern 1 and the abscissa of the center coordinates of the two second sub-patterns 21, and if the difference exceeds the threshold, the measured parameter information is fed back to the exposure machine, and the position of the current mask is corrected by the exposure machine. Since the two second sub-patterns 21 are symmetrically disposed with respect to the first pattern 1, a difference between the first pattern 1 and the abscissa of the center coordinates of the two second sub-patterns 21 may reflect the overlapping accuracy of the first layer pattern and the second layer pattern. When the exposure machine exposes and develops the third layer pattern to the third layer of the wafer, the pattern on the current mask is projected to the preset position of the wafer according to the built-in preset coordinate system, so that the central coordinates of the two third sub-patterns 31 are identical to the abscissa of the central coordinates of the first pattern 1, the pattern formed by combining the first pattern 1, the second pattern 2 and the third pattern 3 is ensured to be rectangular, the exposure machine records parameters O4 (X4, Y4) and O5 (X5, Y5) of the central coordinates of the two third sub-patterns 31, and the central coordinates of the two third sub-patterns 31 can reflect the position of the third layer pattern. Then, detecting the positions of the first pattern 1, the second pattern 2 and the third pattern 3 on the wafer by using a measuring instrument, and judging whether the combined pattern of the first pattern 1, the second pattern 2 and the third pattern 3 is in a preset rectangular shape or not; specifically, the measuring instrument may collect the image information of the first pattern 1, the second pattern 2 and the third pattern 3, find the center of the first pattern 1 and the centers of the two third sub-patterns 31 according to the image information, calculate whether the difference (Δy1= |y1-y4= |y1-y5|) between the ordinate of the center coordinates of the first pattern 1 and the ordinate of the center coordinates of the two second sub-patterns 21 exceeds a threshold value, and if the difference exceeds the threshold value, feed the measured parameter information back to the exposure machine, and correct the position of the current mask through the exposure machine. Since the two third sub-patterns 31 are symmetrically disposed with respect to the first pattern 1, a difference between the first pattern 1 and the abscissa of the center coordinates of the two third sub-patterns 31 may reflect the overlapping accuracy of the first layer pattern and the third layer pattern.

In some embodiments, the outer contours of the first pattern 1, the second sub-pattern 21, and the third sub-pattern 31 include at least two of square, rectangle, and triangle. For example, as shown in fig. 4b, the outer contours of the first pattern 1 and the second sub-pattern 21 are square, and the outer contour of the third sub-pattern 31 is rectangular; as shown in fig. 4c, the first pattern 1 is square, and the second sub-pattern 21 and the third sub-pattern 31 are triangular; as shown in fig. 4d, the first pattern 1 is square, and the second sub-pattern 21 and the third sub-pattern 31 are rectangular; as shown in fig. 4e, the first pattern 1 is rectangular, and the second sub-pattern 21 and the third sub-pattern 31 are triangular; the first pattern 1 may have a rectangular shape, and the second sub-pattern 21 and the third sub-pattern 31 may each have a square shape. Of course, as shown in fig. 4f, the first pattern 1, the second sub-pattern 21, and the third sub-pattern 31 may each be rectangular.

Preferably, as shown, the outer contours of the first pattern 1, the second sub-pattern 21 and the third sub-pattern 31 are all rectangular. It can be appreciated that, on the one hand, the first pattern 1, the second sub-pattern 21 and the third sub-pattern 31 with rectangular outline are simple in pattern, so that the manufacturing difficulty of the mask can be reduced; the alignment precision of the alignment can be higher, and the space occupied by the alignment mark of the alignment on the cutting path can be effectively reduced by the regular rectangle; on the other hand, the external contour of all patterns is rectangular, so that the extending direction of the external contour lines of all patterns is parallel to the coordinate axis direction, and when the measuring instrument is used for detecting/calculating the distances between the central coordinates of different patterns, only the coordinate difference value in the direction of the corresponding coordinate axis is required to be measured/calculated, thereby greatly reducing the calculated amount.

In some embodiments, the first pattern 1 and/or the second sub-pattern 21 and/or the third sub-pattern 31 are each a ring-shaped pattern; as shown in fig. 4a and 4b, the first pattern 1, the second sub-pattern 21 and the third sub-pattern 31 are all annular patterns, on one hand, the annular patterns have low requirements on processing the mask, have simple structure and do not occupy too much space on the mask; on the other hand, the rectangular ring and square ring nested patterns adopted in the embodiment of the application have the following advantages: 1. the length and the width of the rectangular ring are formed by rectangular patterns, the length and the width of the rectangular ring have an equal ratio relationship, and the width of the rectangular patterns is consistent with the width of the rectangular ring on the X axis and the Y axis, so that the high accuracy of the overlay mark is ensured; 2. the length and the width of the square ring are formed by square patterns, the length and the width of the square ring have an equal ratio relationship, the length and the width of the square patterns are consistent in an X axis and a Y axis, the self-alignment advantage exists, and the high accuracy of the overlay mark is ensured; preferably, the rectangular ring (third sub-pattern) and the square ring (first pattern, second sub-pattern) in the embodiment of the present application have an equal ratio relationship of 3:1, each layer of alignment mark shares an X-axis or Y-axis coordinate, meanwhile, the connection proportion relation ensures the precision, the top view is square after the third layer of alignment mark is finished, the error of the alignment mark of the first layer and the second layer of the wafer in the X-axis and the Y-axis is inspected in a self-alignment manner, and the precision of the multilayer alignment is ensured.

In some embodiments, the first pattern 1, the second pattern 2 and the third pattern 3 are made of copper or an alloy with aluminum. After the current layer (the first layer or the second layer or the third layer) of the wafer is subjected to exposure development by using a mask and an exposure machine, a hollowed-out pattern (a first pattern 1 or a second pattern 2 or a third pattern 3) is formed on the current layer of the wafer; and filling copper or the same aluminum alloy into the hollowed-out pattern to form a solid pattern (the first pattern 1, the second pattern 2 or the third pattern 3). After copper or copper-aluminum alloy is filled, the subsequent process can be prevented from damaging the alignment mark, and the alignment mark can be effectively detected by a measuring instrument (optical detection equipment). In the prior art node integrated circuit manufacturing process, the mechanical strength of copper and copper-aluminum alloy is higher, the post-annealing process has good plasticity and the post-chemical mechanical polishing (chemical mechanical polishing, CMP) process has low damage to the overlay mark, the uncertainty of the overlay error measurement result of the overlay mark is reduced, and the precision of multilayer overlay is improved.

To further improve stacking accuracy of the overlay, in some embodiments, the projections of the first pattern 1, the second pattern 2, and the third pattern 3 on the wafer constitute a pattern with a square outer contour. Preferably, the first pattern 1 is square, one of the second sub-pattern 21 and the third sub-pattern 31 is square, and the other is rectangular; in this way, when the third pattern 3 is generated, it can be determined whether the overlay error exceeds the threshold value by determining whether the distance between the center coordinates of the two second sub-patterns 21 and the distance between the center coordinates of the two third sub-patterns 31 are equal. Since the lines of the outer contour formed by the projections of the pattern, the second pattern 2 and the third pattern 3 on the wafer are parallel to the coordinate axes, when judging the distance between the center coordinates, only the difference between the coordinates in the direction of one axis is needed to judge whether the difference exceeds the threshold value, so that the calculated amount is reduced.

In some embodiments, the alignment mark can be circularly generated in the wafer processing process, that is, each three layers form a set of alignment mark, and the alignment error of the adjacent layer can be reduced by identifying the alignment mark of the adjacent layer; by identifying the alignment marks of the adjacent three layers (formation), the alignment error of the current layer can be further corrected, and the alignment accuracy of alignment is improved.

The alignment mark is aligned by the alignment mark, the regular square ring pattern and the rectangular ring pattern are combined into the regular rectangular pattern, the occupied space of the alignment mark in a cutting path is effectively reduced, the measurement accuracy is improved, and meanwhile, the stacking accuracy of multilayer alignment can be ensured by utilizing the regular square pattern formed by the alignment mark of the first three layers. Secondly, the alignment mark is not easy to damage by other processing technologies due to the fact that copper or copper-aluminum alloy is adopted for filling, and the alignment mark made of metal materials can provide maximum signal intensity and can be effectively detected by optical detection equipment. And moreover, the regular square ring and rectangular ring are simple and convenient in design structure, and do not occupy too much space of the mask. In summary, the alignment mark can improve the production yield of the semiconductor processing yellow light area and reduce the manufacturing cost of the semiconductor.

Claims (10)

1. An overlay alignment mark formed on a wafer, the wafer including at least a first layer pattern in a first layer of the wafer and a second layer pattern in a second layer above the first layer of the wafer, the overlay alignment mark comprising at least:

a first pattern formed on a first layer of the wafer as a part of the first layer pattern;

a second pattern formed on a second layer of the wafer as a part of the second layer pattern and including two second sub-patterns symmetrically disposed about the first pattern in the first direction;

the projection of the first pattern and the second pattern on the wafer forms a pattern with a rectangular external contour.

2. The overlay alignment mark of claim 1, wherein: in a preset coordinate system, the abscissa or the ordinate of the central coordinates of the first pattern and the two second sub-patterns are the same.

3. The overlay alignment mark of claim 1, wherein: the wafer further includes a third layer pattern in a third layer above the second layer of the wafer, the overlay alignment mark further includes

A third pattern formed on a third layer of the wafer as a part of the third layer pattern and including two third sub-patterns symmetrically disposed about the first pattern in a second direction perpendicular to the first direction;

the projections of the first pattern, the second pattern and the third pattern on the wafer form a pattern with a rectangular external contour.

4. The overlay alignment mark of claim 3, wherein: under a preset coordinate system, the horizontal coordinates of the central coordinates of the first pattern and the two second sub-patterns are the same, and the vertical coordinates of the central coordinates of the first pattern and the two third sub-patterns are the same; or (b)

Under a preset coordinate system, the ordinate of the central coordinates of the first pattern and the two second sub-patterns are the same, and the abscissa of the central coordinates of the first pattern and the two third sub-patterns are the same.

5. The overlay alignment mark of claim 3, wherein: the outer contours of the first pattern, the second sub-pattern, and the third sub-pattern include at least two of square, rectangle, and triangle.

6. The overlay alignment mark of claim 5, wherein: the outer contours of the first pattern, the second sub-pattern and the third sub-pattern are all rectangular.

7. The overlay alignment mark of claim 6, wherein: the external contour of the first pattern and the second sub-pattern is square, and the external contour of the third sub-pattern is rectangular; or (b)

The external contour of the first pattern and the third sub-pattern is square, and the external contour of the second sub-pattern is rectangular; or (b)

The external contour of the first pattern is square, and the external contour of the second sub pattern and the third sub pattern are rectangular; or (b)

The outer contour of the first pattern is rectangular, and the outer contour of the second sub-pattern and the third sub-pattern is rectangular or square.

8. The overlay alignment mark of claim 3, wherein: the first pattern and/or the second sub-pattern and/or the third sub-pattern are ring-shaped patterns.

9. The overlay alignment mark of claim 8, wherein: the first pattern, the second pattern and the third pattern are made of copper or aluminum alloy.

10. The overlay alignment mark as set forth in any one of claims 3 to 9, wherein: the projections of the first pattern, the second pattern and the third pattern on the wafer form a pattern with square external outline.

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