CN218939717U - Flip LED chip with multistage reflecting layer - Google Patents
Flip LED chip with multistage reflecting layer Download PDFInfo
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- CN218939717U CN218939717U CN202320630207.1U CN202320630207U CN218939717U CN 218939717 U CN218939717 U CN 218939717U CN 202320630207 U CN202320630207 U CN 202320630207U CN 218939717 U CN218939717 U CN 218939717U
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Abstract
The utility model belongs to the technical field of chips, and particularly relates to a flip LED chip with a multistage reflecting layer, which comprises a substrate, wherein an N-type semiconductor layer, a light-emitting quantum well layer and a P-type semiconductor layer are sequentially arranged above the substrate from bottom to top, a current expansion layer is arranged above the P-type semiconductor layer, a current blocking DBR reflecting layer is arranged between the P-type semiconductor layer and the current expansion layer, and a DBR reflecting layer, a conductive metal reflecting layer, a passivation DBR reflecting layer and a welding metal reflecting layer are arranged above the current expansion layer. According to the flip LED chip with the multi-stage reflecting layers, the brightness of the chip can be effectively improved through the design of the multi-stage reflecting structure, meanwhile, the DBR reflecting layers and the passivation DBR reflecting layers are arranged, the leakage current of the chip can be effectively reduced, the conductive metal reflecting layers and the welding metal reflecting layers conduct current, meanwhile, the effect of increasing light reflection and heat conduction can be achieved, and the reliability of the chip is effectively improved.
Description
Technical Field
The utility model belongs to the technical field of chips, and particularly relates to a flip LED chip with a multistage reflection layer.
Background
LEDs are widely used as a new generation of light sources in the field of lighting and backlighting technologies. The traditional LED chip adopts the normal dress structure, and the front is its light emitting surface, and the welding gold thread when welding electrode and encapsulation all is at the coplanar with the light emitting surface, and the existence of welding gold thread can influence the luminous homogeneity of LED chip when the encapsulation, can lead to light's output efficiency to become low simultaneously, and sapphire substrate's heat dispersion is relatively poor simultaneously, seriously hinders thermal diffusion.
The welding electrode of the flip LED chip is arranged on the back of the luminous surface, the welding electrode can be attached to the substrate through solder paste, the electrode on the back can be electrified and can play a role in heat dissipation, the defect of the front-mounted LED chip is well overcome, but the flip LED chip still has the defects of low internal quantum efficiency, easiness in electric leakage and the like.
Disclosure of Invention
The utility model aims to provide a flip LED chip with a multi-stage reflecting layer, so as to solve the technical problems in the background art.
In order to achieve the technical purpose, the technical scheme of the utility model comprises the following steps:
the flip LED chip with the multi-stage reflecting layer comprises a substrate, wherein an N-type semiconductor layer, a light-emitting quantum well layer and a P-type semiconductor layer are sequentially arranged above the substrate from bottom to top, a spoon-shaped groove is formed in the middle of the top of the N-type semiconductor layer, a first spoon-shaped hole is formed in the middle of the light-emitting quantum well layer, a second spoon-shaped hole is formed in the middle of the P-type semiconductor layer, a current expansion layer is arranged above the P-type semiconductor layer, a current blocking DBR reflecting layer is arranged between the P-type semiconductor layer and the current expansion layer, and a DBR reflecting layer, a conductive metal reflecting layer, a passivation DBR reflecting layer and a welding metal reflecting layer are arranged above the current expansion layer;
the DBR reflection layer covers the upper surface of the current expansion layer, the N-type semiconductor layer, the light-emitting quantum well layer and the side wall of the P-type semiconductor layer and is connected with the top edge of the substrate, and is provided with a fourth spoon-shaped hole and a first round hole;
the shape and position of the first spoon-shaped hole, the second spoon-shaped hole and the fourth spoon-shaped hole correspond to those of the spoon-shaped groove, and the edge of the fourth spoon-shaped hole of the DBR reflection layer extends to the bottom of the spoon-shaped groove;
the passivation DBR reflection layer covers the upper surface of conducting metal reflection layer with conducting metal reflection layer's lateral wall and with the marginal junction of the upper surface of DBR reflection layer, passivation DBR reflection layer's middle part gets into in the fourth spoon shape hole, passivation DBR reflection layer's one side is equipped with the circular hole of second, and the opposite side is equipped with three square hole.
As an improvement, the current blocking DBR reflecting layer is uniformly distributed on the P-type semiconductor layer in a circular shape, and the position of the current blocking DBR reflecting layer corresponds to the position of the first circular hole;
the middle part of the current expansion layer is provided with a third spoon-shaped hole, and the position and the shape of the third spoon-shaped hole correspond to those of the spoon-shaped groove.
As a further improvement, the conductive metal reflecting layer includes an N conductive metal reflecting layer and a P conductive metal reflecting layer, the P conductive metal reflecting layer is connected with the current spreading layer through a first circular hole of the DBR reflecting layer, and the P conductive metal reflecting layer is provided with a fifth scoop-shaped hole;
the N conductive metal reflecting layer is spoon-shaped, the N conductive metal reflecting layer is positioned in a fourth spoon-shaped hole of the DBR reflecting layer, the lower surface of the N conductive metal reflecting layer is connected with the bottom surface of a spoon-shaped groove of the N-type semiconductor layer, and the side wall of the N conductive metal reflecting layer is connected with the DBR reflecting layer.
As a further improvement, the positions of the second circular holes correspond to the positions of the N conductive metal reflecting layers, and the positions of the three square holes correspond to the positions of the P conductive metal reflecting layers.
As a further improvement, the weld metal reflecting layer includes an N weld metal reflecting layer and a P weld metal reflecting layer, the P weld metal reflecting layer being located on top of where the passivation DBR reflecting layer is provided with the square hole, the N weld metal reflecting layer being located on top of where the passivation DBR reflecting layer is provided with the second circular hole;
the P welding metal reflecting layer is connected with the P conductive metal reflecting layer through three square holes, and the N welding metal reflecting layer is connected with the N conductive metal reflecting layer through the second round holes.
As a further improvement, the current blocking DBR reflective layer is 3 groups of SiO 2 With TiO 2 The material is formed into a current blocking DBR reflecting layer through vapor deposition lamination, and the thickness of the current blocking DBR reflecting layer is 400-500nm;
the DBR reflection layer is 15 groups of SiO 2 With TiO 2 The DBR reflection layer is formed by vapor deposition lamination of materials, and the thickness of the DBR reflection layer is 2-3 mu m;
the passivation DBR reflection layer adopts Si0 2 DBR structure, wherein Si0 2 Has a thickness of 1.5-2 μm and DBR of 3 groups of SiO 2 With TiO 2 The material is formed by vapor deposition lamination, and the thickness of the material is 400-500nm.
By adopting the technical scheme, the utility model has the beneficial effects that:
according to the flip LED chip with the multi-stage reflecting layers, the brightness of the flip LED chip can be effectively improved through the design of the multi-stage reflecting structure, meanwhile, the DBR reflecting layers and the passivation DBR reflecting layers are arranged, the leakage current of the flip LED chip can be effectively reduced, the conductive metal reflecting layers and the welding metal reflecting layers conduct current, meanwhile, the effect of increasing light reflection and heat conduction can be achieved, and the reliability of the flip LED chip is effectively improved.
Drawings
Fig. 1 is a schematic structural view of a substrate, an N-type semiconductor layer, a light emitting quantum well layer, and a P-type semiconductor layer;
FIG. 2 is a cross-sectional view taken along the direction A-A of FIG. 1;
FIG. 3 is a schematic diagram of a current blocking DBR mirror distribution;
FIG. 4 is a schematic diagram of a current spreading layer distribution;
FIG. 5 is a schematic diagram of a DBR reflection layer distribution;
FIG. 6 is a schematic diagram of a conductive metal reflective layer distribution;
FIG. 7 is a schematic diagram of a passivation DBR reflection layer distribution;
FIG. 8 is a schematic diagram of a weld metal reflector layer distribution;
FIG. 9 is a B-B sectional view of FIG. 8;
FIG. 10 is a C-C sectional view of FIG. 8;
wherein: 1-a substrate; a 2-N type semiconductor layer; 3-a luminescent quantum well layer; a 4-P type semiconductor layer; a 5-current blocking DBR reflective layer; 6-a current spreading layer; a 7-DBR reflection layer; 71-a first circular hole; 72-a fourth scoop-shaped aperture; an 8-P conductive metal reflective layer; a 9-N conductive metal reflective layer; 10-passivating the DBR reflective layer; 101-square holes; 102-a second circular hole; 11-P welding a metal reflecting layer; 12-N welding a metal reflecting layer; 13-ribs; 14-spoon-shaped groove.
Detailed Description
The utility model will be further described with reference to the following detailed description and the accompanying drawings. Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to be limiting of the present patent; for the purpose of better illustrating embodiments of the utility model, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the utility model correspond to the same or similar components; in the description of the present utility model, it should be understood that, if there is an azimuth or positional relationship indicated by terms such as "upper", "lower", "left", "right", etc., based on the azimuth or positional relationship shown in the drawings, it is only for convenience of describing the present utility model and simplifying the description, but it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus terms describing the positional relationship in the drawings are merely illustrative and should not be construed as limitations of the present patent, and specific meanings of the terms described above may be understood by those skilled in the art according to specific circumstances.
As shown in fig. 1-10, a flip-chip LED chip with multiple reflection layers includes a substrate 1, an N-type semiconductor layer 2, a light-emitting quantum well layer 3 and a P-type semiconductor layer 4 are sequentially disposed above the substrate 1 from bottom to top, a spoon-shaped groove 14 is disposed in the middle of the top of the N-type semiconductor layer 2, a rib 13 is disposed at the top edge of the N-type semiconductor layer 2, the rib 13 and the spoon-shaped groove 14 are MESA of a MESA etched to the N-type semiconductor layer 2, and the edge of the substrate 1 is isolation groove etched to the substrate 1.
The middle part on luminous quantum well layer 3 is equipped with first spoon shape hole, the middle part on P type semiconductor layer 4 is equipped with the second spoon shape hole, be equipped with current expansion layer 6 above P type semiconductor layer 4, be equipped with electric current between P type semiconductor layer 4 and the current expansion layer 6 and block DBR reflection layer 5, and further, electric current blocks DBR reflection layer 5 and is circular structure evenly distributed on P type semiconductor layer 4, the middle part on current expansion layer 6 is equipped with the third spoon shape hole, the position and the shape in third spoon shape hole are corresponding with spoon shape groove 14, electric current expansion layer 6 top is equipped with DBR reflection layer 7, conductive metal reflection layer, passivation DBR reflection layer 10 and welded metal reflection layer.
Specifically, the current expansion layer 6 is an ITO transparent conductive layer, and the current blocking DBR reflection layer is 3 groups of SiO 2 With TiO 2 The material is formed by vapor deposition lamination, and the thickness of the material is 400-500nm, so that the material can not only play a role in reflecting light, but also reduce the congestion of current at the first circular holes 71.
In the present embodiment, the DBR reflecting layer 7 covers the current spreading layer 6The upper surface and the side walls of the current spreading layer 6, the N-type semiconductor layer 2, the light emitting quantum well layer 3 and the P-type semiconductor layer 4 and connected to the top edge of the substrate 1, the DBR reflecting layer 7 is provided with a fourth spoon-shaped hole 72 and a first circular hole 71, the position and shape of the first circular hole 71 corresponds to the position and shape of the current blocking DBR reflecting layer 5, and specifically, the DBR reflecting layer 7 is 15 sets of SiO 2 With TiO 2 The material is formed by vapor deposition lamination, the reflectivity is more than 95 percent, and the thickness is 2-3 mu m.
The shape and position of the first, second and fourth scoop holes 72 correspond to the shape and position of the scoop channel 14, and the edge of the fourth scoop hole 72 of the DBR reflective layer 7 extends to the bottom of the scoop channel 14.
The arrangement of the DBR reflecting layer 7 can effectively reduce the leakage current of the chip; only the first circular hole 71 and the fourth spoon hole 72 are leaked, so that the reflection area of the DBR reflection layer can be maximized, and the brightness of the chip can be improved.
The passivation DBR reflection layer 10 covers the upper surface of the conductive metal reflection layer and the side wall of the conductive metal reflection layer and is connected with the edge of the upper surface of the DBR reflection layer 7, the middle part of the passivation DBR reflection layer 10 enters the fourth spoon-shaped hole 72, one side of the passivation DBR reflection layer 10 is provided with a second round hole 102, the other side is provided with three square holes 101, one square hole 101 is arranged at one end of the spoon-shaped groove 14 away from the spoon head, and the other two square holes 101 are arranged at two sides of the spoon-shaped groove 14 away from the spoon head.
Specifically, the passivation DBR reflection layer 10 employs Si0 2 DBR structure, wherein Si0 2 Has a thickness of 1.5-2 μm and DBR of 3 groups of SiO 2 With TiO 2 The material is formed by vapor deposition lamination, and the thickness of the material is 400-500nm.
The arrangement of the passivation DBR reflecting layer 10 can effectively reduce the leakage current of the flip LED chip; only the three square holes 101 and the second circular holes 102 are leaked, so that the reflection area of the passivation DBR reflection layer 10 can be maximized, and the brightness of the flip-chip LED chip can be improved.
The conductive metal reflecting layer comprises an N conductive metal reflecting layer 9 and a P conductive metal reflecting layer 8, the P conductive metal reflecting layer 8 is connected with the current expansion layer 6 through a first circular hole 71 of the DBR reflecting layer 7, the P conductive metal reflecting layer 8 is provided with a fifth spoon-shaped hole, and the position and the shape of the fifth spoon-shaped hole correspond to those of the spoon-shaped groove 14.
The N conductive metal reflecting layer 9 is spoon-shaped, the N conductive metal reflecting layer 9 is located in the fourth spoon-shaped hole 72 of the DBR reflecting layer 7, the lower surface of the N conductive metal reflecting layer 9 is connected with the bottom surface of the spoon-shaped groove 14 of the N-type semiconductor layer 2, and the side wall of the N conductive metal reflecting layer 9 is connected with the DBR reflecting layer 7.
The conductive metal reflecting layer can be an aluminum, chromium, platinum or gold structure or a silver, nickel, platinum or gold structure, and the reflectivity is more than 80%.
The positions of the second circular holes 102 correspond to the positions of the N conductive metal reflecting layers 9, and the positions of the three-square holes 101 correspond to the positions of the end parts of the P conductive metal reflecting layers 8.
The welding metal reflection layer comprises an N welding metal reflection layer 12 and a P welding metal reflection layer 11, wherein the P welding metal reflection layer 11 is positioned at the top of the passivation DBR reflection layer 10 where the square hole 101 is arranged, and the N welding metal reflection layer 12 is positioned at the top of the passivation DBR reflection layer 10 where the second round hole 102 is arranged;
the P-weld metal reflective layer 11 is connected to the P-conductive metal reflective layer 8 through the triangular hole 101, and the N-weld metal reflective layer 12 is connected to the N-conductive metal reflective layer 9 through the second circular hole 102.
The welding metal reflecting layer can be aluminum, chromium, platinum and gold structures or silver, nickel, platinum and gold structures, and the thickness of the welding metal reflecting layer is larger than 2 mu m, so that the welding metal reflecting layer is favorable for the mounting of chips and the heat dissipation of chips in the later stage.
The utility model provides a flip LED chip with a multi-stage reflecting layer, which comprises a substrate 1, wherein an N-type semiconductor layer 2, a light-emitting quantum well layer 3 and a P-type semiconductor layer 4 are sequentially arranged above the substrate 1 from bottom to top, a current expansion layer 6 is arranged above the P-type semiconductor layer 4, a current blocking DBR reflecting layer 5 is arranged between the P-type semiconductor layer 4 and the current expansion layer 6, and a DBR reflecting layer 7, a conductive metal reflecting layer, a passivation DBR reflecting layer 10 and a welding metal reflecting layer are sequentially arranged above the current expansion layer 6 from bottom to top. The LED flip chip has the advantages that the brightness of the chip can be effectively improved through the design of the multistage reflection structure, meanwhile, the DBR reflection layer 7 and the passivation DBR reflection layer 10 are arranged, the leakage current of the flip LED chip can be effectively reduced, the conductive metal reflection layer and the welding metal reflection layer conduct current, the effect of increasing light reflection and heat conduction can be simultaneously achieved, and the reliability of the flip LED chip is effectively improved.
The above embodiments of the present utility model do not limit the scope of the present utility model. Any other corresponding changes and modifications made in accordance with the technical idea of the present utility model shall be included in the scope of the claims of the present utility model.
Claims (6)
1. The flip LED chip with the multi-stage reflecting layer comprises a substrate, an N-type semiconductor layer, a light-emitting quantum well layer and a P-type semiconductor layer are sequentially arranged above the substrate from bottom to top, and the flip LED chip is characterized in that a spoon-shaped groove is formed in the middle of the top of the N-type semiconductor layer, a first spoon-shaped hole is formed in the middle of the light-emitting quantum well layer, a second spoon-shaped hole is formed in the middle of the P-type semiconductor layer, a current expansion layer is arranged above the P-type semiconductor layer, a current blocking DBR reflecting layer is arranged between the P-type semiconductor layer and the current expansion layer, and a DBR reflecting layer, a conductive metal reflecting layer, a passivation DBR reflecting layer and a welding metal reflecting layer are arranged above the current expansion layer;
the DBR reflection layer covers the upper surface of the current expansion layer, the N-type semiconductor layer, the light-emitting quantum well layer and the side wall of the P-type semiconductor layer and is connected with the top edge of the substrate, and is provided with a fourth spoon-shaped hole and a first round hole;
the shape and position of the first spoon-shaped hole, the second spoon-shaped hole and the fourth spoon-shaped hole correspond to those of the spoon-shaped groove, and the edge of the fourth spoon-shaped hole of the DBR reflection layer extends to the bottom of the spoon-shaped groove;
the passivation DBR reflection layer covers the upper surface of conducting metal reflection layer with conducting metal reflection layer's lateral wall and with the marginal junction of the upper surface of DBR reflection layer, passivation DBR reflection layer's middle part gets into in the fourth spoon shape hole, passivation DBR reflection layer's one side is equipped with the circular hole of second, and the opposite side is equipped with three square hole.
2. The flip-chip LED chip with multi-level reflective layer according to claim 1, wherein said current blocking DBR reflective layer is uniformly distributed over said P-type semiconductor layer in a circular shape, the position of said current blocking DBR reflective layer corresponding to the position of said first circular aperture;
the middle part of the current expansion layer is provided with a third spoon-shaped hole, and the position and the shape of the third spoon-shaped hole correspond to those of the spoon-shaped groove.
3. The flip-chip LED chip with multi-level reflective layer according to claim 1, wherein said conductive metal reflective layer comprises an N conductive metal reflective layer and a P conductive metal reflective layer, said P conductive metal reflective layer being connected to said current spreading layer through a first circular aperture of said DBR reflective layer, said P conductive metal reflective layer being provided with a fifth scoop aperture;
the N conductive metal reflecting layer is spoon-shaped, the N conductive metal reflecting layer is positioned in a fourth spoon-shaped hole of the DBR reflecting layer, the lower surface of the N conductive metal reflecting layer is connected with the bottom surface of a spoon-shaped groove of the N-type semiconductor layer, and the side wall of the N conductive metal reflecting layer is connected with the DBR reflecting layer.
4. A flip-chip LED chip with multi-level reflective layer according to claim 3, wherein the second circular hole positions correspond to the N conductive metal reflective layer positions, and the three square holes positions correspond to the P conductive metal reflective layer positions.
5. The flip-chip LED chip with multi-level reflective layer according to claim 4, wherein said solder metal reflective layer comprises an N solder metal reflective layer and a P solder metal reflective layer, said P solder metal reflective layer being on top of where said passivation DBR reflective layer is disposed at said square aperture, said N solder metal reflective layer being on top of where said passivation DBR reflective layer is disposed at said second circular aperture;
the P welding metal reflecting layer is connected with the P conductive metal reflecting layer through three square holes, and the N welding metal reflecting layer is connected with the N conductive metal reflecting layer through the second round holes.
6. The flip-chip LED chip with multiple reflective layers according to claim 1, wherein the current blocking DBR reflective layers are 3 groups of SiO 2 With TiO 2 The material is formed into a current blocking DBR reflecting layer through vapor deposition lamination, and the thickness of the current blocking DBR reflecting layer is 400-500nm;
the DBR reflection layer is 15 groups of SiO 2 With TiO 2 The DBR reflection layer is formed by vapor deposition lamination of materials, and the thickness of the DBR reflection layer is 2-3 mu m;
the passivation DBR reflection layer adopts Si0 2 DBR structure, wherein Si0 2 Has a thickness of 1.5-2 μm and DBR of 3 groups of SiO 2 With TiO 2 The material is formed by vapor deposition lamination, and the thickness of the material is 400-500nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320630207.1U CN218939717U (en) | 2023-03-28 | 2023-03-28 | Flip LED chip with multistage reflecting layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320630207.1U CN218939717U (en) | 2023-03-28 | 2023-03-28 | Flip LED chip with multistage reflecting layer |
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| Publication Number | Publication Date |
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| CN218939717U true CN218939717U (en) | 2023-04-28 |
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| CN202320630207.1U Active CN218939717U (en) | 2023-03-28 | 2023-03-28 | Flip LED chip with multistage reflecting layer |
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