CN218868211U - Time delay reset control circuit - Google Patents
Time delay reset control circuit Download PDFInfo
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- CN218868211U CN218868211U CN202222893981.XU CN202222893981U CN218868211U CN 218868211 U CN218868211 U CN 218868211U CN 202222893981 U CN202222893981 U CN 202222893981U CN 218868211 U CN218868211 U CN 218868211U
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Abstract
The application relates to a time delay reset control circuit belongs to electronic circuit technical field, and it includes: the main control unit outputs a forced reset signal; the key detection unit comprises a key switch, an input end and two output ends, wherein the input end of the key detection unit receives a power supply signal, one output end of the key detection unit outputs a reset signal, the other output end of the key detection unit is connected with the main control unit, and whether the key switch is closed or not determines the level of the reset signal; the control end of the first control unit receives the forced reset signal, the input end of the first control unit is connected with the power supply, the output end of the first control unit is connected with the power supply end of the main control unit, and the first control unit is conducted in a low level mode; the input end of the charging unit receives a reset signal; and the time delay unit, the switch unit and the second control unit. The embedded chip can be controlled to be disconnected with the power supply through the keys so as to achieve the reset function, and the ID structure of the product is not changed.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a delay reset control circuit.
Background
With the continuous development of electronic technology, more and more embedded electronic products go deep into our lives, and the living standard of people is improved, but when the embedded electronic products are used, the main control chip of the embedded electronic products may be in a dead halt state due to the influence of various internal or external factors, so that the embedded electronic products cannot work normally, and the embedded electronic products are wasted.
Keys and key controls are common configurations and functions for embedded type electronic products. The reset circuit is usually added in order to solve the problem that the main control chip can reset when the main control chip is halted, but the ID structure of an electronic product can be changed, or an additional reset chip is added, so that the production cost is greatly increased, or the software is reset, and the main control chip is automatically reset after being placed for a period of time under the control of codes, but the user experience can be influenced and the improvement is needed.
Disclosure of Invention
In order to solve the problem that the product is wasted due to the fact that an electronic product is halted, the application provides a delay reset control circuit.
The application provides a time delay reset control circuit, adopts following technical scheme:
the main control unit outputs a forced reset signal;
the key detection unit comprises a key switch, an input end and two output ends, wherein the input end of the key detection unit receives a power supply signal, one output end of the key detection unit outputs a reset signal, the other output end of the key detection unit is connected with the main control unit, and whether the key switch is closed or not determines the level of the reset signal;
the control end of the first control unit receives the forced reset signal, the input end of the first control unit is connected with a power supply, the output end of the first control unit is connected with the power supply end of the main control unit, and the first control unit is conducted in a low level mode;
the input end of the charging unit receives the reset signal, and the output end of the charging unit is connected with the control end of the first control unit;
the input end of the delay unit is connected with the output end of the charging unit, and the output end of the delay unit is grounded;
the input end of the switch unit is connected with the output end of the key detection unit, one output end of the switch unit is connected with the control end of the second control unit, and the other output end of the switch unit is grounded;
and the input end of the second control unit is connected with the control end of the first control unit, the output end of the second control unit is grounded, and the second control unit is switched on at a high level.
By adopting the technical scheme, when the input forced reset signal is high, the first control unit is cut off, the main control unit is powered off, the main control unit is reset immediately and stops working, when the key is not pressed, the reset signal output by the key detection unit is low level, the reset signal output to the control end of the first control unit through the charging unit is still low level, the first control unit is conducted at the moment, the power supply supplies power for the main control unit, when the key is pressed, the output reset signal is high level, the charging unit charges the delay unit, after the high level reset signal is input, the switching unit is also conducted, and outputs a high level signal to the second control unit, the second control unit is conducted, the delay unit is gradually discharged, the first control unit is normally conducted, the switching unit is also discharged immediately, then the output end of the switching unit is changed into low level, the second control unit is cut off, then the reset signal continues to charge the delay unit through the charging unit, after a period of time, the input end voltage of the delay unit is raised to high level, the first control unit is cut off, thereby the power supply is stopped, the main control unit immediately stops working, the main control unit is reset function is realized, and the electronic product is saved in use, and the use of the product is not required.
Preferably, the key detection unit further includes a first resistor and a second resistor, one end of the key switch is connected to a power supply, the other end of the key switch is connected to one end of the first resistor, the first resistor and the second resistor are connected in series, one end of the second resistor, which is far away from the first resistor, is grounded, a connection node of the key switch and the first resistor outputs a reset signal, and a connection node of the first resistor and the second resistor is connected to the main control unit.
By adopting the technical scheme, when the key switch is not pressed, the reset signal is grounded through the first resistor and the second resistor, the reset signal is at a low level, the main control unit judges that the key is not pressed at the moment through detecting the low level signal of the connecting node of the first resistor and the second resistor, when the key switch is pressed, the power supply is switched on, the reset signal is at a high level, the first resistor is set to be a resistor with a small resistance value, the reset signal is also at a high level after being subjected to voltage division by the first resistor, and the main control unit detects that the voltage signal at the moment is at the high level and judges that the key switch is closed.
Preferably, the power supply further comprises an isolation unit, the isolation unit comprises a diode, the anode of the diode receives a forced reset signal, and the cathode of the diode is connected to the control end of the first control unit.
By adopting the technical scheme, the diode plays a role in isolation and filtering, and the stability of the circuit during operation is improved.
Preferably, the first control unit includes a first MOS transistor, a source of the first MOS transistor is connected to the power supply, a drain of the first MOS transistor is connected to the main control unit, a gate of the first MOS transistor is connected to an output terminal of the charging unit, and the first MOS transistor is a P-MOS transistor.
By adopting the technical scheme, the first MOS tube adopts the P-MOS tube, the working mode is that the low level is conducted, the high level is cut off, and the connection state between the main control unit and the power supply can be controlled.
Preferably, the charging unit includes a third resistor, one end of the third resistor receives a reset signal, and the other end of the third resistor is connected to the input end of the delay unit and the control end of the control unit.
By adopting the technical scheme, the third resistor is a large-resistance storage resistor, and the reset signal charges the charging unit through the third resistor.
Preferably, the delay unit includes a first capacitor, one end of the first capacitor is connected to the output end of the charging unit, and the other end of the first capacitor is grounded.
By adopting the technical scheme, the reasonable capacitance value of the first capacitor is set, and the time from the charging and lifting voltage of the first capacitor to the cut-off level signal of the first control unit determines the reset time of the main control unit.
Preferably, the switch unit includes a second capacitor and a fourth resistor, one end of the second capacitor is connected to the output end of the key detection unit, the second capacitor and the fourth resistor are connected in series, one end of the fourth resistor far from the second capacitor is grounded, and a connection node of the second capacitor and the fourth resistor is connected to the control end of the second control unit.
By adopting the technical scheme, the second capacitor is set to be a small-capacitance-value capacitor, so that the effect of rapid switching can be achieved, and the fourth resistor is a ground resistor, so that the circuit can be protected.
Preferably, the second control unit includes a second MOS transistor, a gate of the second MOS transistor is connected to an output terminal of the switching unit, a source of the second MOS transistor is connected to an output terminal of the charging unit, a drain of the second MOS transistor is grounded, and the second MOS transistor is an N-MOS transistor.
By adopting the technical scheme, the second MOS tube adopts the N-MOS tube, the working mode is high level conduction, low level cut-off, and a discharge loop can be provided for the first capacitor and the second capacitor, so that the circuit is continuously performed.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the high-low level output of the reset signal is controlled by whether the key switch is closed or not, when the key switch is not closed, the reset signal is low level, the first control unit is conducted, the power supply supplies power to the main control unit, when the key switch is closed, the reset signal output is high, the delay unit is charged, the switch unit is conducted and enables the second control unit to be conducted, the delay unit and the switch unit are discharged, the high-level reset signal continues to charge the delay unit until the voltage at one end of the delay unit is raised to the cut-off voltage of the first control unit, the power supply cuts off the power of the main control unit, and the main control unit is reset, so that the reset function of the main control unit is controlled through the keys, the ID structure of a product does not need to be changed, the established effect can be achieved by utilizing the normally-arranged key switch of the product, and the principle is easy to achieve.
2. And a reasonable capacitance value of the first capacitor is set, and the time from the charging and lifting voltage of the first capacitor to the cut-off level signal of the first control unit determines the reset time of the main control unit.
Drawings
Fig. 1 is a circuit connection diagram of a delay reset control circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic block diagram of a delay reset control circuit according to an embodiment of the present application.
Description of the reference numerals: 1. a main control unit; 2. a key detection unit; 3. a first control unit; 4. a charging unit; 5. a delay unit; 6. a switch unit, 7, a second control unit; 8. and an isolation unit.
Detailed Description
The present application is described in further detail below with reference to fig. 1.
The embodiment of the application discloses a delay reset control circuit. Referring to fig. 1, includes:
the main control unit 1 outputs a forced reset signal;
the key detection unit 2 comprises a key switch SW, an input end and two output ends, the input end of the key detection unit 2 receives a power supply signal, one output end of the key detection unit 2 outputs a reset signal, the other output end of the key detection unit 2 is connected with the main control unit 1, and whether the key switch SW is closed or not determines the level of the reset signal;
the control end of the first control unit 3 receives a forced reset signal, the input end of the first control unit 3 is connected with a power supply, the output end of the first control unit 3 is connected with the power supply end of the main control unit 1, and the first control unit 3 is conducted in a low level mode;
the input end of the charging unit 4 receives a reset signal, and the output end of the charging unit 4 is connected with the control end of the first control unit 3;
the input end of the delay unit 5 is connected with the output end of the charging unit 4, and the output end of the delay unit 5 is grounded;
the switch unit 6 comprises an input end and two output ends, the input end of the switch unit 6 is connected with the output end of the key detection unit 2, one output end of the switch unit 6 is connected with the control end of the second control unit 7, and the other output end of the switch unit 6 is grounded;
and an input end of the second control unit 7 is connected with a control end of the first control unit 3, an output end of the second control unit 7 is grounded, and the second control unit 7 is switched on at a high level.
The VBAT is connected to a power supply, and generally adopts a lithium battery for power supply, the RST is a forced reset signal, the HW _ RST is a reset signal, the main control unit 1 is an embedded chip, and the VCC is an embedded power supply.
When a forced reset signal is input to be high, the first control unit 3 is cut off, the main control unit 1 is powered off, the main control unit 1 is reset immediately and stops working, when the key switch SW is not pressed, the HW _ RST signal output by the key detection unit 2 is at a low level, the HW _ RST signal output to the first control unit 3 through the charging unit 4 is still at the low level, at this time, the first control unit 3 is turned on, the power supply supplies power to the main control unit 1, when the key switch SW is pressed, the output HW _ RST signal is at a high level, the charging unit 4 charges the delay unit 5, after the HW _ high level signal is input, the switch unit 6 is also turned on, and outputs a high level signal to the second control unit 7, the second control unit 7 is turned on, the delay unit 5 is gradually discharged, the first control unit 3 is normally turned on, the switch unit 6 is also immediately discharged, then the output end of the switch unit 6 is changed to the low level, the second control unit 7 is cut off, then the HW _ RST signal continues to charge the delay unit 5 through the charging unit 4, after a period of time, the voltage of the delay unit 5 reaches the voltage of the voltage, the main control unit 3, the main control unit 1 is changed, and the main control unit 1 is connected to the main control unit 1, thereby realizing the main control unit 1 is connected to the main control unit, the main control unit 1, and the main control unit is connected to save the main control unit.
The KEY detection unit 2 further comprises a first resistor R1 and a second resistor R2, one end of the KEY switch SW receives a power signal, the other end of the KEY switch SW is connected with one end of the first resistor R1, the first resistor R1 and the second resistor R2 are connected in series, one end, far away from the first resistor R1, of the second resistor R2 is grounded, a connection node of the KEY switch SW and the first resistor R1 outputs a reset signal, the connection node of the first resistor R1 and the second resistor R2 is connected with the main control unit 1 and used for detecting whether the KEY switch SW is pressed down, the KEY is connected with the main control unit 1 and used for detecting the KEY switch SW, and the resistance value of the second resistor R2 is larger than that of the first resistor R1.
When the KEY switch SW is not closed, the HW _ RST signal is grounded through the first resistor R1 and the second resistor R2, at this time, the HW _ RST signal is at a low level, and the main control unit 1 detects that the voltage of a connection node of the first resistor R1 and the second resistor R2 is also at the low level through KEY, which indicates that the KEY switch SW is not closed at this time; when the KEY switch SW is closed, the HW _ RST signal is connected to a power supply through the switch, the HW _ RST signal is at a high level, the resistance value of the second resistor R2 is set to be larger than the resistance value of the first resistor R1, the divided voltage of the first resistor R1 is small, and the main control unit 1 detects that the voltage of the connection node of the first resistor R1 and the second resistor R2 is at the high level through the KEY, which indicates that the KEY switch SW is closed at this time.
The application also comprises an isolation unit 8, a time delay reset control circuit is formed by the first control unit 3, the charging unit 4, the time delay unit 5, the switch unit 6, the second control unit 7 and the isolation unit 8, an overall schematic block diagram formed by the main control unit 1, the key detection unit 2 and the time delay reset control circuit is shown in fig. 2, specifically, the isolation unit 8 comprises a diode D1, the first control unit 3 comprises a first MOS transistor Q1, the charging unit 4 comprises a third resistor R3, the time delay unit 5 comprises a first capacitor C1, the switch unit 6 comprises a second capacitor C2 and a fourth resistor R4, the second control unit 7 comprises a second MOS transistor Q2, the input end of the diode D1 receives a forced reset signal, the output end of the diode D1 is connected with the grid of the first MOS transistor Q1, the source of the first MOS transistor Q1 is connected with a power supply, the drain of the first MOS transistor Q1 is connected to the power supply terminal of the main control unit 1, one end of the third resistor R3 receives a reset signal, the other end of the third resistor R3 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the second capacitor C2 is connected to one end of the third resistor R3 and can receive the reset signal, the other end of the second capacitor C2 is connected to the gate of the second MOS transistor Q2, the source of the second MOS transistor Q2 is connected to the gate of the first MOS transistor Q1, the connection node between the source of the second MOS transistor Q2 and the gate of the first MOS transistor Q1 is connected to the other end of the third resistor R3, the drain of the first MOS transistor Q1 is grounded, the fourth resistor R4 is connected to the second capacitor C2 in series, and the end of the fourth resistor R4, which is far away from the second capacitor C2, is grounded. The first MOS transistor Q1 is a P-MOS transistor, the second MOS transistor Q2 is an N-MOS transistor, the diode D1 can play a role in isolation, the first resistor R1 is a high-resistance resistor, the first capacitor C1 is a high-capacity energy storage capacitor, and the second capacitor C2 is a low-capacity capacitor.
When the input end of the diode D1 receives the forced reset signal and is at a high level, the output end of the diode D1 is also at a high level, and at this time, the voltage flowing into the gate of the first MOS transistor Q1 is also at a high level, because the first MOS transistor Q1 is turned on at a low level and turned off at a high level, the first MOS transistor Q1 is in a turned-off state, and then the source and the drain of the first MOS transistor Q1 are not turned on, i.e., VBAT and VCC are turned off, so that the main control unit 1 has no power input, and the main control unit 1 is immediately reset and stops working. When the HW _ RST signal is input into the charging unit 4, if the key switch is not SW closed, the HW _ RST signal is at a low level, and is also at a low level after passing through the third resistor R3, and the first MOS transistor Q1 is turned on at a low level, then the source and the drain of the first MOS transistor Q1 are turned on, and the power supply can supply power to the main control unit 1; if the key switch SW is closed, the HW _ RST signal changes to a high level, the first capacitor C1 is charged through the third resistor R3, at this time, the first MOS transistor Q1 is not turned on, the second capacitor C2 is turned on instantly, the gate of the second MOS transistor Q2 is connected to a high level signal, the source and the drain of the second MOS transistor Q2 are connected, the first capacitor C1 can discharge through the loop of the second MOS transistor Q2, the fourth resistor R4 is grounded, the second capacitor C2 can also discharge rapidly, the gate input of the second MOS transistor Q2 changes to a low level signal, the second MOS transistor Q2 is turned off, the first MOS transistor Q1 is normally turned on, at this time, the HW _ RST signal continues to charge the first capacitor C1 through the third resistor R3, after a period of time, when the voltage at one end of the first capacitor C1 rises to the high level, the first MOS transistor Q1 is turned off, the main control unit 1 is powered off, reset is realized, and the work is stopped immediately, in the reset process, the time of the main control unit 1 resets the capacitance value of the first capacitor C1.
The above are preferred embodiments of the present application, and the scope of protection of the present application is not limited thereto, so: equivalent changes in structure, shape and principle of the present application shall be covered by the protection scope of the present application.
Claims (8)
1. A delayed reset control circuit, comprising:
a main control unit (1) which outputs a forced reset signal;
a key detection unit (2) comprising a key switch, an input and two outputs, said key being pressed
The input end of the key detection unit (2) receives a power supply signal, one output end of the key detection unit (2) outputs a reset signal, the other output end of the key detection unit is connected with the main control unit (1), and whether the key switch is closed or not determines the level of the reset signal; a first control unit (3), a control end of the first control unit (3) receiving the forced reset
The input end of the first control unit (3) is connected with a power supply, the output end of the first control unit (3) is connected with the power supply end of the main control unit (1), and the first control unit (3) is conducted in a low level mode;
a charging unit (4), an input end of the charging unit (4) receiving the reset signal, the charging
The output end of the electric unit (4) is connected with the control end of the first control unit (3);
a time delay unit (5), wherein the input end of the time delay unit (5) is connected with the output end of the charging unit (4)
The output end of the delay unit (5) is grounded;
a switching unit (6) comprising an input and two outputs, the input of the switching unit (6)
The output end of the key detection unit (2) is connected, one output end of the switch unit (6) is connected with the control end of the second control unit (7), and the other output end of the switch unit (6) is grounded;
the input end of the second control unit (7) is connected with the first control
The control end of the unit (3), the output end of the second control unit (7) is grounded, and the second control unit (7) is conducted in a high level mode.
2. The delay-reset control circuit of claim 1, wherein the key detection unit (2) further comprises a first resistor and a second resistor, one end of the key switch is connected to a power supply, the other end of the key switch is connected to one end of the first resistor, the first resistor and the second resistor are connected in series, one end of the second resistor far away from the first resistor is grounded, a connection node of the key switch and the first resistor outputs a reset signal, and a connection node of the first resistor and the second resistor is connected to the main control unit (1).
3. The delayed reset control circuit of claim 1, further comprising an isolation unit (8), wherein the isolation unit (8) comprises a diode, the anode of the diode receives the forced reset signal, and the cathode of the diode is connected to the control terminal of the first control unit (3).
4. The time delay reset control circuit according to claim 1, wherein the first control unit (3) comprises a first MOS transistor, a source of the first MOS transistor is connected to a power supply, a drain of the first MOS transistor is connected to the main control unit (1), a gate of the first MOS transistor is connected to an output terminal of the charging unit (4), and the first MOS transistor is a P-MOS transistor.
5. The delayed reset control circuit of claim 1 wherein the charging unit (4) comprises a third resistor having one end receiving a reset signal and the other end connected to the input of the delay unit (5) and the control of the control unit.
6. The delayed reset control circuit of claim 1 wherein the delay element (5) comprises a first capacitor having one end connected to the output of the charging element (4) and the other end connected to ground.
7. The delayed reset control circuit as claimed in claim 1, wherein the switching unit (6) comprises a second capacitor and a fourth resistor, one end of the second capacitor is connected to the output terminal of the key detection unit (2), the second capacitor and the fourth resistor are connected in series, one end of the fourth resistor far from the second capacitor is grounded, and a connection node of the second capacitor and the fourth resistor is connected to the control terminal of the second control unit (7).
8. The delay-reset control circuit according to claim 1, wherein the second control unit (7) comprises a second MOS transistor, a gate of the second MOS transistor is connected to one output terminal of the switching unit (6), a source of the second MOS transistor is connected to the output terminal of the charging unit (4), a drain of the second MOS transistor is grounded, and the second MOS transistor is an N-MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222893981.XU CN218868211U (en) | 2022-11-01 | 2022-11-01 | Time delay reset control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222893981.XU CN218868211U (en) | 2022-11-01 | 2022-11-01 | Time delay reset control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218868211U true CN218868211U (en) | 2023-04-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222893981.XU Active CN218868211U (en) | 2022-11-01 | 2022-11-01 | Time delay reset control circuit |
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| Country | Link |
|---|---|
| CN (1) | CN218868211U (en) |
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2022
- 2022-11-01 CN CN202222893981.XU patent/CN218868211U/en active Active
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