CN220290066U - Program-controlled startup and shutdown circuit capable of being forced to shutdown - Google Patents
Program-controlled startup and shutdown circuit capable of being forced to shutdown Download PDFInfo
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- CN220290066U CN220290066U CN202321657065.4U CN202321657065U CN220290066U CN 220290066 U CN220290066 U CN 220290066U CN 202321657065 U CN202321657065 U CN 202321657065U CN 220290066 U CN220290066 U CN 220290066U
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- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Abstract
The utility model provides a program-controlled startup and shutdown circuit capable of being forced to shutdown, which comprises PMOS (P-channel metal oxide semiconductor) transistors Q1 and Q2 and a capacitor C1; the switch KEY S1 is connected with a KEY_INT pin of the singlechip; the switch KEY S1 is also connected with the source electrode of the PMOS tube Q1, the grid electrode of the PMOS tube Q1 is connected with the collector electrode of the triode Q3, and the base electrode of the triode Q3 is connected with the KEY_ON pin of the singlechip; the resistor R4 and the diode D3 are also connected with the drain electrode of the PMOS tube Q2, and the source electrode of the PMOS tube Q2 is connected with the power input end VIN; the grid electrode of the PMOS tube Q2 is connected with the KEY_Power pin of the singlechip, and a capacitor C1 is further connected between the grid electrode and the source electrode of the PMOS tube Q2. The utility model realizes the startup and shutdown by detecting whether the key is pressed or not and switching on or switching off the corresponding control triode Q3; when the key is pressed for a long time, Q2 is turned on, Q1 is turned off, and the system is forced to be shut down.
Description
Technical Field
The utility model relates to the technical field of switching circuits, in particular to a program-controlled switching circuit capable of being forced to be turned off.
Background
In the prior art, in order to prevent a user from touching an on-off key by mistake to cause the device to be turned on or off by mistake, the prior art generally solves the technical problem by adding an on-off delay mode.
At present, a method of integrating a single integrated packaging chip with a peripheral control circuit is commonly used, however, the integrated packaging chip has higher cost, the chip is not programmable, and the delay time is not adjustable; moreover, once the control chip fails, the system cannot be shut down, and the reliability is low; therefore, the existing designs do not meet low cost design requirements and reliability is not stable enough.
Disclosure of Invention
Aiming at the defects of the prior art, the utility model provides a program-controlled startup and shutdown circuit capable of being forced to shutdown.
The technical scheme of the utility model is as follows: a program-controlled startup and shutdown circuit capable of being forced to shutdown comprises a PMOS tube Q1, a PMOS tube Q2, a triode Q3, a switch key S1, a singlechip and a capacitor C1;
one end of the switch KEY S1 is grounded to GND, and the other end of the switch KEY S1 is connected with a KEY_INT pin of the singlechip through a diode D8;
the other end of the switch key S1 is also connected with the source electrode of the PMOS tube Q1 through a resistor R3, and the drain electrode of the PMOS tube Q1 is grounded GND through the resistor R1;
the grid electrode of the PMOS tube Q1 is connected with the collector electrode of the triode Q3 through a resistor R5, and the base electrode of the triode Q3 is connected with the KEY_ON pin of the singlechip through a resistor R7; the emitter of the triode Q3 is grounded GND;
the source electrode of the PMOS tube Q1 is also connected with a switch key S1 through a resistor R4, a diode D3 and a resistor R2;
the resistor R4 and the diode D3 are also connected with the drain electrode of the PMOS tube Q2, and the source electrode of the PMOS tube Q2 is connected with the power input end VIN;
the grid electrode of the PMOS tube Q2 is connected with a KEY_Power pin of the singlechip, and a capacitor C1 is further connected between the grid electrode and the source electrode of the PMOS tube Q2.
Preferably, the drain of the PMOS transistor Q1 is further connected to the power input terminal VIN, and the source of the PMOS transistor Q1 is further connected to the power output terminal Vout.
Preferably, a resistor R6 is further connected between the base and the emitter of the triode Q3.
Preferably, the key_power pin of the singlechip is connected with the gate of the PMOS transistor Q2 through a resistor R8.
Preferably, the key_power pin of the singlechip is connected with the gate of the PMOS transistor Q2 through a diode D5.
Preferably, the model of the singlechip is, but not limited to, STM32F103C8T6.
Preferably, the switch button S1 and the resistor R3 are also connected to a key_power pin of the singlechip.
The beneficial effects of the utility model are as follows:
1. the delay time of the long-time press ON/off is controlled by adjusting the time difference of the single chip microcomputer for detecting the KEY_INT level change and the KEY_ON pin level change; the utility model realizes the startup and shutdown by detecting whether the key is pressed or not and switching on or switching off the corresponding control triode Q3; when the key is pressed for a long time, Q2 is turned on, Q1 is turned off, and the system is forced to be shut down;
2. according to the utility model, the time of forced shutdown can be set by adjusting the capacitance value of the capacitor C1 and the resistance value of the resistor R8, the switch key S1 is pressed for a long time, the capacitor C1 is continuously discharged through the resistor R8, the grid voltage of the PMOS tube Q2 is reduced to a certain value and then reaches the conduction threshold value of the PMOS tube Q2, the Q2 is conducted, the Q1 is cut off, and the system is forced to be powered off and shut down;
drawings
Fig. 1 is a circuit diagram of the present utility model.
Detailed Description
The following is a further description of embodiments of the utility model, taken in conjunction with the accompanying drawings:
as shown in fig. 1, the embodiment provides a program control startup and shutdown circuit capable of forced shutdown, which comprises a PMOS transistor Q1, a PMOS transistor Q2, a triode Q3, a switch button S1, a singlechip and a capacitor C1;
one end of the switch KEY S1 is grounded to GND, and the other end of the switch KEY S1 is connected with a KEY_INT pin of the singlechip through a diode D8;
the other end of the switch key S1 is also connected with the source electrode of the PMOS tube Q1 through a resistor R3, and the drain electrode of the PMOS tube Q1 is grounded GND through the resistor R1;
the grid electrode of the PMOS tube Q1 is connected with the collector electrode of the triode Q3 through a resistor R5, and the base electrode of the triode Q3 is connected with the KEY_ON pin of the singlechip through a resistor R7; the emitter of the triode Q3 is grounded GND;
the source electrode of the PMOS tube Q1 is also connected with a switch key S1 through a resistor R4, a diode D3 and a resistor R2;
the resistor R4 and the diode D3 are also connected with the drain electrode of the PMOS tube Q2, and the source electrode of the PMOS tube Q2 is connected with the power input end VIN;
the grid electrode of the PMOS tube Q2 is connected with a KEY_Power pin of the singlechip, and a capacitor C1 is further connected between the grid electrode and the source electrode of the PMOS tube Q2.
Preferably, the drain of the PMOS transistor Q1 is further connected to the power input terminal VIN, and the source of the PMOS transistor Q1 is further connected to the power output terminal Vout.
As a preferred embodiment, a resistor R6 is further connected between the base and the emitter of the triode Q3.
As the preferred embodiment, the KEY_Power pin of the singlechip is connected with the grid electrode of the PMOS tube Q2 through a resistor R8.
As the preferred embodiment, the KEY_Power pin of the singlechip is connected with the grid electrode of the PMOS tube Q2 through a diode D5.
As preferable in this embodiment, the switch button S1 and the resistor R3 are connected to a key_power pin of the singlechip.
As the preferred model of the embodiment, the model of the singlechip is STM32F103C8T6.
Working principle:
when the switch KEY S1 is pressed, the PMOS tube Q1 is conducted, the whole circuit is powered, after the key_INT pin of the singlechip detects that the switch KEY S1 is pressed for a period of time, the key_ON pin of the singlechip is controlled to output a high level, and the triode Q3 and the PMOS tube Q1 are conducted, at the moment, the switch KEY S1 is released, and the system is powered ON;
when the key_INT pin of the singlechip detects that the switch KEY S1 is pressed for a period of time after the switch KEY S1 is pressed again, controlling the key_ON pin to output a low level, loosening the switch KEY S1 at the moment, cutting off the PMOS tube Q1, and powering off the system; the delay time of the long-time press switch can be controlled by adjusting the time difference of the single chip microcomputer for detecting the KEY_INT level change and the KEY_ON pin level change;
when the system is powered ON and started, but the SCM program runs off, when the control of the KEY_INT and KEY_ON pins fails, the switch KEY S1 is pressed for a long time, the capacitor C1 is continuously discharged through the R8 resistor, the grid voltage of the PMOS tube Q2 is reduced to a certain value and then reaches the conduction threshold value of the PMOS tube Q2, the Q2 is conducted, the Q1 is cut off, and the system is powered off and shut down forcedly; releasing the switch button S1, rapidly charging the capacitor C1 through the diode D5, increasing the voltage of the grid electrode of the PMOS tube Q2, cutting off the PMOS tube Q2, and recovering the circuit system to be normal; the forced shutdown time can be set by adjusting the capacitance value of the capacitor C1 and the resistance value of the resistor R8.
The foregoing embodiments and description have been provided merely to illustrate the principles and best modes of carrying out the utility model, and various changes and modifications can be made therein without departing from the spirit and scope of the utility model as defined in the appended claims.
Claims (7)
1. A program-controlled startup and shutdown circuit capable of being forced to shutdown is characterized in that: the capacitor comprises a PMOS tube Q1, a PMOS tube Q2, a triode Q3, a switch key S1, a singlechip and a capacitor C1;
one end of the switch KEY S1 is grounded to GND, and the other end of the switch KEY S1 is connected with a KEY_INT pin of the singlechip through a diode D8;
the other end of the switch key S1 is also connected with the source electrode of the PMOS tube Q1 through a resistor R3, and the drain electrode of the PMOS tube Q1 is grounded GND through the resistor R1;
the grid electrode of the PMOS tube Q1 is connected with the collector electrode of the triode Q3 through a resistor R5, and the base electrode of the triode Q3 is connected with the KEY_ON pin of the singlechip through a resistor R7; the emitter of the triode Q3 is grounded GND;
the source electrode of the PMOS tube Q1 is also connected with a switch key S1 through a resistor R4, a diode D3 and a resistor R2;
the resistor R4 and the diode D3 are also connected with the drain electrode of the PMOS tube Q2, and the source electrode of the PMOS tube Q2 is connected with the power input end VIN;
the grid electrode of the PMOS tube Q2 is connected with a KEY_Power pin of the singlechip, and a capacitor C1 is further connected between the grid electrode and the source electrode of the PMOS tube Q2.
2. The program-controlled startup and shutdown circuit capable of being forced shutdown according to claim 1, wherein: the drain electrode of the PMOS tube Q1 is also connected with the power input end VIN, and the source electrode of the PMOS tube Q1 is also connected with the power output end Vout.
3. The program-controlled startup and shutdown circuit capable of being forced shutdown according to claim 1, wherein: and a resistor R6 is also connected between the base electrode and the emitter electrode of the triode Q3.
4. The program-controlled startup and shutdown circuit capable of being forced shutdown according to claim 1, wherein: and a KEY_Power pin of the singlechip is connected with the grid electrode of the PMOS tube Q2 through a resistor R8.
5. The program-controlled startup and shutdown circuit capable of being forced shutdown according to claim 1, wherein: and a KEY_Power pin of the singlechip is connected with the grid electrode of the PMOS tube Q2 through a diode D5.
6. The program-controlled startup and shutdown circuit capable of being forced shutdown according to claim 1, wherein: and the switch KEY S1 and the resistor R3 are also connected with a KEY_Power pin of the singlechip.
7. The program-controlled startup and shutdown circuit capable of forced shutdown according to claim 6, wherein: the model of the singlechip is but not limited to STM32F103C8T6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321657065.4U CN220290066U (en) | 2023-06-28 | 2023-06-28 | Program-controlled startup and shutdown circuit capable of being forced to shutdown |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321657065.4U CN220290066U (en) | 2023-06-28 | 2023-06-28 | Program-controlled startup and shutdown circuit capable of being forced to shutdown |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220290066U true CN220290066U (en) | 2024-01-02 |
Family
ID=89329793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321657065.4U Active CN220290066U (en) | 2023-06-28 | 2023-06-28 | Program-controlled startup and shutdown circuit capable of being forced to shutdown |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220290066U (en) |
-
2023
- 2023-06-28 CN CN202321657065.4U patent/CN220290066U/en active Active
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