CN110932706A - Control circuit for avoiding shutdown leakage current of intelligent hardware - Google Patents

Control circuit for avoiding shutdown leakage current of intelligent hardware Download PDF

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Publication number
CN110932706A
CN110932706A CN201911131470.0A CN201911131470A CN110932706A CN 110932706 A CN110932706 A CN 110932706A CN 201911131470 A CN201911131470 A CN 201911131470A CN 110932706 A CN110932706 A CN 110932706A
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China
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diode
resistor
triode
intelligent hardware
cathode
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CN201911131470.0A
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林钊文
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GUANGDONG TELEPOWER COMMUNICATION CO Ltd
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GUANGDONG TELEPOWER COMMUNICATION CO Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region

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Abstract

The invention relates to an energy-saving control circuit, in particular to a control circuit for avoiding shutdown leakage current of intelligent hardware, wherein an emitting electrode of a first triode is connected with a power output end, a collecting electrode of the first triode is respectively connected with a first resistor and a power enable end of the intelligent hardware, and a base electrode of the first triode is connected with a second resistor; the other end of the second resistor is respectively connected with the anode of a third diode and the anode of a fourth diode, and the cathode of the third diode is connected with a switch key for receiving a startup or shutdown control signal; the cathode of the fourth diode is respectively connected with the collector electrodes of the third resistor and the second triode, the other end of the third resistor is connected with the power output end, the base electrode of the second triode is connected with the cathode of the fifth diode, the anode of the fifth diode is connected with the fifth resistor, the other end of the fifth resistor is connected with the GPIO port of the intelligent hardware and used for receiving the high and low levels triggered by the intelligent hardware, and the control circuit cannot generate leakage current when being shut down.

Description

Control circuit for avoiding shutdown leakage current of intelligent hardware
Technical Field
The invention relates to the technical field of energy-saving control circuits, in particular to a control circuit for avoiding shutdown leakage current of intelligent hardware.
Background
With the use of the intelligent hardware becoming more and more extensive, the endurance problem of the intelligent hardware becomes more and more obvious. Most intelligent hardware has two power supply modes: an external adapter and an internal battery. After the intelligent hardware is shut down, the situation that the battery is dead after a period of time still exists, mainly because the hardware circuit of the intelligent hardware is not shut down in a real sense, a part of leakage current still remains, and the energy of the battery is still consumed after the hardware is shut down.
The shutdown leakage current phenomenon widely exists in the existing intelligent hardware, and in order to avoid the shutdown leakage current problem of the intelligent hardware, a circuit with high universality and portability is needed to solve the problem.
Disclosure of Invention
The invention aims to provide a control circuit for avoiding shutdown leakage current of intelligent hardware, which has strong universality and transportability and can not generate leakage current when the intelligent hardware is shut down.
In order to achieve the purpose, the invention provides the following scheme:
a control circuit for avoiding intelligent hardware shutdown leakage current, comprising:
the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first diode, a third diode, a fourth diode and a fifth diode;
an emitting electrode of the first triode is connected with a cathode of a first diode, an anode of the first diode is connected with a power output end, a collector of the first triode is respectively connected with a first resistor and a power enable end of intelligent hardware, the other end of the first resistor is grounded, and a base electrode of the first triode is connected with a resistor R2;
the other end of the second resistor is respectively connected with the anode of a third diode and the anode of a fourth diode, the cathode of the third diode is connected with a switch key and used for receiving a power-on or power-off control signal triggered by the switch key, and the other end of the switch key is grounded; the cathode of the fourth diode is respectively connected with a third resistor and the collector of the second triode, the other end of the third resistor is connected with the power output end, the emitter of the second triode is grounded, the base of the second triode is connected with the cathode of the fifth diode, the anode of the fifth diode is connected with the fifth resistor, the other end of the fifth resistor is connected with the GPIO port of the intelligent hardware and used for receiving the high level or the low level triggered by the intelligent hardware, and a fourth resistor is arranged between the base of the second triode and the collector;
the first triode is a PNP triode, and the second triode is an NPN triode.
Further, the base electrode of the second triode is also connected with the cathode of a sixth diode, the anode of the sixth diode is connected with a sixth resistor, and the other end of the sixth resistor is connected with a USB interface.
Furthermore, the emitting electrode of the first triode is also connected with the cathode of a second diode, and the anode of the second diode is connected with a battery power interface.
Furthermore, the first diode and the second diode are packaged together to form a common-cathode double diode, the fifth diode and the sixth diode are packaged together to form a common-cathode double diode, and the third diode and the fourth diode are packaged together to form a common-anode double diode.
Further, the model of the common cathode double diode is BAT54C, and the model of the common anode double diode is BAT54 AL.
Further, the resistance value of the first resistor is 47 kilo-ohms, the resistance values of the second resistor, the fifth resistor and the sixth resistor are all 4.7 kilo-ohms, the resistance value of the third resistor is 10 kilo-ohms, and the resistance value of the fourth resistor is 1.5 kilo-ohms.
The invention has the beneficial effects that: the invention discloses a control circuit for avoiding shutdown leakage current of intelligent hardware, wherein an emitting electrode of a first triode is connected with a power supply output end, a collecting electrode of the first triode is respectively connected with a first resistor and a power supply enabling end of the intelligent hardware, the other end of the first resistor is grounded, and a base electrode of the first triode is connected with a second resistor; the other end of the second resistor is respectively connected with the anode of a third diode and the anode of a fourth diode, and the cathode of the third diode is connected with a switch key and used for receiving a startup or shutdown control signal triggered by the switch key; the cathode of the fourth diode is respectively connected with the collector electrodes of the third resistor and the second triode, the other end of the third resistor is connected with the power output end, the base electrode of the third resistor is connected with the cathode of the fifth diode, the anode of the fifth diode is connected with the fifth resistor, and the other end of the fifth resistor is connected into the GPIO port of the intelligent hardware and used for receiving the high level or the low level triggered by the intelligent hardware. The control circuit provided by the invention has strong universality and portability, and does not generate leakage current when the intelligent hardware is shut down.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic circuit diagram of a control circuit for avoiding shutdown leakage current of intelligent hardware according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a control circuit based on the improvement of fig. 1 in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, a control circuit for avoiding shutdown leakage current of intelligent hardware according to an embodiment of the present invention includes: the transistor Q1, the transistor Q2, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the diode D1, the diode D3, the diode D4 and the diode D5; an emitter of the triode Q1 is connected with a cathode of the diode D1, an anode of the diode D1 is connected with a power output end, a collector of the triode Q1 is respectively connected with the resistor R1 and a power enable end EN _ VSYS of intelligent hardware, the other end of the resistor R1 is grounded, and a base of the triode Q1 is connected with the resistor R2; the other end of the resistor R2 is respectively connected with the anode of the diode D3 and the anode of the diode D4, the cathode of the diode D3 is connected with the switch KEY PWR _ KEY and is used for receiving a power-on or power-off control signal triggered by the switch KEY PWR _ KEY, and the other end of the switch KEY PWR _ KEY is grounded; the cathode of the diode D4 is respectively connected with the collector of the resistor R3 and the triode Q2, the other end of the resistor R3 is connected with the power output end, the emitter of the triode Q2 is grounded, the base of the triode Q2 is connected with the cathode of the diode D5, the anode of the diode D5 is connected with the resistor R5, the other end of the resistor R5 is connected with a GPIO port of intelligent hardware and used for receiving high level or low level triggered by the intelligent hardware, and a resistor R4 is further arranged between the base of the triode Q2 and the collector; the transistor Q1 is a PNP transistor, and the transistor Q2 is an NPN transistor.
IN this embodiment, when the power output terminal VCC _ IN has a voltage, the intelligent hardware may be started through the power enable terminal EN _ VSYS.
When the switch button PWR _ KEY is pressed, the transistor Q1 is turned on, and the collector of the transistor Q1 is at a high level, so that the power enable terminal EN _ VSYS always outputs a high level. When the switch KEY PWR _ KEY is pressed down, the intelligent hardware is triggered to output a high level through the GPIO port, so that the triode Q2 is switched on, the collector of the triode Q2 is at a low level, the triode Q1 is switched on, and the collector of the triode Q1 maintains the high level. So far, the starting process of the whole control circuit is finished, and the power supply enabling terminal EN _ VSYS always outputs high level to continuously supply power for the intelligent hardware. After the startup is finished, the control circuit does not influence the switching function of the switch KEY PWR _ KEY, and the switch KEY PWR _ KEY can be normally used.
When a shutdown signal is triggered through the switch KEY PWR _ KEY, the control module U2 responds to the shutdown signal to control the GPIO port to output a low level, the GPIO port accessed by the diode D5 is at the low level, the triode Q2 is not conducted, the collector of the triode Q2 is at the high level, the triode Q1 is also not conducted, the collector of the triode Q1 is at the low level, the low level is clamped at the connection point of the triode Q1 and the pull-down resistor R1, so that the EN _ VSYS at the power enable end is maintained at the low level, the power of the intelligent hardware is disconnected, no leakage current is generated, and the control circuit does not consume current. The standby time can be greatly prolonged. In addition, the intelligent hardware can also generate certain radiation when being powered on, and the control circuit provided by the invention can not generate leakage current and radiation when being powered off. When the switch KEY PWR _ KEY is pressed again, the control process of the intelligent hardware is started through the power enable terminal EN _ VSYS, and the intelligent hardware can be restarted.
The control circuit of the invention mainly depends on a GPIO port of intelligent hardware and a switch KEY PWR _ KEY for control, and in the technical field, GPIO (General-purpose input/output) refers to a General I/O port. The intelligent hardware is provided with a GPIO port and a switch KEY PWR _ KEY, so that the method is very high in universality and transportability.
Referring to fig. 2, in a modified embodiment, the base of the transistor Q2 is further connected to the cathode of the diode D6, the anode of the diode D6 is connected to the resistor R6, and the other end of the resistor R6 is connected to the USB interface. The intelligent hardware is provided with the USB interface, so that more power supply access options are added, external input voltage can be accessed through the USB interface, and the USB interface can be a Micro USB interface, a Type-C interface, a B-5Pin interface, a B-4Pin interface, a B-8Pin interface and a B-8Pin-2 x 4 interface.
In a modified embodiment, the emitter of the transistor Q1 is also connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the battery power interface. When the anode of diode D2 is connected to the battery power supply, power can be supplied from the battery power supply, adding a further power supply option.
In an improved embodiment, the diode D1 and the diode D2 are packaged together as a common cathode dual diode, the diode D5 and the diode D6 are packaged together as a common cathode dual diode, and the diode D3 and the diode D4 are packaged together as a common anode dual diode.
In a specific embodiment, the model of the common cathode double diode is BAT54C, and the model of the common anode double diode is BAT54 AL.
According to the common polarity of the diodes, the common anode or common cathode packaging mode is adopted, so that the diodes can have uniform specification under the condition of not changing the characteristics of the diodes, the installation is convenient, and the internal elements are protected.
In a preferred embodiment, the resistor R1 has a resistance of 47 kohms, the resistors R2, R5 and R6 each have a resistance of 4.7 kohms, the resistor R3 has a resistance of 10 kohms and the resistor R4 has a resistance of 1.5 kohms.
To better illustrate the control circuit, IN a typical application, the power enable terminal EN _ VSYS is connected to the power module U1 through a resistor R7, the power module U1 is further provided with a power output terminal VCC _ IN, a USB interface (VCC _ MICRO _ IN port), and a battery power interface (VBAT port), the power module U1 is electrically connected to the control module U2 through the power interface VCC _ SYS, and the control module U2 is provided with a USB interface (VCC _ MICRO _ IN port), a GPIO port, and a switch KEY PWR _ KEY.
The control circuit provided by the invention can not generate leakage current in a standby state and can smoothly switch the on-off state. The working principle is as follows:
the control process for starting the system power supply (triggering the power supply enable terminal EN _ VSYS high level) is as follows:
when inserting power adapter (namely when power output VCC _ IN has the voltage), or when battery powered (namely when the VBAT port inserts the power), can start the power enable end EN _ VSYS of system, specifically can divide into two kinds of situations:
in case one, when the switch PWR _ KEY is pressed, the transistor Q1 is turned on, and the collector of the transistor Q1 is at a high level, thereby activating the power module U1. When the switch KEY PWR _ KEY is pressed, the control module U2 of the intelligent hardware is started, after the control module U2 is started, a high level is output through a GPIO port of the control module U2, so that the triode Q2 is switched on, the collector of the triode Q2 is at a low level, the triode Q1 is switched on, and the collector of the triode Q1 maintains at a high level. So far, the starting process of the whole control circuit is finished, and the power supply enabling end EN _ VSYS of the system always outputs high level to continuously supply power for the intelligent hardware.
And IN case II, when the USB interface is connected with a power supply (namely, when the power supply is connected from a VCC _ MICRO _ IN port), the triode Q2 is conducted, the collector of the triode Q2 is at a low level, the triode Q1 is further conducted, the collector of the triode Q1 maintains a high level, and the power supply enabling end EN _ VSYS of the system always outputs a high level to continuously supply power for intelligent hardware.
After the startup is finished, the control circuit does not influence the switching function of the switch KEY PWR _ KEY, and the switch KEY PWR _ KEY can be normally used.
The control process for turning off the system power (triggering the power enable terminal EN _ VSYS low level) is as follows:
when the switch KEY PWR _ KEY is pressed for a long time and released, a shutdown signal is triggered, the control module U2 responds to the shutdown signal to control the GPIO port to output a low level, at this time, the GPIO port accessed by the diode D5 and the VCC _ MICRO _ IN port accessed by the diode D6 are both low levels, the transistor Q2 is not turned on, the collector of the transistor Q2 is high level, the transistor Q1 is also not turned on, the collector of the transistor Q1 is low level, and the low level state is clamped at the connection point of the transistor Q1 and the pull-down resistor R1, so that the power enable end EN _ VSYS of the power module U1 is maintained at low level, the power of the intelligent hardware is cut off, no leakage current is generated, and the control circuit does not consume current. The standby time can be greatly prolonged. In addition, the intelligent hardware can also generate certain radiation when being powered on, and the control circuit provided by the invention can not generate leakage current and radiation when being powered off.
When the switch button PWR _ KEY is pressed again or the power is accessed from the USB interface, the intelligent hardware can be restarted according to the control process of starting the system power supply (triggering the high level of the power supply enable end EN _ VSYS).
The control circuit of the invention is mainly controlled by depending on GPIO ports and switch KEYs PWR _ KEY of the intelligent hardware, and in the technical field, the intelligent hardware is provided with the GPIO ports and the switch KEYs PWR _ KEY, so the invention has strong universality and portability.
The present disclosure has been made in an effort to provide an understanding of the principles and implementations of the present invention, which are set forth in the following detailed description of the embodiments; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (6)

1. A control circuit for avoiding shutdown leakage current of intelligent hardware, comprising:
the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first diode, a third diode, a fourth diode and a fifth diode;
an emitting electrode of the first triode is connected with a cathode of a first diode, an anode of the first diode is connected with a power output end, a collector of the first triode is respectively connected with a first resistor and a power enable end of intelligent hardware, the other end of the first resistor is grounded, and a base electrode of the first triode is connected with a resistor R2;
the other end of the second resistor is respectively connected with the anode of a third diode and the anode of a fourth diode, the cathode of the third diode is connected with a switch key and used for receiving a power-on or power-off control signal triggered by the switch key, and the other end of the switch key is grounded; the cathode of the fourth diode is respectively connected with a third resistor and the collector of the second triode, the other end of the third resistor is connected with the power output end, the emitter of the second triode is grounded, the base of the second triode is connected with the cathode of the fifth diode, the anode of the fifth diode is connected with the fifth resistor, the other end of the fifth resistor is connected with the GPIO port of the intelligent hardware and used for receiving the high level or the low level triggered by the intelligent hardware, and a fourth resistor is arranged between the base of the second triode and the collector;
the first triode is a PNP triode, and the second triode is an NPN triode.
2. The control circuit for avoiding shutdown leakage current of intelligent hardware according to claim 1, wherein the base of the second triode is further connected to a cathode of a sixth diode, an anode of the sixth diode is connected to a sixth resistor, and the other end of the sixth resistor is connected to the USB interface.
3. The control circuit of claim 1, wherein the emitter of the first transistor is further connected to the cathode of a second diode, and the anode of the second diode is connected to the battery power interface.
4. The control circuit of claim 1, wherein the first diode and the second diode are packaged together as a common-cathode dual diode, the fifth diode and the sixth diode are packaged together as a common-cathode dual diode, and the third diode and the fourth diode are packaged together as a common-anode dual diode.
5. The control circuit of claim 4, wherein the type of the CCD is BAT54C, and the type of the CCD is BAT54 AL.
6. The control circuit according to claim 1, wherein the first resistor has a resistance of 47 kohms, the second resistor, the fifth resistor, and the sixth resistor have a resistance of 4.7 kohms, the third resistor has a resistance of 10 kohms, and the fourth resistor has a resistance of 1.5 kohms.
CN201911131470.0A 2019-11-19 2019-11-19 Control circuit for avoiding shutdown leakage current of intelligent hardware Pending CN110932706A (en)

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CN112130474A (en) * 2020-09-20 2020-12-25 西北工业大学 Separated self-powered circuit and method
CN113176749A (en) * 2021-04-23 2021-07-27 广东天波信息技术股份有限公司 Circuit for avoiding I/O port latch in power-on process of processor

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CN106557142A (en) * 2017-01-17 2017-04-05 淮安信息职业技术学院 Embedded system power on-off control circuit
CN107807586A (en) * 2017-11-30 2018-03-16 苏州切思特电子有限公司 A kind of smart home power consumption control system based on metal-oxide-semiconductor

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Publication number Priority date Publication date Assignee Title
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CN112130474B (en) * 2020-09-20 2022-11-01 西北工业大学 Separated self-powered circuit and method
CN113176749A (en) * 2021-04-23 2021-07-27 广东天波信息技术股份有限公司 Circuit for avoiding I/O port latch in power-on process of processor

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