CN213426125U

CN213426125U - Power-on time delay switch circuit

Info

Publication number: CN213426125U
Application number: CN202022878143.6U
Authority: CN
Inventors: 马胤刚; 蒋辉; 张晓琳
Original assignee: Shenyang Seic Information Technology Co ltd
Current assignee: Shenyang Seic Information Technology Co ltd
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2021-06-11
Anticipated expiration: 2030-12-04

Abstract

The utility model provides a go up time delay switch circuit, including time base circuit U1, voltage conversion chip U2, triode Q1, triode Q2, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, inductance L1. The utility model provides a go up electric delay switch circuit, whether the output voltage of power supply chip is controlled through the change of the discharge of last electric capacity back electric capacity in time basic circuit's output state, played last electric delay switch circuit effect, for the reduction consumption among the solution prior art, the operating condition of controlling the part module through control power supply time has increased corresponding timing work for the data processing chip, has increased the working strength of data processing chip and the technical problem of consumption.

Description

Power-on time delay switch circuit

Technical Field

The utility model relates to an go up electric delay switch circuit belongs to consumption control circuit technical field.

Background

With the increasing demand for low power consumption of the device, a data processing chip with lower power consumption is forced to be selected, the working time of some data acquisition modules is controlled, and the data acquisition modules are powered off under an unnecessary state, so that the power consumption is reduced, but a large amount of timing work is added to the data processing chip, and for the data processing chip with low power consumption, the increase of the workload means the increase of the power consumption.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, an object of the present invention is to provide an upper electric delay switch circuit, and the concrete technical scheme is:

a power-on time delay switch circuit comprises a time base circuit U1 and a voltage conversion chip U2, wherein a TRIG pin of the time base circuit U1 is connected with a collector of a triode Q2, the collector of the triode Q2 is connected with a 5V voltage positive electrode input end through a resistor R4, an emitter of a triode Q2 is grounded, a base of the triode Q2 is connected with the resistor R5, the other end of the R5 is connected with a negative electrode of a capacitor C5, and a positive electrode of the capacitor C5 is connected with the 5V voltage positive electrode input end; the THR pin of the time base circuit U1 is connected with the anode of a capacitor C4, the cathode of the capacitor C4 is grounded, the anode of the capacitor C4 is connected with a resistor R3, the other end of the resistor R3 is connected with the 5V voltage anode input end, and the THR pin of the time base circuit U1 is connected with the DISC pin; the CVOLT pin of the time-base circuit U1 is grounded through a capacitor C3, the RST pin and the VCC pin of the time-base circuit U1 are connected with the 5V voltage positive electrode input end, and the GND pin of the time-base circuit U1 is grounded; an OUT pin of the time-base circuit U1 is connected with a base electrode of a triode Q1 through a resistor R2, the base electrode of the triode Q1 is grounded through a resistor R1, a collector electrode of the triode Q1 is connected with a 5V voltage positive electrode input end, and an emitter electrode of the triode Q2 is grounded through a resistor R7 and a resistor R6 which are connected in series; the EN pin of the voltage conversion chip U2 is connected between a resistor R7 and a resistor R6, the VIN pin of the voltage conversion chip U2 is connected with the 5V voltage positive input end, the VOUT pin of the voltage conversion chip U2 is connected to the 3.3V voltage output end through an inductor L1, and the GND pin of the voltage conversion chip U2 is grounded.

Preferably, the positive electrode of the capacitor C5 and the emitter of the transistor Q2 are respectively connected with a parallel circuit formed by connecting the capacitor C1 and the capacitor C2 in parallel.

Further, the VIN pin and the GND pin of the voltage conversion chip U2 are respectively connected to a parallel circuit in which the capacitor C6 and the capacitor C7 are connected in parallel.

Furthermore, the input end of the inductor L1 and the GND pin of the voltage conversion chip U2 are respectively connected with a parallel circuit in which a capacitor C8 and a capacitor C9 are connected in parallel.

Preferably, the specification model of the time base circuit U1 is NE 555.

Preferably, the specification model of the voltage conversion chip U2 is XC6209F332 MR.

The utility model discloses can reduce the unnecessary consumption that produces of data acquisition module, time delay automatic power off reduces data processing chip's work load and consumption.

Drawings

Fig. 1 is a circuit diagram of an upper power delay switch circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, a power-on delay switch circuit includes a time base circuit U1 and a voltage conversion chip U2, a TRIG pin of the time base circuit U1 is connected with a collector of a transistor Q2, the collector of the transistor Q2 is connected with a 5V voltage positive input terminal through a resistor R4, an emitter of the transistor Q2 is grounded, a base of the transistor Q2 is connected with the resistor R5, the other end of the resistor R5 is connected with a negative electrode of a capacitor C5, and a positive electrode of the capacitor C5 is connected with the 5V voltage positive input terminal; the THR pin of the time base circuit U1 is connected with the anode of a capacitor C4, the cathode of the capacitor C4 is grounded, the anode of the capacitor C4 is connected with a resistor R3, the other end of the resistor R3 is connected with the 5V voltage anode input end, and the THR pin of the time base circuit U1 is connected with the DISC pin; the CVOLT pin of the time-base circuit U1 is grounded through a capacitor C3, the RST pin and the VCC pin of the time-base circuit U1 are connected with the 5V voltage positive electrode input end, and the GND pin of the time-base circuit U1 is grounded; an OUT pin of the time-base circuit U1 is connected with a base electrode of a triode Q1 through a resistor R2, the base electrode of the triode Q1 is grounded through a resistor R1, a collector electrode of the triode Q1 is connected with a 5V voltage positive electrode input end, and an emitter electrode of the triode Q2 is grounded through a resistor R7 and a resistor R6 which are connected in series; the EN pin of the voltage conversion chip U2 is connected between a resistor R7 and a resistor R6, the VIN pin of the voltage conversion chip U2 is connected with the 5V voltage positive input end, the VOUT pin of the voltage conversion chip U2 is connected to the 3.3V voltage output end through an inductor L1, and the GND pin of the voltage conversion chip U2 is grounded. The specification model of the time-base circuit U1 is NE555, and the specification model of the voltage conversion chip U2 is XC6209F332 MR.

And the positive electrode of the capacitor C5 and the emitter of the triode Q2 are respectively connected with a parallel circuit formed by connecting the capacitor C1 and the capacitor C2 in parallel. The VIN pin and the GND pin of the voltage conversion chip U2 are respectively connected with a parallel circuit formed by connecting a capacitor C6 and a capacitor C7 in parallel. The input end of the inductor L1 and the GND pin of the voltage conversion chip U2 are respectively connected with a parallel circuit formed by connecting a capacitor C8 and a capacitor C9 in parallel.

The principle of the power-on delay switch circuit is as follows: when the circuit is powered on, a power supply 5V charges a capacitor C5 through C5, R5 and the base electrode of a triode Q2, at the moment, the triode Q2 is in saturated conduction, and the collector electrode of the triode Q2 outputs low level; as the charging of C5 proceeds, the voltage on the capacitor C5 gradually increases, the charging current gradually decreases, and the potential at the base of the transistor Q2 gradually decreases. When the voltage of the capacitor C5 is charged to be close to the 5V power voltage, the potential of the base of the transistor Q2 gradually decreases to be close to 0V, the transistor Q2 is cut off, the charging of the capacitor C5 is finished, and the collector of the transistor Q2 outputs high level. That is, during the short time of the initial power-up period of the circuit, a negative pulse is generated at the collector of the transistor Q2, and the width of the negative pulse is determined by the values of the resistor R1 and the capacitor C1. The negative pulse is input to a TRIG pin of the time-base circuit U1 to trigger a monostable circuit consisting of the time-base circuit U1 to overturn, so that an OUT pin of the time-base circuit U1 outputs high level, and the monostable circuit is changed from a steady state to a transient steady state. The triode Q1 is conducted by the high level output by the OUT pin of the time-base circuit U1, the EN pin of the voltage conversion chip U2 acquires the high level, and the voltage conversion chip U2 works to output 3.3V voltage. The time-base circuit U1 charges the capacitor C4 from the 5V power supply through R3 during the transient time, so that the voltage on the capacitor C4 gradually rises. With the charging, when the voltage on the capacitor C4 gradually increases to 2/3 × 5V, the state of the time-base circuit U1 is reversed, the transient state is changed to the steady state, the OUT pin of the time-base circuit U1 outputs a low level, the transistor Q1 is turned off, the EN pin of the voltage conversion chip U2 collects the low level, the voltage conversion chip U2 is disabled, and no voltage is output. The voltage output time Td of the voltage conversion chip U2 is 1.1 × R1 × C1, and Td is equal to about 240 seconds. The voltage conversion chip U2 outputs 3.3V voltage for 240 seconds after power-on, and the output voltage is automatically stopped after 240 seconds. The circuit is powered off and then powered on before data is read every time, so that the data acquisition module can obtain the time of about 240s of power supply, data acquisition is carried out in the period, after the time is up, the state of the time-base circuit is changed, the voltage conversion chip is disabled, and the acquisition module is powered off.

The utility model provides a go up electric delay switch circuit, whether the output voltage of power supply chip is controlled through the change of the discharge of last electric capacity back electric capacity in time basic circuit's output state, played last electric delay switch circuit effect, for the reduction consumption among the solution prior art, the operating condition of controlling the part module through control power supply time has increased corresponding timing work for the data processing chip, has increased the working strength of data processing chip and the technical problem of consumption.

Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.

Claims

1. A power-on time delay switch circuit, comprising: the circuit comprises a time-base circuit U1 and a voltage conversion chip U2, wherein a TRIG pin of the time-base circuit U1 is connected with a collector of a triode Q2, the collector of the triode Q2 is connected with a 5V voltage positive input end through a resistor R4, an emitter of the triode Q2 is grounded, a base of the triode Q2 is connected with the resistor R5, the other end of the R5 is connected with a negative electrode of a capacitor C5, and a positive electrode of the capacitor C5 is connected with the 5V voltage positive input end; the THR pin of the time base circuit U1 is connected with the anode of a capacitor C4, the cathode of the capacitor C4 is grounded, the anode of the capacitor C4 is connected with a resistor R3, the other end of the resistor R3 is connected with the 5V voltage anode input end, and the THR pin of the time base circuit U1 is connected with the DISC pin; the CVOLT pin of the time-base circuit U1 is grounded through a capacitor C3, the RST pin and the VCC pin of the time-base circuit U1 are connected with the 5V voltage positive electrode input end, and the GND pin of the time-base circuit U1 is grounded; an OUT pin of the time-base circuit U1 is connected with a base electrode of a triode Q1 through a resistor R2, the base electrode of the triode Q1 is grounded through a resistor R1, a collector electrode of the triode Q1 is connected with a 5V voltage positive electrode input end, and an emitter electrode of the triode Q2 is grounded through a resistor R7 and a resistor R6 which are connected in series; the EN pin of the voltage conversion chip U2 is connected between a resistor R7 and a resistor R6, the VIN pin of the voltage conversion chip U2 is connected with the 5V voltage positive input end, the VOUT pin of the voltage conversion chip U2 is connected to the 3.3V voltage output end through an inductor L1, and the GND pin of the voltage conversion chip U2 is grounded.

2. A power-up delay switch circuit as claimed in claim 1, wherein: and the positive electrode of the capacitor C5 and the emitter of the triode Q2 are respectively connected with a parallel circuit formed by connecting the capacitor C1 and the capacitor C2 in parallel.

3. A power-up delay switch circuit as claimed in claim 2, wherein: the VIN pin and the GND pin of the voltage conversion chip U2 are respectively connected with a parallel circuit formed by connecting a capacitor C6 and a capacitor C7 in parallel.

4. A power-up delay switch circuit as claimed in claim 3, wherein: the input end of the inductor L1 and the GND pin of the voltage conversion chip U2 are respectively connected with a parallel circuit formed by connecting a capacitor C8 and a capacitor C9 in parallel.

5. A power-up delay switch circuit as claimed in claim 1, wherein: the specification model of the time-base circuit U1 is NE 555.

6. A power-up delay switch circuit as claimed in claim 1, wherein: the specification model of the voltage conversion chip U2 is XC6209F332 MR.