CN220137574U - Circuit for controller idle timing dormancy - Google Patents
Circuit for controller idle timing dormancy Download PDFInfo
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- CN220137574U CN220137574U CN202321682820.4U CN202321682820U CN220137574U CN 220137574 U CN220137574 U CN 220137574U CN 202321682820 U CN202321682820 U CN 202321682820U CN 220137574 U CN220137574 U CN 220137574U
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- 230000005059 dormancy Effects 0.000 title claims abstract description 22
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 20
- 230000007958 sleep Effects 0.000 claims description 10
- 238000012360 testing method Methods 0.000 abstract description 16
- 230000003321 amplification Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model discloses a circuit for idle timing dormancy of a controller, which comprises a first power supply (V1), a second power supply (V2), a buck chip (DCDC), a controller (MCU), a first MOS switch (Q1), a second MOS switch (Q2), an NPN triode (Q3), a third resistor (R3) and a timing chip (U1), wherein the first MOS switch (Q1) and the second MOS switch (Q2) are used for controlling the on-off of a power supply loop of a product, the controller (MCU) is used for controlling the power supply loop and controlling dormancy and awakening of a system, and the timing chip (U1) is used for timing hardware and providing dormancy signals for the controller (MCU). Through the technical scheme, the power-off and the dormancy of the controller (MCU) can be realized when the product is idle, and when the test is needed, the power-on of the controller (MCU) is used for enabling the product to be supplied with power again for testing.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to a circuit for controller idle timing dormancy.
Background
In modern industrial manufacturing, product performance often needs to be tested, in traditional test projects, a conventional test circuit is not powered off immediately after product testing is completed, a controller and a product can still be powered on continuously for one day or more after the completion of testing of some test products, power consumption can be increased under the condition, and electric quantity waste is serious. Therefore, the existing product test circuit has the technical defects that the product is not powered off immediately after the test is finished and serious electric quantity waste is caused.
Disclosure of Invention
The utility model provides a circuit for idle and timing dormancy of a controller, which aims to solve the technical defects that an existing product testing circuit has the technical defects that a product is not powered off immediately after the testing is finished and the electric quantity is seriously wasted.
A circuit for controller idle timing dormancy comprises a first power supply (V1), a second power supply (V2), a step-down chip (DCDC), a controller (MCU), a first MOS switch (Q1), a second MOS switch (Q2), an NPN triode (Q3), a timing chip (U1) and a third resistor (R3); the source electrode of the first MOS switch (Q1) is connected with a power supply (V1), the drain electrode of the first MOS switch (Q1) is connected with one end of the buck chip (DCDC), and the grid electrode of the first MOS switch (Q1) is connected with the drain electrode of the second MOS switch (Q2); the source electrode of the second MOS switch (Q2) is grounded, and the grid electrode of the second MOS switch (Q2) is connected with the fifth pin of the controller (MCU); the other end of the step-down chip (DCDC) is connected with one end of a product, and a fourth pin of the controller (MCU) is connected with the other end of the product; the base electrode of the NPN type triode (Q3) is connected with a third pin of the controller (MCU), the collector electrode of the NPN type triode (Q3) is connected with a second pin and an eighth pin of the timing chip (U1), and the emitter electrode of the NPN type triode (Q3) is connected with a first pin of the timing chip (U1); the sixth pin of timing chip (U1) with the second pin of controller (MCU) is connected, the fourth pin, the seventh pin of timing chip (U1) ground connection, the fifth pin of timing chip (U1) with second power (V2) is connected, the sixth pin of timing chip (U1) with one end of third resistance (R3) is connected and is formed first connecting point, first connecting point with the second pin of controller (MCU) is connected, the other end of third resistance (R3) with second power (V2) is connected.
Preferably, the timing chip (U1) is further connected with a potentiometer resistor (R1) and a second resistor (R2), the potentiometer resistor (R1) is connected with the second resistor (R2) in parallel, one end of the potentiometer resistor (R1) is connected with a second pin of the timing chip (U1), the other end of the potentiometer resistor (R1) is connected with a third pin of the timing chip (U1) to form a second connection point, and the second connection point is grounded.
Preferably, a ninth capacitor is disposed between the second connection point and the ground terminal.
Preferably, a fifth resistor (R5) is provided between the gate of the first MOS switch (Q1) and the drain of the second MOS switch (Q2).
Preferably, a fourth resistor (R4) is disposed between the first MOS switch (Q1) and the first power supply (V1), one end of the fourth resistor (R4) is connected to the first power supply (V1) and the source of the first MOS switch (Q1), and the other end of the fourth resistor (R4) is connected to the gate of the first MOS switch (Q1) and one end of the fifth resistor (R5).
Preferably, the circuit further includes a sixth resistor (R6), one end of the sixth resistor (R6) is connected to the fifth pin of the controller (MCU) and the gate of the second MOS switch (Q2), and the other end of the sixth resistor (R6) is connected to the source of the second MOS switch (Q2) and then grounded.
Preferably, a connection point between the other end of the buck chip (DCDC) and one end of the product is connected to a first connection end of the capacitor bank, and a second connection end of the capacitor bank is grounded.
The capacitor bank comprises a plurality of sub-capacitors which are respectively connected in parallel between a first connecting end and a second connecting end of the capacitor bank.
Preferably, the first pin and the sixth pin of the controller (MCU) are connected with the third power supply (V3), a control switch (K) for on-off control is further arranged between the sixth pin and the third power supply, and the sixth pin of the controller (MCU) is a pin for acquiring a wake-up signal.
The utility model discloses a circuit for idle timing dormancy of a controller, which comprises a first power supply (V1), a second power supply (V2), a buck chip (DCDC), a controller (MCU), a first MOS switch (Q1), a second MOS switch (Q2), an NPN triode (Q3), a third resistor (R3) and a timing chip (U1), wherein the first MOS switch (Q1) and the second MOS switch (Q2) are used for controlling the on-off of a power supply loop of a product, the NPN triode (Q3) plays a role of current amplification and switching, the controller (MCU) is used for controlling the dormancy and the awakening of the power supply loop and controlling the system, and the timing chip (U1) is used for timing hardware and providing dormancy signals for the controller (MCU). Through the technical scheme, the power-off and the dormancy of the controller (MCU) can be realized when the product is idle, and when the product needs to be tested, the power-on of the controller (MCU) is used for enabling the product to be supplied with power again for testing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit configuration diagram of a controller for idle timing sleep according to an embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
The present utility model is not limited to the above embodiments, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the present utility model, and these modifications and substitutions are intended to be included in the scope of the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
The utility model discloses a circuit for controller idle timing dormancy, which comprises a first power supply V1, a second power supply V2, a step-down chip DCDC, a controller MCU, a first MOS switch Q1, a second MOS switch Q2, an NPN triode Q3, a third resistor R3 and a timing chip U1, as shown in figure 1.
The source of the first MOS switch Q1 is connected to the power supply V1, the drain of the first MOS switch Q1 is connected to one end of the buck chip DCDC, and the gate of the first MOS switch Q1 is connected to the drain of the second MOS switch Q2; the source electrode of the second MOS switch Q2 is grounded, the grid electrode of the second MOS switch Q2 is connected with the fifth pin of the controller MCU, when testing is needed, the fifth pin of the controller MCU outputs a drive_control high-level signal, the voltage of the second MOS switch Q2 is larger than the starting voltage, the second MOS switch Q2 is in a conducting state, and the first MOS switch Q1 and the second MOS switch Q2 are used for controlling the on-off of a power supply loop of a product; the other end of the step-down chip DCDC is connected with one end of a product, the fourth pin of the controller MCU is connected with the other end of the product, the product is in an idle state after the product is tested, at the moment, the product sends a high-level Test completion Signal to the fourth pin of the MCU through a test_Signal Signal, and the MCU sets EN_control of the third pin to be high level after receiving the Signal; the base of the NPN triode Q3 is connected with a third pin of the controller MCU, the collector of the NPN triode Q3 is connected with a second pin and an eighth pin of the timing chip U1, the emitter of the NPN triode Q3 is connected with a first pin of the timing chip U1, the NPN triode Q3 plays roles of current amplification and switching, the EN_control of the third pin is set to be high level after the MCU receives a signal, the NPN triode Q3 is conducted, the high level of Vref is output to the first pin Trigger pin of the timing chip U1, and the timing chip U1 starts timing.
The sixth pin of the timing chip U1 is connected with the second pin of the controller MCU, the fourth pin and the seventh pin of the timing chip U1 are grounded, the fifth pin of the timing chip U1 is connected with the second power supply V2, the second power supply V2 supplies power to the timing chip U1, the timing chip U1 is used for timing hardware and providing a sleep signal to the controller MCU, the sixth pin of the timing chip U1 is connected with one end of the third resistor R3 to form a first connection point, the third resistor R3 is used for shunting current and protecting the timing chip U1, the first connection point is connected with the second pin of the controller MCU, and the other end of the third resistor R3 is connected with the second power supply V2, and the controller MCU is used for controlling a power supply loop and controlling the sleep and the wake-up of the system. After the timing Time reaches the preset Time, the timing chip U1 sends a low level to the second pin of the controller MCU through the sixth pin Time_trigger, the second pin of the controller MCU triggers an interrupt after receiving the low level, then a drive_control signal output by the fifth pin of the controller MCU is pulled to the low level from the high level, the drive_control signal of the low level is transmitted to the second MOS switch Q2, the product is powered down, and then the controller MCU also enters a dormant state.
The timing chip U1 is also connected with a potentiometer resistor R1 and a second resistor R2, the potentiometer resistor R1 is connected with the second resistor R2 in parallel, one end of the potentiometer resistor R1 is connected with a second pin of the timing chip U1, the other end of the potentiometer resistor R1 is connected with a third pin of the timing chip U1 to form a second connection point, and the second connection point is grounded; by adjusting the external potentiometer resistor R1, the timing time can be set, and the larger the set potentiometer resistor value is, the longer the timing time of the timing chip U1 is.
Preferably, a ninth capacitor is disposed between the second connection point and the ground terminal.
Preferably, a fifth resistor R5 is disposed between the gate of the first MOS switch Q1 and the drain of the second MOS switch Q2.
A fourth resistor R4 is disposed between the first MOS switch Q1 and the first power supply V1, one end of the fourth resistor R4 is connected to the first power supply V1 and the source of the first MOS switch Q1, the other end of the fourth resistor R4 is connected to the gate of the first MOS switch Q1 and one end of the fifth resistor R5, and the fourth resistor R4 can shunt current and protect the first MOS switch Q1.
The circuit further comprises a sixth resistor R6, one end of the sixth resistor R6 is connected with a fifth pin of the controller MCU and the grid electrode of the second MOS switch Q2, the other end of the sixth resistor R6 is connected with the source electrode of the second MOS switch Q2 and then grounded, and the sixth resistor R6 can shunt current and protect the second MOS switch Q2.
The other end of the step-down chip DCDC is connected with the first connecting end of the capacitor bank through a connecting point of one end of the product, the second connecting end of the capacitor bank is grounded, the capacitor bank has a filtering function, and the charging and discharging characteristics of the capacitor can convert the pulsating direct current voltage in the circuit into relatively stable direct current voltage so as to filter high frequency and impulse interference.
The capacitor bank comprises a plurality of sub-capacitors which are respectively connected in parallel between the first connecting end and the second connecting end of the capacitor bank, and the plurality of sub-capacitors are grounded after being connected in parallel, and in the embodiment, the number of the capacitors in the capacitor bank is selected to be eight, and the capacitance is 100 microfarads.
The first pin and the sixth pin of the controller MCU are connected with a third power supply, the third power supply is in a 3V3 high level, a control switch K for carrying out on-off control is further arranged between the sixth pin and the third power supply, the sixth pin of the controller MCU is a pin for acquiring a wake-up signal, when a wake-up circuit is needed to be retested, the switch is pressed down, the 3V3 high level is received by the sixth pin of the controller MCU, the controller MCU is awakened from a dormant state, and the load is retested.
In a specific embodiment, when a product needs to be tested, a fifth pin of the controller MCU outputs a drive_control high level Signal, the voltage of the second MOS switch Q2 is larger than the starting voltage, the second MOS switch Q2 is in a conducting state, the product is electrified and tested, and is in an idle state after the product is tested, at this Time, the product sends a test_signal Signal and sends a high level Test completion Signal to a fourth pin of the MCU, the MCU receives the Signal and then sets an EN_control Signal of the third pin to be high level, the NPN triode Q3 is conducted, and outputs a high level of Vref to a first pin Trigger pin of the timing chip U1, the timing chip U1 starts timing, after the timing Time reaches a preset Time, the timing chip U1 sends a low level to a second pin of the controller MCU through a sixth pin time_trigger, the second pin of the controller MCU receives the low level and then sends the drive_control Signal of the fifth pin of the controller MCU to be low level, and then the drive_control Signal of the fifth pin of the controller MCU is pulled to the low level from the high level to the low level, and the drive_control Signal of the second MOS switch Q1 is sent to the MCU to the sleep state, and the product is also sent to the sleep state; when the circuit is required to be awakened and retested, the switch of the controller MCU is pressed, the sixth pin of the controller MCU receives 3V3 high level, the controller MCU is awakened from the dormant state, and the load product is retested.
The utility model discloses a circuit for idle timing dormancy of a controller, which comprises a first power supply (V1), a second power supply (V2), a buck chip (DCDC), a controller (MCU), a first MOS switch (Q1), a second MOS switch (Q2), an NPN triode (Q3), a third resistor (R3) and a timing chip (U1), wherein the first MOS switch (Q1) and the second MOS switch (Q2) are used for controlling the on-off of a power supply loop of a product, the NPN triode (Q3) plays a role of current amplification and switching, the controller (MCU) is used for controlling the dormancy and the awakening of the power supply loop and controlling the system, and the timing chip (U1) is used for timing hardware and providing dormancy signals for the controller (MCU). Through the technical scheme, the power-off and the dormancy of the controller (MCU) can be realized when the product is idle, and when the product needs to be tested, the power-on of the controller (MCU) is used for enabling the product to be supplied with power again for testing, so that the power consumption of the product in an idle state is reduced, and the purpose of saving power is achieved.
While the utility model has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
Claims (9)
1. The circuit for the controller idle timing dormancy is characterized by comprising a first power supply (V1), a second power supply (V2), a step-down chip (DCDC), a controller (MCU), a first MOS switch (Q1), a second MOS switch (Q2), an NPN triode (Q3), a timing chip (U1) and a third resistor (R3);
the source electrode of the first MOS switch (Q1) is connected with a power supply (V1), the drain electrode of the first MOS switch (Q1) is connected with one end of the buck chip (DCDC), and the grid electrode of the first MOS switch (Q1) is connected with the drain electrode of the second MOS switch (Q2);
the source electrode of the second MOS switch (Q2) is grounded, and the grid electrode of the second MOS switch (Q2) is connected with the fifth pin of the controller (MCU);
the other end of the step-down chip (DCDC) is connected with one end of a product, and a fourth pin of the controller (MCU) is connected with the other end of the product;
the base electrode of the NPN type triode (Q3) is connected with a third pin of the controller (MCU), the collector electrode of the NPN type triode (Q3) is connected with a second pin and an eighth pin of the timing chip (U1), and the emitter electrode of the NPN type triode (Q3) is connected with a first pin of the timing chip (U1);
the sixth pin of timing chip (U1) with the second pin of controller (MCU) is connected, the fourth pin, the seventh pin of timing chip (U1) ground connection, the fifth pin of timing chip (U1) with second power (V2) is connected, the sixth pin of timing chip (U1) with one end of third resistance (R3) is connected and is formed first connecting point, first connecting point with the second pin of controller (MCU) is connected, the other end of third resistance (R3) with second power (V2) is connected.
2. The circuit for controller idle timing dormancy according to claim 1, wherein a potentiometer resistor (R1) and a second resistor (R2) are further connected to the timing chip (U1), the potentiometer resistor (R1) is connected in parallel with the second resistor (R2), one end of the potentiometer resistor (R1) is connected to a second pin of the timing chip (U1), the other end of the potentiometer resistor (R1) is connected to a third pin of the timing chip (U1) to form a second connection point, and the second connection point is grounded.
3. A circuit for controller idle timing sleep as claimed in claim 2, characterized in that a ninth capacitance is arranged between the second connection point and ground.
4. A circuit for controller idle timing sleep as claimed in claim 1, characterized in that, a fifth resistor (R5) is arranged between the gate of the first MOS switch (Q1) and the drain of the second MOS switch (Q2).
5. The circuit for controller idle timing dormancy according to claim 4, wherein a fourth resistor (R4) is disposed between the first MOS switch (Q1) and the first power supply (V1), one end of the fourth resistor (R4) is connected to the first power supply (V1) and the source of the first MOS switch (Q1), and the other end of the fourth resistor (R4) is connected to the gate of the first MOS switch (Q1) and one end of the fifth resistor (R5).
6. A circuit for controller idle timing sleep as claimed in claim 1, characterized in that, the circuit further comprises a sixth resistor (R6), one end of the sixth resistor (R6) is connected to the fifth pin of the controller (MCU) and the gate of the second MOS switch (Q2), and the other end of the sixth resistor (R6) is connected to the source of the second MOS switch (Q2) and then grounded.
7. A circuit for controller idle timing sleep as claimed in claim 1, characterized in that, the connection point of the other end of the buck chip (DCDC) to one end of the product is connected to a first connection of a capacitor bank, a second connection of which is grounded.
8. The circuit for controller idle timing sleep of claim 7, wherein the capacitor bank includes a plurality of sub-capacitances connected in parallel between the first and second connection terminals of the capacitor bank, respectively.
9. The circuit for controller idle timing dormancy according to claim 1, wherein the first pin and the sixth pin of the controller (MCU) are connected with a third power supply (V3), a control switch (K) for controlling on-off is further provided between the sixth pin and the third power supply, and the sixth pin of the controller (MCU) is a pin for acquiring a wake-up signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321682820.4U CN220137574U (en) | 2023-06-29 | 2023-06-29 | Circuit for controller idle timing dormancy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321682820.4U CN220137574U (en) | 2023-06-29 | 2023-06-29 | Circuit for controller idle timing dormancy |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220137574U true CN220137574U (en) | 2023-12-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321682820.4U Active CN220137574U (en) | 2023-06-29 | 2023-06-29 | Circuit for controller idle timing dormancy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220137574U (en) |
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2023
- 2023-06-29 CN CN202321682820.4U patent/CN220137574U/en active Active
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