CN218866084U - Low-jitter pulse distribution test system of full-function clock tester - Google Patents
Low-jitter pulse distribution test system of full-function clock tester Download PDFInfo
- Publication number
- CN218866084U CN218866084U CN202222131739.9U CN202222131739U CN218866084U CN 218866084 U CN218866084 U CN 218866084U CN 202222131739 U CN202222131739 U CN 202222131739U CN 218866084 U CN218866084 U CN 218866084U
- Authority
- CN
- China
- Prior art keywords
- circuit
- low
- jitter
- signal
- jitter pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model discloses a low jitter pulse distribution test system of full function clock tester, clock tester low jitter pulse distribution circuit include signal distribution circuit, low jitter pulse signal production circuit, impedance matching circuit and, signal distribution circuit is used for carrying out level conversion with the signal that receives and reduces the shake, and signal distribution circuit's output is connected with low jitter pulse signal production circuit's input, and low jitter pulse signal production circuit is used for carrying out level conversion with the signal and reduces the shake, low jitter pulse signal production circuit is connected with impedance matching circuit for the signal after the production distribution carries out and signal distribution circuit carries out impedance matching; through the utility model discloses, a plurality of clock tester of test that can be succinct fast has satisfied different clock tester test task demands, and low jitter pulse distribution reduces measuring error, has avoided causing the unsafe phenomenon of test result because of the jitter error.
Description
Technical Field
The utility model belongs to the technical field of the time frequency measurement, concretely relates to low shake pulse distribution test system of full function clock tester.
Background
In the prior art, a clock tester low-jitter pulse distribution circuit adopts a scheme of connecting a plurality of gate circuits in parallel. FIG. 1 is a circuit diagram of the prior art, as shown in FIG. 1, a plurality of gates are connected in parallel to output a plurality of pulse signals, the jitter of the output signal is determined by the selected gate, and a TTL or COMS circuit is generally used;
in the prior art, a low jitter circuit is added behind an original gate circuit, a signal is amplified by a triode to generate a pulse with a steep front edge, the triode has shorter transient time, and the pulse signal can be output in a lower jitter mode.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a low jitter pulse distribution test system of full function clock tester to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above purpose, the utility model adopts the following technical scheme: full function clock tester hangs down shake pulse distribution test system, clock tester hangs down shake pulse distribution circuit and includes signal distribution circuit, low shake pulse signal generating circuit, impedance matching circuit and, signal distribution circuit is used for carrying out level switching with the signal that receives and reduces the shake, and signal distribution circuit's output is connected with the input of low shake pulse signal generating circuit, and low shake pulse signal generating circuit is used for carrying out level switching with the signal and reduces the shake, low shake pulse signal generating circuit is connected with impedance matching circuit for the signal after the production distribution carries out and signal distribution circuit carries out impedance matching.
Furthermore, the clock tester is connected to the input end of the signal distribution circuit through a connecting cable and a connector, the low-jitter pulse signal generation circuit converts the pulse signal into a low-jitter signal, and the output low-jitter signal passes through the impedance matching network to output a triode and a voltage regulator tube protection circuit.
Further, the low jitter pulse signal generating circuit comprises a gate circuit, a comparator or a trigger, and the gate circuit obtains a jitter rising edge signal.
Further, the impedance matching circuit comprises a resistor connected with the pulse output and a resistor matched with the test cable, and the resistance value of the resistor is ohm.
Further, the impedance matching circuit comprises 3 connected resistors, the resistance value is calculated according to the length of the test cable and the pulse jitter time, and the total resistance value is 50 ohms to the ground.
Furthermore, the clock tester is connected with the clock tester low-jitter pulse distribution circuit and used for generating a frequency signal, and the clock display unit connected with the clock tester low-jitter pulse distribution circuit generates a standard time signal; the counter testing device is connected with the clock tester low-jitter pulse distribution circuit and used for testing the clock error performance index according to the pulse signal.
Compared with the prior art, the beneficial effects of the utility model reside in that:
the utility model reduces the jitter of the pulse signal and meets the test requirement of the clock tester by the low jitter pulse signal generating circuit; the impedance matching circuit is used for realizing the matching of the signal circuit, increasing the signal transmission distance and avoiding the distortion caused by too long transmission distance.
Through the utility model discloses, a plurality of clock tester of test that can be succinct fast has satisfied different clock tester test task demands, and low jitter pulse distribution reduces measuring error, has avoided causing the unsafe phenomenon of test result because of the jitter error.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a circuit diagram of the prior art;
fig. 2 is a block diagram of the low jitter pulse distribution circuit of the clock tester of the present invention;
FIG. 3 is a circuit diagram of the low jitter pulse distribution generation circuit of the present invention;
fig. 4 is a schematic diagram of one embodiment of the low jitter pulse distribution circuit of the clock tester of the present invention;
FIG. 5 is a block diagram of the testing system of the present invention;
fig. 6 is a circuit diagram of the impedance matching and transmission circuit of the present invention.
In the figure: 100. a clock tester; 101. a signal distribution circuit; 102. a low jitter pulse signal generating circuit; 103. an impedance matching circuit; 200. a clock tester low jitter pulse distribution circuit; 300. a clock display unit; 400. a recording unit; 500. the counter test device.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
Referring to fig. 1-6, the utility model provides a technical solution:
the utility model provides a low-jitter pulse distribution test system of a full-function clock tester, which solves the problem of large jitter caused by directly adopting a parallel connection mode of gate drive in the prior art, and meets the test requirement of a counter; the impedance matching and the transmission circuit are used for realizing the matching of the signal circuit, reducing the output signal distortion of long-distance transmission of pulse signals and testing the jitter error introduced by a cable;
the clock tester low-jitter pulse distribution circuit 200 comprises a signal distribution circuit 101, a low-jitter pulse signal generation circuit 102, an impedance matching circuit 103 and a clock signal processing circuit, wherein the signal distribution circuit 101 is used for carrying out level conversion on received signals to reduce jitter, the output end of the signal distribution circuit 101 is connected with the input end of the low-jitter pulse signal generation circuit 102, the low-jitter pulse signal generation circuit 102 is used for carrying out level conversion on the signals to reduce jitter, and the low-jitter pulse signal generation circuit 102 is connected with the impedance matching circuit 103 and is used for generating distributed signals to carry out impedance matching with the signal distribution circuit 101; the clock tester 100 is connected with the clock tester low jitter pulse distribution circuit 200 and is used for generating a frequency signal, and the clock display unit 300 connected with the clock tester low jitter pulse distribution circuit 200 generates a standard time signal; the recording unit 400 connected to the clock tester low jitter pulse distribution circuit 200 generates a signal record, and the counter test apparatus 500 connected to the clock tester low jitter pulse distribution circuit 200 performs a test of a clock error performance index based on the pulse signal.
Specifically, the clock tester low jitter pulse distribution circuit 200 further includes: the input end of the impedance matching circuit 103 is connected with the output end of the impedance matching circuit 103, and the other end of the impedance matching circuit is connected with the matching resistor for signal transmission.
Specifically, the clock tester low jitter pulse distribution circuit 200 includes a level shifter.
Specifically, the clock tester low jitter pulse distribution circuit 200 includes a flip-flop.
Specifically, the clock tester low jitter pulse distribution circuit 200 includes an IC module.
Specifically, the clock tester is connected to the input end of the signal distribution circuit 101 through a connection cable and a connector, the low jitter pulse signal generation circuit 102 converts the pulse signal into a low jitter signal, and the output low jitter signal passes through the impedance matching network to output a triode and a voltage regulator tube protection circuit.
Specifically, the low jitter pulse signal generating circuit 102 includes a gate circuit, a comparator or a flip-flop, the gate circuit may be 74F14, the gate circuit obtains a jittered rising edge signal, the number of the low jitter pulse signal generating circuits 102 may be one or more, and the low jitter signal may pass through a plurality of gate circuits connected in parallel in sequence to meet the requirement of practical application, where the low jitter pulse signal generating circuit 102 includes one or any combination of a shaping circuit, an inverting circuit and a triode.
In one embodiment, the gate circuit includes one or any combination of an and gate, an or gate and a not gate.
Fig. 4 shows one embodiment of a low jitter pulse signal generating circuit. As shown in fig. 4, the pulse signal is first passed through one or more shapers and phase shifters and then sent to the triodes to become a pulse signal with a steep leading edge, which is amplified and then used as an impedance matching network.
Specifically, the impedance matching circuit 103 includes a resistor connected to the pulse output and a resistor matching the test cable, and the resistance of the resistor is 50 ohms.
Specifically, the impedance matching circuit 103 includes 3 resistors connected, and the resistance value is calculated according to the length of the test cable and the pulse jitter time, and the total resistance value is 50 ohms to ground.
To sum up, the utility model can generate low jitter pulse signals by adding the rapid jitter circuit, thereby avoiding jitter errors introduced by pulse distribution and reducing the measurement errors of the clock tester; manual error calibration is not needed, and the problem of inaccurate test of the clock tester is avoided. And, the utility model discloses a matching network after one or more gate circuits and triode enlarge can use different cable types and length, does not introduce transmission jitter error through the calculation parameter.
Above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the design of the present invention, equivalent replacement or change should be covered within the protection scope of the present invention.
Claims (6)
1. Full function clock tester low jitter pulse distribution test system, its characterized in that: the clock tester low-jitter pulse distribution circuit (200) comprises a signal distribution circuit (101), a low-jitter pulse signal generation circuit (102), an impedance matching circuit (103) and a circuit for carrying out level conversion and jitter reduction on received signals, wherein the output end of the signal distribution circuit (101) is connected with the input end of the low-jitter pulse signal generation circuit (102), the low-jitter pulse signal generation circuit (102) is used for carrying out level conversion and jitter reduction on the signals, and the low-jitter pulse signal generation circuit (102) is connected with the impedance matching circuit (103) and is used for generating the distributed signals to carry out impedance matching with the signal distribution circuit (101).
2. The full function clock tester low jitter pulse distribution test system of claim 1 wherein: the clock tester is connected to the input end of the signal distribution circuit (101) through a connecting cable and a connector, the low-jitter pulse signal generation circuit (102) converts a pulse signal into a low-jitter signal, and the output low-jitter signal passes through an impedance matching network to output a triode and a voltage regulator tube protection circuit.
3. The full function clock tester low jitter pulse distribution test system of claim 1, wherein: the low jitter pulse signal generating circuit (102) includes a gate circuit, a comparator or a flip-flop, and the gate circuit obtains a jittered rising edge signal.
4. The full function clock tester low jitter pulse distribution test system of claim 1 wherein: the impedance matching circuit (103) comprises a resistor connected with the pulse output and a resistor matched with the test cable, and the resistance value of the resistor is 50 ohms.
5. The fully functional clock tester low jitter pulse distribution test system of claim 4 in which: the impedance matching circuit (103) comprises 3 connected resistors, the resistance value is calculated according to the length of the test cable and the pulse jitter time, and the total resistance value is 50 ohms to the ground.
6. The full function clock tester low jitter pulse distribution test system of claim 1, wherein: the clock tester (100) is connected with the clock tester low-jitter pulse distribution circuit (200) and used for generating a frequency signal, and the clock display unit (300) is connected with the clock tester low-jitter pulse distribution circuit (200) and used for generating a standard time signal; the recording unit (400) connected with the clock tester low-jitter pulse distribution circuit (200) generates signal recording, and the counter test device (500) connected with the clock tester low-jitter pulse distribution circuit (200) is used for testing the clock error performance index according to the pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222131739.9U CN218866084U (en) | 2022-08-13 | 2022-08-13 | Low-jitter pulse distribution test system of full-function clock tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222131739.9U CN218866084U (en) | 2022-08-13 | 2022-08-13 | Low-jitter pulse distribution test system of full-function clock tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218866084U true CN218866084U (en) | 2023-04-14 |
Family
ID=87364278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222131739.9U Active CN218866084U (en) | 2022-08-13 | 2022-08-13 | Low-jitter pulse distribution test system of full-function clock tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218866084U (en) |
-
2022
- 2022-08-13 CN CN202222131739.9U patent/CN218866084U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109324248B (en) | Integrated vector network analyzer for data domain analysis and testing method thereof | |
| CN103840899B (en) | A kind of transmitting-receiving subassembly automatic test equipment | |
| CN104022828A (en) | Fiber data transmission method based on asynchronous communication mode | |
| CN103837767A (en) | Method for conducting characterization on reciprocity mixer with vector network | |
| US11105879B1 (en) | Time-domain segmented calibration method for a characteristic impedance of a time-domain reflectometer | |
| CN218866084U (en) | Low-jitter pulse distribution test system of full-function clock tester | |
| CN111856374B (en) | High-speed digital oscilloscope bandwidth calibration testing device and testing method | |
| CN106685377B (en) | Narrow pulse generating circuit and adjustable width single pulse generator | |
| CN202421440U (en) | Circuit delay time measurement device | |
| CN113938191A (en) | Method and device for parameter testing of optical module | |
| CN206609901U (en) | A kind of PCIE channel loss test tool | |
| CN216118413U (en) | Time measuring circuit | |
| CN110988785A (en) | Remote online calibration method for digital quantity input type electric energy meter | |
| CN114935716A (en) | ATE-based FPGA embedded SERDES test system and method | |
| CN106932746B (en) | Electronic current transformer performance test system and method | |
| CN114706718B (en) | PCIe signal integrity verification method, device, equipment and medium | |
| CN103095255B (en) | A kind of method eliminating back ditch based on Schmidt trigger | |
| CN106896270A (en) | A kind of measuring method of transmission line impedance | |
| WO2019105083A1 (en) | Improved impedance analysis method | |
| CN105425197A (en) | DC energy meter calibration method and system | |
| CN104866008B (en) | A kind of clock system | |
| CN109254217B (en) | S parameter extraction method of unilateral clamp | |
| CN101949681A (en) | System and method for measuring length of twisted pair based on RS485 bus signal transmission delay | |
| CN213517250U (en) | Terminating resistance calibration circuit | |
| CN204422715U (en) | Circuit radar installations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |