CN218734212U - Differential amplification circuit and radio frequency front end module - Google Patents

Abstract

The utility model discloses a differential amplification circuit and a radio frequency front end module, which comprises a first-stage amplification unit, a second-stage amplification unit and a matching circuit arranged between the first-stage amplification unit and the second-stage amplification unit; in the embodiment, the connecting wire is adopted to replace an inductor in the matching circuit of the differential amplifying circuit and participates in impedance conversion of the differential amplifying circuit, so that the overall performance (such as impedance matching performance) of the differential amplifying circuit is ensured, the phenomenon that the overall occupied area of the differential amplifying circuit is too large due to the introduction of the inductor can be avoided, the overall layout of the differential amplifying circuit is optimized, and the requirement for miniaturization is met.

Description

Differential amplification circuit and radio frequency front end module

Technical Field

The utility model relates to a radio frequency technology field especially relates to a differential amplification circuit and radio frequency front end module.

Background

With the increasing popularity of 5G communication, the performance requirements for transmitting and receiving radio frequency signals by communication devices such as terminals are also increasing. For example, power amplification circuits in rf front-end circuits are required to have better linearity, power, efficiency, bandwidth, etc. However, in order to meet various performance requirements, the conventional differential amplifier circuit usually needs to occupy a large area to lay out the connected components. For example: in order to realize impedance matching, a plurality of matching capacitors and a plurality of matching inductors are often required to be connected to the existing differential amplification circuit, so that the occupied area of the differential amplification circuit is overlarge. Therefore, how to realize the miniaturization of the differential amplifier circuit while ensuring the overall performance of the differential amplifier circuit is a problem to be solved urgently at present.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a differential amplifier circuit to solve the problem that differential amplifier circuit can't compromise performance and area occupied simultaneously.

A differential amplification circuit comprises a first-stage amplification unit, a second-stage amplification unit and a matching circuit arranged between the first-stage amplification unit and the second-stage amplification unit; the matching circuit comprises a connecting line, and the connecting line is connected with a node on a connecting path between the first-stage amplification unit and the second-stage amplification unit.

Further, the connection line includes a bonding wire.

Further, the connecting lines include a first connecting line, a first end of the first connecting line is connected to a node on a connecting path between the first output end of the first-stage amplifying unit and the first input end of the second-stage amplifying unit, and a second end of the first connecting line is connected to a node on a connecting path between the second output end of the first-stage amplifying unit and the second input end of the second-stage amplifying unit.

Furthermore, the connecting lines include a second connecting line and a third connecting line, a first end of the second connecting line is connected to a node on a connecting path between the first output end of the first-stage amplifying unit and the first input end of the second-stage amplifying unit, and a second end of the second connecting line is grounded; and a first end of the third connecting line is connected with a node on a connecting path between the second output end of the first-stage amplifying unit and the second input end of the second-stage amplifying unit, and a second end of the third connecting line is grounded.

Furthermore, the matching circuit further comprises a first matching capacitor, a second matching capacitor, a third matching capacitor and a fourth matching capacitor, wherein a first end of the first matching capacitor is connected with a first input/output of the first-stage amplification unit, a second end of the first matching capacitor is connected with a first end of the second matching capacitor, and a second end of the second matching capacitor is connected with a first input end of the second-stage amplification unit; the first end of the third matching capacitor is connected with the second output end of the first-stage amplification unit, the second end of the third matching capacitor is connected with the first end of the fourth matching capacitor, and the second end of the fourth matching capacitor is connected with the second input end of the second-stage amplification unit.

Further, a first end of the first connection line is connected to a second end of the first matching capacitor, and a second end of the first connection line is connected to a second end of the third matching capacitor.

Furthermore, a first end of the second connection line is connected to the second end of the first matching capacitor, a second end of the second connection line is grounded, a first end of the third connection line is connected to the second end of the third matching capacitor, and a second end of the second connection line is grounded.

Further, the equivalent inductance value of the connecting line is less than or equal to 1 nanohenry.

Further, the first-stage amplification unit includes a first amplification transistor and a first balun, a first end of the first amplification transistor is connected to a first input end of the first balun, a second input end of the first balun is grounded, a first output end of the first balun is a first output end of the first-stage amplification unit, and a second output end of the first balun is a second output end of the first-stage amplification unit, or the first-stage amplification unit includes a first differential amplification transistor and a second differential amplification transistor, an output end of the first differential amplification transistor is a first output end of the first-stage amplification unit, and an output end of the second differential amplification transistor is a second output end of the first-stage amplification unit;

the second-stage amplification unit comprises a third differential amplification transistor and a fourth differential amplification transistor, wherein the input end of the third differential amplification transistor is the first input end of the second-stage amplification unit, and the input end of the fourth differential amplification transistor is the second input end of the second-stage amplification unit.

Furthermore, the differential amplification circuit further comprises a third connecting line and a fourth connecting line, the first end of the third connecting line is connected with the output end of the first differential amplification transistor, the second end of the third connecting line is connected with the first power supply end, the first end of the fourth connecting line is connected with the output end of the second differential amplification transistor, and the second end of the fourth connecting line is connected with the second power supply end.

A radio frequency front-end module comprises a first-stage amplification chip, a second-stage amplification chip and a matching circuit arranged between the first-stage amplification chip and the second-stage amplification chip, wherein the matching circuit comprises a connecting wire; the connecting line is connected with a bonding pad arranged on a connecting path between the first-stage amplification chip and the second-stage amplification chip.

Further, the connecting wire includes first connecting wire, the pad includes first pad and second pad, first pad sets up on the first output of first order amplification chip with on the first input of second level amplification chip the connection route, the second pad sets up the second output of first order amplification chip with on the connection route of the second input of second level amplification chip, the first end of first connecting wire with first pad is connected, the second end of first connecting wire with the second pad is connected.

Further, the connecting wire includes that second connecting wire and third are connected, the pad includes third pad and fourth pad, the third pad sets up the first output of first order amplification chip with on the connection route on the first input of second level amplification chip, the fourth pad sets up the second output of first order amplification chip with on the connection route of the second input of second level amplification unit, the first end of second connecting wire with the third pad is connected, the second end of second connecting wire is connected with the earthing terminal, the first end of third connecting wire with the fourth pad is connected, the second end of third connecting wire is connected with the earthing terminal.

The differential amplification circuit comprises a first-stage amplification unit, a second-stage amplification unit and a matching circuit arranged between the first-stage amplification unit and the second-stage amplification unit; in the embodiment, the impedance matching of the differential amplification circuit is realized by adopting the connecting wire to replace an inductor in the matching circuit of the differential amplification circuit to participate in impedance conversion of the differential amplification circuit, so that the overall performance (such as bandwidth performance) of the differential amplification circuit is ensured, the phenomenon that the overall occupied area of the differential amplification circuit is too large due to the introduction of the inductor is avoided, the overall layout of the differential amplification circuit is optimized, and the requirement for miniaturization of the differential amplification circuit is met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention;

fig. 2 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 3 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 4 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 5 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 6 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 7 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention;

fig. 8 is another circuit diagram of the differential amplifier circuit according to an embodiment of the present invention.

In the figure: 10. a first stage amplification unit; 20. a second stage amplification unit; s10, a first connecting line; s11, a second connecting line; s12, a third connecting line; m11, a first differential amplifying transistor; m12, a second differential amplifying transistor; m21, a third differential amplifying transistor; m22, a fourth differential amplifying transistor; c11, a first matching capacitor; c21, a second matching capacitor; c12, a third matching capacitor; c22, a fourth matching capacitor; 100. a first stage amplification chip; 200. and a second stage amplification chip.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under 823030," "under 8230; below," "under 8230," "under," "over," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230, below" and "at 8230, below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed structures and steps will be provided in the following description so as to explain the technical solution provided by the present invention. The preferred embodiments of the present invention are described in detail below, however, other embodiments of the present invention are possible in addition to these detailed descriptions.

The present embodiment provides a differential amplification circuit, as shown in fig. 1 and fig. 2, including a first-stage amplification unit 10, a second-stage amplification unit 20, and a matching circuit 30 disposed between the first-stage amplification unit 10 and the second-stage amplification unit 20; the matching circuit 30 includes a connection line connected to a node on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20.

The first stage amplification unit 10 amplifies the rf input signal and outputs an rf amplified signal. Alternatively, the first-stage amplification unit 10 may be a single-ended amplification unit, or may be a differential amplification unit. The second-stage amplifying unit 20 amplifies the rf amplified signal output by the first-stage amplifying unit 10, and outputs an rf output signal. Alternatively, the second-stage amplifying unit 20 may be a single-ended amplifying unit, or may be a differential amplifying unit.

Note that, since the present application is a differential amplification circuit, at least one of the first-stage amplification unit 10 and the second amplification unit 20 is a differential amplification unit. The first-stage amplification unit 10 to the second amplification unit 20 may be a differential amplification circuit from a single end to a differential end, may also be a differential amplification circuit from a differential end to a single end, and may also be a differential amplification circuit from a double differential end. The first-stage amplification unit 10 may be any one of a driver stage and an intermediate stage. The second-stage amplification unit 20 may be any one of an intermediate stage and an output stage.

The matching circuit 30 is a circuit that is disposed between the first-stage amplification unit 10 and the second-stage amplification unit 20, and that participates in impedance conversion of the differential amplification circuit to implement impedance matching. In the present embodiment, the matching circuit 30 includes a connection line connected to a node on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20. It is to be understood that the connection line in the present application is not a connection line on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20, but a connection line connected to a node on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20, and the connection line in the present application mainly functions as impedance matching. For example: the connection line may have one end connected to a node on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20 and the other end connected to a ground terminal.

Wherein, the connecting wire participates in the impedance conversion of the differential amplifying circuit. In this embodiment, the connection line has an inductive impedance, and can participate in impedance matching instead of an inductor. Compared with the impedance matching through the inductor, the connecting line can save larger occupied area on the premise of realizing the same function and achieving the same performance, so that the layout of the differential amplifying circuit is more compact and reasonable. Optionally, the connecting line may be any connecting line that can connect two metal nodes, such as a jumper, a bonding wire, or a lead. The connection lines may be in the form of pads.

In a specific embodiment, preferably, the connection line includes a bonding wire.

In this embodiment, the differential amplification circuit includes a first-stage amplification unit, a second-stage amplification unit, and a matching circuit provided between the first-stage amplification unit and the second-stage amplification unit; in the embodiment, the connecting wire is adopted to replace an inductor in the matching circuit of the differential amplifying circuit and participates in impedance conversion of the differential amplifying circuit, so that impedance matching of the differential amplifying circuit is realized, the integral performance (such as bandwidth performance) of the differential amplifying circuit is ensured, the phenomenon that the integral occupied area of the differential amplifying circuit is too large due to the introduction of the inductor is avoided, the integral layout of the differential amplifying circuit is optimized, and the requirement for miniaturization is met.

In a specific embodiment, referring to fig. 1 below, the connection lines include a first connection line S10, a first end of the first connection line S10 is connected to a node on a connection path between a first output terminal of the first-stage amplification unit 10 and a first input terminal of the second-stage amplification unit 20, and a second end of the first connection line S10 is connected to a node on a connection path between a second output terminal of the first-stage amplification unit 10 and a second input terminal of the second-stage amplification unit 20.

In the present embodiment, the first-stage amplification unit 10 includes a first differential amplification transistor M11 and a second differential amplification transistor M12. The second-stage amplification unit 20 includes a third differential amplification transistor M21 and a fourth differential amplification transistor M22. The first differential amplifying transistor M11, the second differential amplifying transistor M12, the third differential amplifying transistor M21 and the fourth differential amplifying transistor M22 may be BJT transistors or Field Effect Transistors (FETs). Optionally, the first differential amplifying transistor M11, the second differential amplifying transistor M12, the third differential amplifying transistor M21 and the fourth differential amplifying transistor M22 each include at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. For example, the first differential amplifying transistor M11, the second differential amplifying transistor M12, the third differential amplifying transistor M21 and the fourth differential amplifying transistor M22 may be formed by connecting a plurality of BJT transistors in parallel.

In a specific embodiment, the first differential amplifying transistor M11 is configured to amplify a first radio frequency input signal and output a first radio frequency amplified signal (amplified first radio frequency input signal), the first radio frequency amplified signal is input to the input terminal of the third differential amplifying transistor M21 through the matching circuit 30, the second differential amplifying transistor M12 is configured to amplify a second radio frequency input signal and output a second radio frequency amplified signal (amplified second radio frequency input signal), and the second radio frequency amplified signal is input to the input terminal of the fourth differential amplifying transistor M22 through the matching circuit 30. The first rf input signal may be an rf signal output after being amplified by a corresponding pre-stage amplifying circuit, or may be one of balanced rf signals obtained by converting an unbalanced input rf signal. Similarly, the second rf input signal may also be an rf signal output after being amplified by the corresponding pre-stage amplifying circuit, or may also be one of balanced rf signals obtained by converting an unbalanced input rf signal.

In this example, the first connection line S10 presents an inductive impedance to participate in impedance conversion of the differential amplifier circuit, and since the first end of the first connection line is connected to a node on a connection path between the first output terminal of the first-stage amplifier unit and the first input terminal of the second-stage amplifier unit and the second end is connected to a node on a connection path between the second output terminal of the first-stage amplifier unit and the second input terminal of the second-stage amplifier unit, the first connection line is not directly connected to the Ground (GND), and a virtual ground node is formed on the first connection line by self-adaptation, thereby avoiding a parasitic effect caused by direct connection to the Ground (GND) and improving balance and symmetry of the differential amplifier circuit.

In a specific embodiment, a virtual ground node is formed on the first connection line 10, and the virtual ground node is configured to adaptively adjust the balance of the differential amplification circuit. It is understood that, since the first connection line is not directly connected to Ground (GND), a virtual ground node is formed on the first connection line, and the position of the virtual ground node can be adaptively adjusted to satisfy the balance of the differential amplifier circuit, so that the balance and symmetry of the differential amplifier circuit can be further improved while impedance matching is achieved and other performances of the differential amplifier circuit are satisfied.

In a specific embodiment, referring to fig. 2 below, the connection lines include a second connection line S11 and a third connection line S12, a first end of the second connection line S11 is connected to a node on a connection path between the first output terminal of the first-stage amplification unit 10 and the first input terminal of the second-stage amplification unit 20, and a second end of the second connection line S11 is grounded; a first end of the third connection line S12 is connected to a node on a connection path between the second output end of the first-stage amplification unit 10 and the second input end of the second-stage amplification unit 20, and a second end of the third connection line S12 is grounded.

In this example, the second connection line S11 and the third connection line S12 have inductive impedance to participate in impedance conversion of the differential amplifier circuit. Preferably, in order to ensure the balance of the differential amplifier circuit, the inductive impedance equivalent to the second connection line S11 is equal to the inductive impedance equivalent to the third connection line S12. Compared with the inductance which is connected to the ground at the node on the connection path between the first output end of the first-stage amplification unit 10 and the first input end of the second-stage amplification unit 20 and the inductance which is connected to the ground at the node on the connection path between the second output end of the first-stage amplification unit 10 and the second input end of the second-stage amplification unit 20, the impedance conversion of the differential amplification circuit is participated by the connection wire in the embodiment, so that the impedance of the differential amplification circuit can be ensured, the overall performance (such as bandwidth performance) of the differential amplification circuit is ensured, the phenomenon that the overall occupied area of the differential amplification circuit is too large due to the introduction of the inductance is avoided, the overall layout of the differential amplification circuit is optimized, and the requirement of miniaturization is met.

In a specific embodiment, referring to fig. 3 and 4 below, the matching circuit further includes a first matching capacitor C11, a second matching capacitor C21, a third matching capacitor C12, and a fourth matching capacitor C22, a first end of the first matching capacitor C11 is connected to the first output end of the first-stage amplification unit 10, a second end of the first matching capacitor C11 is connected to the first end of the second matching capacitor C21, and a second end of the second matching capacitor C21 is connected to the first input end of the second-stage amplification unit 20. A first end of the third matching capacitor C12 is connected to the second output end of the first-stage amplifying unit 10, a second end of the third matching capacitor C12 is connected to a first end of the fourth matching capacitor C22, and a second end of the fourth matching capacitor C22 is connected to the second input end of the second-stage amplifying unit 20.

The first matching capacitor C11, the second matching capacitor C21, the third matching capacitor C12, and the fourth matching capacitor C22 are all capacitors participating in impedance conversion in the matching circuit. Capacitive impedances presented by the first matching capacitor C11, the second matching capacitor C21, the third matching capacitor C12 and the fourth matching capacitor C22 interact with inductive impedances presented by connecting lines in the matching circuit, so that impedance matching of the differential amplification circuit is realized, and bandwidth performance of the differential amplification circuit in an operating frequency band is optimized.

Referring to fig. 3 below, a first end of the first connection line S10 is connected to a second end of the first matching capacitor C11, and a second end of the first connection line S10 is connected to a second end of the third matching capacitor C12.

In this example, the capacitive impedances presented by the first matching capacitor C11, the second matching capacitor C21, the third matching capacitor C12, and the fourth matching capacitor C22 interact with the inductive impedance presented by the first connection line S10, so as to implement impedance matching of the differential amplifier circuit, and optimize the bandwidth performance of the differential amplifier circuit in the working frequency band.

Alternatively, referring to fig. 4 below, a first end of the second connection line S11 is connected to the second end of the first matching capacitor C11, a second end of the second connection line S11 is grounded, a first end of the third connection line S12 is connected to the second end of the third matching capacitor C21, and a second end of the third connection line S12 is grounded.

In this example, the capacitive impedances presented by the first matching capacitor C11, the second matching capacitor C21, the third matching capacitor C12, and the fourth matching capacitor C22 interact with the inductive impedances presented by the second connecting line S11 and the third connecting line S12 to implement impedance matching of the differential amplifier circuit, and optimize the bandwidth performance of the differential amplifier circuit in the operating frequency band.

In one embodiment, the equivalent inductance value of the connection line is less than or equal to 1 nanohenry.

Because this example adopts the non-balun type matching circuit, consequently, only need less inductance impedance and less capacitance impedance interact can realize impedance matching to not only can reduce the impedance matching degree of difficulty and guarantee the matching bandwidth, can also reduce the area occupied of matching circuit, satisfy subsequent encapsulation demand.

In a specific embodiment, referring to fig. 5 below, the first-stage amplification unit 10 includes a first amplification transistor M10 and a first balun B1, a first end of the first amplification transistor M10 is connected to a first input end of the first balun B1, a second input end of the first balun B1 is grounded, a first output end of the first balun B1 is a first output end of the first-stage amplification unit, and a second output end of the first balun is a second output end of the first-stage amplification unit. It is understood that the first stage amplification unit 10 in this embodiment is a single-ended amplification unit.

Alternatively, referring to fig. 3 below, the first-stage amplification unit 10 includes a first differential amplification transistor M11 and a second differential amplification transistor M12, an output end of the first differential amplification transistor M11 is a first output end of the first-stage amplification unit, and an output end of the second differential amplification transistor M12 is a second output end of the first-stage amplification unit. It is to be understood that the first-stage amplification unit 10 in the present embodiment is a differential amplification unit.

The second-stage amplifying unit 20 includes a third differential amplifying transistor M21 and a fourth differential amplifying transistor M22, an input end of the third differential amplifying transistor M21 is a first input end of the second-stage amplifying unit 20, and an input end of the fourth differential amplifying transistor M22 is a second input end of the second-stage amplifying unit 20. It is to be understood that the second-stage amplification unit 20 in the present embodiment is a differential amplification unit.

Therefore, when the first-stage amplification unit 10 is a single-ended amplification unit and the second-stage amplification unit 20 is a differential amplification unit, the differential amplification circuit is a single-ended to differential amplification circuit. When the first-stage amplification unit 10 is a differential amplification unit and the second-stage amplification unit 20 is a differential amplification unit, the differential amplification circuit is a double-differential amplification circuit.

Referring to fig. 6, in a specific embodiment, the differential amplifier circuit further includes a third connection line S21 and a fourth connection line S22, a first end of the third connection line S21 is connected to the output terminal of the first differential amplifier transistor M11, a second end of the third connection line S21 is connected to the first power supply terminal, a first end of the fourth connection line S22 is connected to the output terminal of the second differential amplifier transistor M12, and a second end of the fourth connection line S22 is connected to the second power supply terminal.

The first power supply terminal supplies power to the first differential amplifying transistor M11 through the third connection line S21, so as to ensure the normal operation of the first differential amplifying transistor M11. The second power supply terminal supplies power to the second differential amplifying transistor M12 through the fourth connection line S22 to ensure the normal operation of the second differential amplifying transistor M12.

Compared with the power supply end which supplies power to the first differential amplifying transistor M11 and the second differential amplifying transistor M12 in an inductance mode, the power supply end supplies power to the first differential amplifying transistor M11 and the second differential amplifying transistor M12 through the transmission line, so that normal power supply of the differential amplifying circuit can be ensured, and the phenomenon that the total occupied area of the differential amplifying circuit is too large due to the introduction of the inductance can be avoided.

The application also provides a radio frequency front-end module, which comprises a first-stage amplification chip 100, a second-stage amplification chip 200 and a matching circuit 30 arranged between the first-stage amplification chip 100 and the second-stage amplification chip 200, wherein the matching circuit 30 comprises a connecting wire; the connection line is connected to a pad disposed on a connection path between the first-stage amplification chip 100 and the second-stage amplification chip 200.

The first-stage amplifier chip 100 is a chip integrated with an amplifier device or a conversion/synthesis device. For example: two differential amplifying transistors are integrated on the first stage amplifying chip 100, or a differential amplifying transistor and a balun are integrated on the first stage amplifying chip 100. Likewise, the second-stage amplification chip 200 is a chip integrated with an amplification device or a conversion synthesis device. For example: two differential amplifying transistors are integrated on the second stage amplifying chip 200, or a differential amplifying transistor and a balun are integrated on the second stage amplifying chip 200.

The matching circuit 30 is a circuit that is provided between the first-stage amplification chip 100 and the second-stage amplification chip 200, and participates in impedance conversion of the differential amplification circuit to achieve impedance matching. The matching circuit 30 includes a connection line connected to a pad disposed on a connection path between the first-stage amplification chip 100 and the second-stage amplification chip 200. It is to be understood that the connection line in the present application is not a connection line on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20, but a connection line connected in parallel on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20. For example: the connection line may have one end connected to a pad on a connection path between the first-stage amplification unit 10 and the second-stage amplification unit 20 and the other end connected to a ground terminal.

Wherein, the connecting wire participates in the impedance conversion of the differential amplifying circuit. In this embodiment, the connection presents an inductive impedance, and the wire can replace the inductor. Compared with the impedance conversion through the inductor, the connecting line can save a larger area on the premise of realizing the same function and achieving the same performance, so that the layout of the differential amplification circuit is more compact and reasonable. Optionally, the connecting line may be any connecting line that can connect two metal nodes, such as a jumper line, a bonding wire, or a lead line. The connecting wires are connected in the form of bonding pads.

Referring to fig. 7 below, in a specific embodiment, the connection line includes a first connection line S10, the pad includes a first pad and a second pad, the first pad is disposed on a connection path between the first output terminal of the first-stage amplification chip and the first input terminal of the second-stage amplification chip, the second pad is disposed on a connection path between the second output terminal of the first-stage amplification chip and the second input terminal of the second-stage amplification chip, a first end of the first connection line S10 is connected to the first pad, and a second end of the first connection line is connected to the second pad.

Referring to fig. 8, in another specific embodiment, the connection lines include a second connection line S11 and a third connection line S12, the pads include a third pad and a fourth pad, the third pad is disposed on a connection path between the first output terminal of the first-stage amplifier chip and the first input terminal of the second-stage amplifier chip, the fourth pad is disposed on a connection path between the second output terminal of the first-stage amplifier chip and the second input terminal of the second-stage amplifier unit, a first end of the second connection line S11 is connected to the third pad, a second end of the second connection line S11 is connected to a ground terminal, a first end of the third connection line S12 is connected to the fourth pad, and a second end of the third connection line S12 is connected to the ground terminal.

The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims (14)

1. A differential amplification circuit is characterized by comprising a first-stage amplification unit, a second-stage amplification unit and a matching circuit arranged between the first-stage amplification unit and the second-stage amplification unit; the matching circuit comprises a connecting line, and the connecting line is connected with a node on a connecting path between the first-stage amplification unit and the second-stage amplification unit.

2. The differential amplification circuit of claim 1, wherein the connection line comprises a bond wire.

3. The differential amplification circuit according to claim 1, wherein the connection line includes a first connection line having a first end connected to a node on a connection path between the first output terminal of the first-stage amplification unit and the first input terminal of the second-stage amplification unit, and a second end connected to a node on a connection path between the second output terminal of the first-stage amplification unit and the second input terminal of the second-stage amplification unit.

4. The differential amplification circuit according to claim 1, wherein the connection line includes a second connection line and a third connection line, a first end of the second connection line is connected to a node on a connection path between the first output terminal of the first-stage amplification unit and the first input terminal of the second-stage amplification unit, and a second end of the second connection line is grounded; and a first end of the third connecting line is connected with a node on a connecting path between the second output end of the first-stage amplifying unit and the second input end of the second-stage amplifying unit, and a second end of the third connecting line is grounded.

5. The differential amplification circuit according to claim 3, wherein the matching circuit further includes a first matching capacitor, a second matching capacitor, a third matching capacitor, and a fourth matching capacitor, a first end of the first matching capacitor is connected to the first input/output of the first-stage amplification unit, a second end of the first matching capacitor is connected to a first end of the second matching capacitor, and a second end of the second matching capacitor is connected to the first input terminal of the second-stage amplification unit; the first end of the third matching capacitor is connected with the second output end of the first-stage amplification unit, the second end of the third matching capacitor is connected with the first end of the fourth matching capacitor, and the second end of the fourth matching capacitor is connected with the second input end of the second-stage amplification unit.

6. The differential amplification circuit according to claim 4, wherein the matching circuit further includes a first matching capacitor, a second matching capacitor, a third matching capacitor, and a fourth matching capacitor, a first end of the first matching capacitor is connected to the first input/output of the first-stage amplification unit, a second end of the first matching capacitor is connected to a first end of the second matching capacitor, and a second end of the second matching capacitor is connected to the first input terminal of the second-stage amplification unit; the first end of the third matching capacitor is connected with the second output end of the first-stage amplification unit, the second end of the third matching capacitor is connected with the first end of the fourth matching capacitor, and the second end of the fourth matching capacitor is connected with the second input end of the second-stage amplification unit.

7. The differential amplification circuit according to claim 5, wherein a first end of the first connection line is connected to a second end of the first matching capacitor, and a second end of the first connection line is connected to a second end of the third matching capacitor.

8. The differential amplifier circuit as in claim 6, wherein a first end of said second connection line is connected to a second end of said first matching capacitor, a second end of said second connection line is grounded, a first end of said third connection line is connected to a second end of said third matching capacitor, and a second end of said third connection line is grounded.

9. The differential amplifier circuit as claimed in claim 1, wherein an equivalent inductance value of said connection line is 1 nanohenry or less.

10. The differential amplification circuit according to claim 1, wherein the first-stage amplification unit includes a first amplification transistor and a first balun, a first terminal of the first amplification transistor is connected to a first input terminal of the first balun, a second input terminal of the first balun is grounded, a first output terminal of the first balun is a first output terminal of the first-stage amplification unit, and a second output terminal of the first balun is a second output terminal of the first-stage amplification unit, or the first-stage amplification unit includes a first differential amplification transistor and a second differential amplification transistor, an output terminal of the first differential amplification transistor is a first output terminal of the first-stage amplification unit, and an output terminal of the second differential amplification transistor is a second output terminal of the first-stage amplification unit;

the second-stage amplification unit comprises a third differential amplification transistor and a fourth differential amplification transistor, wherein the input end of the third differential amplification transistor is the first input end of the second-stage amplification unit, and the input end of the fourth differential amplification transistor is the second input end of the second-stage amplification unit.

11. The differential amplification circuit according to claim 10, further comprising a third connection line and a fourth connection line, a first end of the third connection line being connected to the output terminal of the first differential amplification transistor, a second end of the third connection line being connected to the first power supply terminal, a first end of the fourth connection line being connected to the output terminal of the second differential amplification transistor, and a second end of the fourth connection line being connected to the second power supply terminal.

12. A radio frequency front-end module is characterized by comprising a first-stage amplification chip, a second-stage amplification chip and a matching circuit arranged between the first-stage amplification chip and the second-stage amplification chip, wherein the matching circuit comprises a connecting wire; the connecting line is connected with a bonding pad arranged on a connecting path between the first-stage amplification chip and the second-stage amplification chip.

13. The rf front-end module of claim 12, wherein the connection line comprises a first connection line, the pad comprises a first pad and a second pad, the first pad is disposed on a connection path between a first output terminal of the first stage amplifier chip and a first input terminal of the second stage amplifier chip, the second pad is disposed on a connection path between a second output terminal of the first stage amplifier chip and a second input terminal of the second stage amplifier chip, a first end of the first connection line is connected to the first pad, and a second end of the first connection line is connected to the second pad.

14. The rf front-end module of claim 12, wherein the connecting wires comprise a second connecting wire and a third connecting wire, the pads comprise a third pad and a fourth pad, the third pad is disposed on a connection path between the first output terminal of the first-stage amplifier chip and the first input terminal of the second-stage amplifier chip, the fourth pad is disposed on a connection path between the second output terminal of the first-stage amplifier chip and the second input terminal of the second-stage amplifier chip, a first end of the second connecting wire is connected to the third pad, a second end of the second connecting wire is connected to a ground terminal, a first end of the third connecting wire is connected to the fourth pad, and a second end of the third connecting wire is connected to the ground terminal.

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