CN216794945U

CN216794945U - Push-pull power amplifying circuit and radio frequency front end module

Info

Publication number: CN216794945U
Application number: CN202122922580.8U
Authority: CN
Inventors: 戎星桦; 曹原; 雷传球; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2022-06-21
Anticipated expiration: 2031-11-25

Abstract

The utility model discloses a push-pull power amplification circuit and a radio frequency front-end module.A first capacitor is coupled to the output end of a first differential amplification transistor at one end, and is coupled to the output end of a second differential amplification transistor at the other end; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; the capacitance values of the first capacitor and the second capacitor are adjusted, so that the requirements for impedance balance are met among the output end of the first differential amplification transistor, the output end of the second differential amplification transistor, the output end of the third differential amplification transistor and the output end of the fourth differential amplification transistor; therefore, the problem that the overall loss of the push-pull power amplifying circuit is overlarge due to unbalanced impedance among the output end of the first differential amplifying transistor, the output end of the second differential amplifying transistor, the output end of the third differential amplifying transistor and the output end of the fourth differential amplifying transistor is solved.

Description

Push-pull power amplifying circuit and radio frequency front end module

Technical Field

The utility model relates to the technical field of radio frequency, in particular to a push-pull power amplifying circuit and a radio frequency front-end module.

Background

Radio frequency power amplifiers are widely used in the fields of communications, broadcasting, radar, industrial processing, medical instruments, scientific research, and the like. Radio frequency power amplifiers commonly employ a push-pull format. At present, a push-pull power amplifier is used as a core radio frequency unit in a communication system, performance characteristics of the push-pull power amplifier have a great influence on overall system indexes, and especially loss and efficiency of the push-pull power amplifier are always focused. Especially, with the development of a 5G communication system, the power loss of the push-pull power amplifier becomes an important performance index for measuring the operating efficiency of the power amplifier, and plays an important role in the whole communication system.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a push-pull power amplification circuit and a radio frequency front end module, which solve the problem of large insertion loss of the push-pull power amplification circuit.

A push-pull power amplification circuit comprises a radio frequency input port, a first push-pull power amplifier and a second push-pull power amplifier, wherein the radio frequency input port is respectively coupled to the input end of the first push-pull power amplifier and the input end of the second push-pull power amplifier;

the first push-pull power amplifier comprises a first differential amplification transistor, a second differential amplification transistor and a first capacitor, and the second push-pull power amplifier comprises a third differential amplification transistor, a fourth differential amplification transistor and a second capacitor; the first differential amplifying transistor is arranged at the side far away from the second push-pull power amplifier, and the fourth differential amplifying transistor is arranged at the side far away from the first push-pull power amplifier;

one end of the first capacitor is coupled to the output end of the first differential amplification transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplification transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; wherein the first and second capacitors are configured to balance impedances between the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor, and the output terminal of the fourth differential amplifying transistor.

Further, the first capacitor and the second capacitor are configured to make an output impedance of the first differential amplifying transistor, an output impedance of the second differential amplifying transistor, an output impedance of the third differential amplifying transistor, and an output impedance of the fourth differential amplifying transistor the same.

Further, the capacitance value of the first capacitor and the capacitance value of the second capacitor are different.

Further, the capacitance value of the first capacitor is larger than that of the second capacitor.

Further, the capacitance value of the first capacitor is twenty percent greater than the capacitance value of the second capacitor.

Further, the rf input port is configured to receive an rf input signal, and output a first rf signal to the input terminal of the first differential amplifying transistor, a second rf signal to the input terminal of the second differential amplifying transistor, a third rf signal to the input terminal of the third differential amplifying transistor, and a fourth rf signal to the input terminal of the fourth differential amplifying transistor, wherein the phase of the first rf signal is a first phase, the phase of the second rf signal is a second phase, the phase of the third rf signal is a second phase, and the phase of the fourth rf signal is a third phase.

Further, the first push-pull power amplifier further comprises a first balun, and the second push-pull power amplifier further comprises a second balun;

the output end of the first differential amplifying transistor is connected with the first input end of the first balun; the output end of the second differential amplifying transistor is connected with the second input end of the first balun; the output end of the third differential amplification transistor is connected with the first input end of the second balun; the output end of the fourth differential amplification transistor is connected with the second input end of the second balun; the first output end of the first balun outputs a radio frequency output signal, the second output end of the first balun is connected with the first output end of the second balun, and the second output end of the second balun is connected with a ground end.

Further, the first balun includes a first primary winding and a first secondary winding, the first primary winding includes a first primary coil and a second primary coil; the first secondary winding comprises a first secondary coil and a second secondary coil; the first primary coil and the first secondary coil are coupled to form a first coupling coil, and the second primary coil and the second secondary coil are coupled to form a second coupling coil; the first coupling coil and the second coupling coil are adjacently arranged; the second balun includes a second primary winding and a second secondary winding, the second primary winding including a third primary coil and a fourth primary coil; the second secondary winding comprises a third secondary coil and a fourth secondary coil; the third primary coil and the third secondary coil are coupled to form a third coupling coil, and the fourth primary coil and the fourth secondary coil are coupled to form a fourth coupling coil; the third coupling coil and the fourth coupling coil are arranged adjacently.

Further, the first differential amplification transistor is a BJT transistor and includes a base, a collector and an emitter, the base of the first differential amplification transistor receives an input first radio frequency signal, the collector of the first differential amplification transistor is coupled to the first input terminal of the first balun, and the emitter of the first differential amplification transistor is grounded; the second differential amplification transistor is a BJT (bipolar junction transistor) and comprises a base electrode, a collector electrode and an emitter electrode, the base electrode of the second differential amplification transistor receives an input second radio-frequency signal, the collector electrode of the second differential amplification transistor is coupled to the second input end of the first balun, and the emitter electrode of the second differential amplification transistor is grounded; the base of the third differential amplification transistor receives an input third radio frequency signal, the collector of the third differential amplification transistor is coupled to the first input end of the second balun, and the emitter of the third differential amplification transistor is grounded; the base of the fourth differential amplification transistor receives an input fourth radio-frequency signal, the collector of the fourth differential amplification transistor is coupled to the second input end of the second balun, and the emitter of the fourth differential amplification transistor is grounded.

The application also provides a radio frequency front-end module, which is characterized by comprising a substrate, a push-pull power amplification chip arranged on the substrate, a first balun and a second balun arranged on the substrate,

the push-pull power amplification chip comprises a radio frequency input port, a first differential amplification transistor, a second differential amplification transistor, a third differential amplification transistor, a fourth differential amplification transistor, a first capacitor and a second capacitor;

the radio frequency input port is respectively coupled to an input end of the first differential amplification transistor, an input end of the second differential amplification transistor, an input end of the third differential amplification transistor and an input end of the fourth differential amplification transistor;

the first differential amplification transistor is connected with a first bonding pad of the push-pull power amplification chip, and the first bonding pad is in wire bonding with a first input end of the first balun; the second differential amplification transistor is connected with a second bonding pad of the push-pull power amplification chip, and the second bonding pad is in wire bonding with a second input end of the first balun; the third differential amplification transistor is connected with a third bonding pad of the push-pull power amplification chip, and the third bonding pad is in wire bonding with the first input end of the second balun; the fourth differential amplification transistor is connected with a fourth bonding pad of the push-pull power amplification chip, and the fourth bonding pad is in wire bonding with the second input end of the second balun;

a first output end of the first balun outputs a radio frequency output signal, a second output end of the first balun is connected with a first output end of the second balun, and a second output end of the second balun is connected with a ground end;

one end of the first capacitor is coupled to the output end of the first differential amplification transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplification transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; wherein the first and second capacitors are configured to balance impedance among the first, second, third and fourth differential amplification transistor outputs.

The push-pull power amplification circuit comprises a radio frequency input port, a first push-pull power amplifier and a second push-pull power amplifier, wherein the radio frequency input port is respectively coupled to the input end of the first push-pull power amplifier and the input end of the second push-pull power amplifier; the first push-pull power amplifier comprises a first differential amplification transistor, a second differential amplification transistor and a first capacitor, and the second push-pull power amplifier comprises a third differential amplification transistor, a fourth differential amplification transistor and a second capacitor; the first differential amplification transistor is arranged on the side far away from the second push-pull power amplifier, and the fourth differential amplification transistor is arranged on the side far away from the first push-pull power amplifier; one end of the first capacitor is coupled to the output end of the first differential amplification transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplification transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; wherein the first and second capacitors are configured to balance impedances between the output of the first differential amplifying transistor, the output of the second differential amplifying transistor, the output of the third differential amplifying transistor, and the output of the fourth differential amplifying transistor; one end of the first capacitor is coupled to the output end of the first differential amplification transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplification transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; by adjusting capacitance values of the first capacitor and the second capacitor, impedance adjustment of the first push-pull power amplifier and the second push-pull power amplifier is performed by the first capacitor and the second capacitor, and impedance balance requirements among an output end of the first differential amplification transistor, an output end of the second differential amplification transistor, an output end of the third differential amplification transistor and an output end of the fourth differential amplification transistor can be met; therefore, the problem that the overall loss of the push-pull power amplifying circuit is overlarge due to the fact that impedance among the output end of the first differential amplifying transistor, the output end of the second differential amplifying transistor, the output end of the third differential amplifying transistor and the output end of the fourth differential amplifying transistor is unbalanced is solved, and the overall performance of the push-pull power amplifying circuit is optimized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a circuit diagram of a push-pull power amplifier circuit according to an embodiment of the utility model;

FIG. 2 is another circuit diagram of a push-pull power amplifier circuit according to an embodiment of the utility model;

FIG. 3 is another circuit diagram of a push-pull power amplifier circuit according to an embodiment of the utility model;

FIG. 4 is a schematic circuit diagram of the RF front-end module according to an embodiment of the present invention;

fig. 5 is another circuit diagram of the push-pull power amplifier circuit according to an embodiment of the utility model.

In the figure, 100, a first push-pull power amplifier; 200. a second push-pull power amplifier; m1, a first differential amplifying transistor; m2, a second differential amplifying transistor; m3, a third differential amplifying transistor; m4, a fourth differential amplifying transistor; c1, a first capacitor; c2, a second capacitor; 10. a first balun; 20. a second balun; 30. a first pre-stage conversion circuit; 40. a second preceding stage conversion circuit; 50. an input conversion circuit; 300. a push-pull power amplification chip; 400. a substrate.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated throughout the same reference numerals to indicate same elements for clarity.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under …," "under …," "below," "under …," "over …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the utility model, however, the utility model is capable of other embodiments in addition to those detailed.

A push-pull power amplifier circuit, as shown in fig. 1, includes a radio frequency input port N, a first push-pull power amplifier 100 and a second push-pull power amplifier 200, where the radio frequency input port N is coupled to an input terminal of the first push-pull power amplifier 100 and an input terminal of the second push-pull power amplifier 200, respectively.

In a specific embodiment, the rf input port N is configured to receive an rf input signal, convert the rf input signal into a first input signal and a second input signal; and inputs the first input signal to an input terminal of the first push-pull power amplifier 100 and inputs the second input signal to an input terminal of the second push-pull power amplifier 200.

The first push-pull power amplifier 100 is configured to amplify a first input signal. The second push-pull power amplifier 30 is used for amplifying the second input signal. It is understood that the push-pull power amplifying circuit of the present application, which includes the first push-pull power amplifier 20 and the second push-pull power amplifier 30, has a larger output power than a circuit including only a single push-pull power amplifier.

The first push-pull power amplifier 100 includes a first differential amplifying transistor M1, a second differential amplifying transistor M2, and a first capacitor C1. One end of the first capacitor C1 is coupled to the output end of the first differential amplifying transistor M1, and the other end is coupled to the output end of the second differential amplifying transistor M2. In a specific embodiment, the first capacitor C1 is configured to adjust the impedance of the output terminal of the first differential amplifying transistor M1 and the impedance of the output terminal of the second differential amplifying transistor M2, so as to meet the requirement of impedance matching. For example, the inductive impedance at the output terminal of the first differential amplifying transistor M1 and the inductive impedance at the output terminal of the second differential amplifying transistor M2 are converted into capacitive impedances.

The second push-pull power amplifier 200 includes a third differential amplifying transistor M3, a fourth differential amplifying transistor M4, and a second capacitor C2. One end of the second capacitor C2 is coupled to the output end of the third differential amplifying transistor M3, and the other end is coupled to the output end of the fourth differential amplifying transistor M4. In a specific embodiment, the second capacitor C2 is configured to adjust the impedance of the output terminal of the third differential amplifying transistor M3 and the impedance of the output terminal of the fourth differential amplifying transistor M4, so as to meet the requirement of impedance matching. For example, the inductive impedance at the output terminal of the third differential amplifying transistor M3 and the inductive impedance at the output terminal of the fourth differential amplifying transistor M4 are converted into capacitive impedances.

The first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3, and the fourth differential amplifying transistor M4 may be BJT transistors or Field Effect Transistors (FETs). Optionally, the first differential amplifying transistor M1 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. Illustratively, the first differential amplifying transistor M1 may be formed by connecting a plurality of BJT transistors in parallel. The second differential amplifying transistor M2 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. For example, the second differential amplifying transistor M2 may be formed by connecting a plurality of BJT transistors in parallel. The third differential amplifying transistor M3 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. Illustratively, the third differential amplifying transistor M3 may be formed by connecting a plurality of BJT transistors in parallel. The fourth differential amplifying transistor M4 includes at least one BJT transistor (e.g., HBT transistor) or at least one field effect transistor. Illustratively, the fourth differential amplifying transistor M4 may be formed by connecting a plurality of BJT transistors in parallel.

It is to be understood that the first differential amplifying transistor M1 and the second differential amplifying transistor M2 may be any one of the first push-pull power amplifier stages, and exemplarily, the amplifying stage may be any one of the driver stage, the intermediate stage, or the output stage. The third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 may be any one of amplification stages in the second push-pull power amplifier, which may be any one of a driving stage, an intermediate stage, or an output stage, for example.

In one implementation, referring to fig. 5 below, the first push-pull power amplifier 100 further includes a first pre-conversion circuit 30. The first pre-conversion circuit 30 is configured to convert the first input signal output from the radio frequency input port N into a first converted signal and a second converted signal, and input the first converted signal to an input terminal of the first differential amplifying transistor M1 and the second converted signal to an input terminal of the second differential amplifying transistor M2. The second push-pull power amplifier 20 further comprises a second pre-conversion circuit 40. The second pre-stage conversion circuit 40 is configured to convert the second input signal output from the radio frequency input port N into a third converted signal and a fourth converted signal, and input the third converted signal to an input terminal of the third differential amplification transistor M3 and the fourth converted signal to an input terminal of the fourth differential amplification transistor M4.

In this embodiment, the first pre-stage conversion circuit 30 is preferably a first input balun. The second pre-conversion circuit 40 is preferably a second input balun. Specifically, a first input end of the first input balun is connected to the rf input port N, a second input end of the first input balun is connected to the ground, a first output end of the first input balun is connected to the input end of the first differential amplifying transistor M1, and a second output end of the first input balun is connected to the input end of the second differential amplifying transistor M2, so as to input the first conversion signal to the input end of the first differential amplifying transistor M1 and input the second conversion signal to the input end of the second differential amplifying transistor M2. A first input end of the second input balun is connected to the rf input port N, a second input end of the second input balun is connected to the ground, a first output end of the second input balun is connected to the input end of the third differential amplifying transistor M3, and a second output end of the second input balun is connected to the input end of the fourth differential amplifying transistor M4, so as to input the third conversion signal to the input end of the third differential amplifying transistor M3 and input the fourth conversion signal to the input end of the fourth differential amplifying transistor M4.

In a specific embodiment, referring to fig. 5 below, the push-pull power amplifying circuit further includes an input switching circuit 50, and the input switching circuit 50 is preferably an input switching balun. The first input end of the input conversion balun is connected with the radio frequency input port, the second input end of the input conversion balun is connected with the ground terminal, the first output end of the input conversion balun is connected with the first input end of the first input balun, the second output end of the input conversion balun is connected with the first input end of the second input balun, and the input conversion balun is used for converting a radio frequency input signal into a first input signal and outputting the first input signal to the first input balun and outputting a second input signal to the second input balun.

Specifically, the first push-pull power amplifier 100 and the second push-pull power amplifier 200 are arranged in parallel, the first differential amplifying transistor M1 is arranged on the side far from the second push-pull power amplifier 200, and the fourth differential amplifying transistor M4 is arranged on the side far from the first push-pull power amplifier 100. In an embodiment, in order to satisfy the impedance matching requirement and the impedance balancing requirement of the push-pull power amplifier circuit, the impedances of the output terminal of the first differential amplifier transistor M1, the output terminal of the second differential amplifier transistor M2, the output terminal of the third differential amplifier transistor M3 and the output terminal of the fourth differential amplifier transistor M4 should be kept in a balanced/same state under an ideal condition. However, in practical application and design processes, signals amplified by the first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 need to be merged and converted by a later-stage circuit, and due to the self-structural characteristics of the later-stage circuit (e.g., the later-stage quasi-balun) or other factors, an impedance imbalance occurs among the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor and the output terminal of the fourth differential amplifying transistor, so that the overall loss of the push-pull power amplifying circuit is too large.

In this regard, the present application provides a first capacitor C1 with one end coupled to the output end of the first differential amplifying transistor M1 and the other end coupled to the output end of the second differential amplifying transistor M2; one end of the second capacitor C2 is coupled to the output end of the third differential amplifying transistor M3, and the other end is coupled to the output end of the fourth differential amplifying transistor M4; wherein the first and second capacitors are configured to balance impedances between the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor, and the output terminal of the fourth differential amplifying transistor.

In this embodiment, one end of the first capacitor is coupled to the output end of the first differential amplifying transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplifying transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; by adjusting the capacitance values of the first capacitor C1 and the second capacitor C2, the first capacitor C1 and the second capacitor C2 can adjust the impedance of the first push-pull power amplifier 100 and the second push-pull power amplifier 200, and simultaneously, the output end of the first differential amplifying transistor M1, the output end of the second differential amplifying transistor M2, the output end of the third differential amplifying transistor M3 and the output end of the fourth differential amplifying transistor M4 can meet the requirement of impedance balance; therefore, the problem that the overall loss of the push-pull power amplifying circuit is overlarge due to the fact that impedance among the output end of the first differential amplifying transistor, the output end of the second differential amplifying transistor, the output end of the third differential amplifying transistor and the output end of the fourth differential amplifying transistor is unbalanced is solved, and the overall performance of the push-pull power amplifying circuit is optimized.

Wherein the capacitance value of the first capacitor C1 is different from the capacitance value of the second capacitor C2. In an embodiment, since the first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 are the same amplifying transistor, in an ideal state, in order to satisfy the impedance matching requirement of the push-pull power amplifying circuit, the first capacitor C1 and the second capacitor C2 are capacitors with the same capacitance value. However, in practical applications, since impedances of the output terminal of the first differential amplifying transistor M1, the output terminal of the second differential amplifying transistor M2, the output terminal of the third differential amplifying transistor M3 and the output terminal of the fourth differential amplifying transistor M4 tend to be unbalanced, in this embodiment, the first capacitor C1 and the second capacitor C2 are set as two capacitors with different capacitance values, so that the impedance imbalance between the output terminal of the first differential amplifying transistor M1, the output terminal of the second differential amplifying transistor M2, the output terminal of the third differential amplifying transistor M3 and the output terminal of the fourth differential amplifying transistor M4 can be compensated, and the overall loss of the push-pull power amplifying circuit is reduced.

Further, the capacitance value of the first capacitor C1 is larger than that of the second capacitor C2. In a specific embodiment, due to the self-structural characteristics of the subsequent circuit (e.g., the subsequent quasi-commutated balun) or other factors, the impedance of the output terminal of the fourth differential amplifying transistor M4 generally deviates from the impedance of the output terminal of the first differential amplifying transistor M1, the impedance of the output terminal of the second differential amplifying transistor M2 and the impedance between the output terminals of the third differential amplifying transistor M3. For example: the impedance at the output terminal of the first differential amplifying transistor M1, the impedance at the output terminal of the second differential amplifying transistor M2, and the impedance at the output terminal of the third differential amplifying transistor M3 are all 5 Ω, and the impedance at the output terminal of the fourth differential amplifying transistor M4 is only 4-jX in practice. In view of this, in the present embodiment, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are adjusted to make the capacitance value of the first capacitor C1 larger than the capacitance value of the second capacitor C2, so that the impedances between the output end of the first differential amplifying transistor M1, the output end of the second differential amplifying transistor M2, the output end of the third differential amplifying transistor M3 and the output end of the fourth differential amplifying transistor M4 are balanced, that is, the impedance of the output end of the first differential amplifying transistor, the impedance of the output end of the second differential amplifying transistor, the impedance of the output end of the third differential amplifying transistor and the impedance of the output end of the fourth differential amplifying transistor are the same, and the overall loss of the push-pull power amplifying circuit is reduced.

Preferably, in a practical application, when the capacitance value of the first capacitor C1 is set to be twenty percent larger than the capacitance value of the second capacitor C2 based on the deviation between the impedance at the output end of the fourth differential amplifying transistor M4 and the impedance at the output end of the first differential amplifying transistor M1, the impedance at the output end of the second differential amplifying transistor M2, and the impedance at the output end of the third differential amplifying transistor M3, the balance among the output end of the first differential amplifying transistor M1, the output end of the second differential amplifying transistor M2, the output end of the third differential amplifying transistor M3, and the output end of the fourth differential amplifying transistor M4 is optimized, and the overall loss of the push-pull power amplifying circuit is minimized.

In one embodiment, the capacitance value of the first capacitor is preferably twenty percent greater than the capacitance value of the second capacitor.

In a specific embodiment, the total capacitance of the first capacitor C1 and the second capacitor C2 is determined in advance according to the overall impedance of the push-pull power amplifying circuit, that is, the total capacitance of the first capacitor C1 and the second capacitor C2 needs to satisfy the impedance matching of the push-pull power amplifying circuit, and the total capacitance of the first capacitor C1 and the second capacitor C2 is a fixed value. Therefore, in the process of adjusting the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2, the present application still needs to ensure that the total capacitance value of the first capacitor C1 and the second capacitor C2 is not changed. That is, the increased capacitance of the first capacitor C1 should be the same as the decreased capacitance of the second capacitor C2, provided that the total capacitance of the first capacitor C1 and the second capacitor C2 is not changed. Preferably, the capacitance value of the first capacitor is twenty percent greater than the capacitance value of the second capacitor. Illustratively, if the total capacitance value of the first capacitor C1 and the second capacitor C2 should be 11 Ω when the impedance matching of the push-pull power amplifying circuit is satisfied, and the average value of the first capacitor C1 and the second capacitor C2 is 5.5 Ω, in order to achieve impedance balance among the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor, and the output terminal of the fourth differential amplifying transistor, the first capacitor C1 is set to 5 Ω, and the second capacitor C2 is set to 6 Ω.

In a specific embodiment, the rf input port N is configured to receive an rf input signal, and output a first rf signal to the input terminal of the first differential amplifying transistor M1, a second rf signal to the input terminal of the second differential amplifying transistor M2, a third rf signal to the input terminal of the third differential amplifying transistor M3, and a fourth rf signal to the input terminal of the fourth differential amplifying transistor M4, wherein the phase of the first rf signal is a first phase, the phase of the second rf signal is a second phase, the phase of the third rf signal is a second phase, and the phase of the fourth rf signal is a third phase.

The first radio frequency signal and the second radio frequency signal are a pair of balanced differential signals. The third radio frequency signal and the fourth radio frequency signal are a pair of balanced differential signals. Ideally, the phase of the first rf signal is the same as the phase of the fourth rf signal, and the phase of the second rf signal is the same as the phase of the third rf signal. However, in practical applications, since there is a deviation in the impedance of the output terminal of the fourth differential amplifier transistor M4, there is often some deviation in the phase of the fourth rf signal from the phase of the first rf signal. Illustratively, the phase of the first radio frequency signal received by the first differential amplifying transistor M1 is a first phase P, the phase of the second radio frequency signal received by the second differential amplifying transistor M2 is a second phase N, the phase of the third radio frequency signal received by the third differential amplifying transistor M3 is a second phase N, and the phase of the fourth radio frequency signal received by the fourth differential amplifying transistor M4 is a third phase M, wherein the third phase M of the fourth radio frequency signal is a phase between the first phase P and the second phase N.

In a specific embodiment, the first push-pull power amplifier 100 further includes a first balun 10, and the second push-pull power amplifier 200 further includes a second balun 20.

The output end of the first differential amplifying transistor M1 is connected to the first input end of the first balun 10; the output terminal of the second differential amplifying transistor M2 is connected to the second input terminal of the first balun 10. The output end of the third differential amplifying transistor M3 is connected to the first input end of the second balun 20; the output end of the fourth differential amplifying transistor M4 is connected to the second input end of the second balun 20; a first output end of the first balun 10 outputs a radio frequency output signal, a second output end of the first balun 10 is connected to a first output end of the second balun 10, and a second output end of the second balun 10 is connected to a ground end.

The first push-pull power amplifier 10 comprises a first balun 11 and the second push-pull power amplifier 20 comprises a second balun 21. The first balun 11 is configured to perform a conversion synthesis on the first radio frequency signal and the second radio frequency signal amplified by the first push-pull power amplifier 10. The second balun 21 is configured to perform a conversion synthesis on the third radio frequency signal and the fourth radio frequency signal amplified by the second push-pull power amplifier 20.

Further, the first balun 10 includes a first primary winding and a first secondary winding, and the first primary winding includes a first primary coil and a second primary coil; the first secondary winding comprises a first secondary coil and a second secondary coil; the first primary coil and the first secondary coil are coupled to form a first coupling coil, and the second primary coil and the second secondary coil are coupled to form a second coupling coil; the first coupling coil and the second coupling coil are disposed adjacent to each other. Wherein the minimum distance between the adjacent first coupling coil and the second coupling coil is about the width distance of one coil.

Alternatively, the first coupling coil and the second coupling coil may be disposed on the same metal layer, or may be disposed on different adjacent metal layers.

One part of the first primary winding forms a first primary coil, and the other part forms a second primary coil; the first end of the first primary winding is used as a starting point, the wiring direction of the first primary coil is used as a first direction, the second end of the first primary winding is used as a starting point, and the wiring direction of the second primary coil is used as a second direction; the first secondary winding comprises a first secondary coil and a second secondary coil, and the first secondary coil comprises a first end and a second end; the second secondary coil comprises a third end and a fourth end; taking a second end of a first secondary coil as a starting point, a wiring direction of the first secondary coil as the first direction, a third end of a second secondary coil as a starting point, and a wiring direction of the second secondary coil as the second direction; the first direction is the same as the second direction, and the first coupling coil and the second coupling coil are arranged adjacently.

In a specific embodiment, when the current direction of the side of the first coupling coil adjacent to the second coupling coil is the same as the current direction of the side of the second coupling coil adjacent to the first coupling coil, the current of the side of the first coupling coil adjacent to the second coupling coil and the current of the side of the second coupling coil adjacent to the first coupling coil are mutually superposed, so that the first coupling coil and the second coupling coil are adjacently arranged, the occupied area of the first balun on the substrate can be reduced, the coupling degree between the first primary winding and the first secondary winding can be further improved, the coupling degree and the overall performance of the push-pull power amplification circuit are further improved, and the push-pull power amplification circuit can support a larger bandwidth.

The second balun 20 includes a second primary winding and a second secondary winding, the second primary winding includes a third primary coil and a fourth primary coil; the second secondary winding comprises a third secondary coil and a fourth secondary coil; the third primary coil and the third secondary coil are coupled to form a third coupling coil, and the fourth primary coil and the fourth secondary coil are coupled to form a fourth coupling coil; the third coupling coil and the fourth coupling coil are arranged adjacently. Wherein the minimum distance between the adjacent third coupling coil and the fourth coupling coil is about the width distance of one coil.

Alternatively, the third coupling coil and the fourth coupling coil may be disposed on the same metal layer, or may be disposed on different adjacent metal layers.

Similarly, a portion of the second primary winding forms a third primary coil and another portion forms a fourth primary coil; the first end of the second primary winding is used as a starting point, the wiring direction of the third primary coil is used as a first direction, the second end of the second primary winding is used as a starting point, and the wiring direction of the fourth primary coil is used as a second direction; the second secondary winding comprises a third secondary coil and a fourth secondary coil, and the third secondary coil comprises a first end and a second end; the fourth secondary coil comprises a third end and a fourth end; taking a second end of a third secondary coil as a starting point, a wiring direction of the third secondary coil as the first direction, a third end of a fourth secondary coil as a starting point, and a wiring direction of the fourth secondary coil as the second direction; the first direction and the second direction are the same, and the third coupling coil and the fourth coupling coil are arranged adjacently.

In a specific embodiment, when the current direction of the side, adjacent to the fourth coupling coil, of the third coupling coil is the same as the current direction of the side, adjacent to the third coupling coil, of the fourth coupling coil, the current of the side, adjacent to the fourth coupling coil, of the third coupling coil and the current of the side, adjacent to the third coupling coil, of the fourth coupling coil are mutually overlapped, so that the third coupling coil and the fourth coupling coil are adjacently arranged, the occupied area of the second balun on the substrate can be reduced, the coupling degree between the second primary winding and the second secondary winding can be further improved, the coupling degree and the overall performance of the push-pull power amplification circuit are further improved, and the push-pull power amplification circuit can support a larger bandwidth.

It is to be understood that the wiring direction is a direction for describing a coil running direction exhibited by an outer structure of the coil, and is not limited to a winding direction of the coil at the time of design or manufacture. As an example, with the first end of the first primary winding as a starting point, the coil of the first primary coil runs clockwise; the second end of the first primary winding is used as a starting point, and the wiring direction of the second primary coil is the counterclockwise direction and the clockwise direction.

In a specific embodiment, the first differential amplifying transistor M1 is a BJT transistor, and includes a base, a collector and an emitter, the base of the first differential amplifying transistor M1 receives an input first radio frequency signal, the collector of the first differential amplifying transistor M1 is coupled to the first input terminal of the first balun 10, and the emitter of the first differential amplifying transistor M1 is grounded; the second differential amplifying transistor M2 is a BJT transistor, and includes a base, a collector and an emitter, the base of the second differential amplifying transistor M2 receives the input second radio frequency signal, the collector of the second differential amplifying transistor M2 is coupled to the second input terminal of the first balun, and the emitter of the second differential amplifying transistor M2 is grounded; the base of the third differential amplifying transistor M3 receives the input third rf signal, the collector of the third differential amplifying transistor M3 is coupled to the first input terminal of the second balun 20, and the emitter of the third differential amplifying transistor M3 is grounded; the base of the fourth differential amplifying transistor M4 receives the input fourth rf signal, the collector of the fourth differential amplifying transistor M4 is coupled to the second input terminal of the second balun 20, and the emitter of the fourth differential amplifying transistor M4 is grounded.

The present application further provides a radio frequency front end module, which includes a substrate 400, a push-pull power amplifier chip 300 disposed on the substrate 400, and a first balun 10 and a second balun 20 disposed on the substrate 400.

The push-pull power amplification chip 300 comprises a radio frequency input port N, a first differential amplification transistor M1, a second differential amplification transistor M2, a third differential amplification transistor M3, a fourth differential amplification transistor M4, a first capacitor C1 and a second capacitor C2. The radio frequency input port N is respectively coupled to an input terminal of the first differential amplifying transistor M1, an input terminal of the second differential amplifying transistor M2, an input terminal of a third differential amplifying transistor M3 and an input terminal of the fourth differential amplifying transistor M4;

the push-pull power amplification chip 300 comprises a first differential amplification transistor M1, a second differential amplification transistor M2, a third differential amplification transistor M3 and a fourth differential amplification transistor M4, wherein the first differential amplification transistor M1 is connected with a first pad a of the push-pull power amplification chip 300, and the first pad a is in wire bonding with a first input end of the first balun 10. The second differential amplifying transistor M2 is connected to a second pad b of the push-pull power amplifying chip 300, and the second pad b is wire-bonded to the second input terminal of the first balun 10. The third differential amplifying transistor M3 is connected to a third pad c of the push-pull power amplifying chip 300, and the third pad c is wire-bonded to the 20 first input terminal of the second balun; the fourth differential amplifying transistor M is connected to a fourth pad d of the push-pull power amplifying chip 300, and the fourth pad d is wire-bonded to the second input end of the second balun 20.

In a specific embodiment, in order to realize the electrical connection of the first differential amplifying transistor M1 and the second differential amplifying transistor M2 disposed on the push-pull power amplifier chip 300 with the first balun 10 disposed on the substrate, and the electrical connection of the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 disposed on the push-pull power amplifier chip 300 with the second balun 20 disposed on the substrate; the connection may be made by wire bonding. The first pad a is bonded to the first input end of the first balun 10 through a lead, and the first pad a is bonded to the first input end of the first balun 10 through one or more leads, by providing the first pad a, the second pad b, the third pad c and the fourth pad d on the push-pull power amplifier chip 300, and connecting the output end of the first differential amplifier transistor M1 to the first pad a of the push-pull power amplifier chip 300. And the output terminal of the second differential amplifying transistor M2 is connected to a second pad b of the push-pull power amplifier chip 300, the second pad b is bonded to the second input terminal of the first balun 10 by a wire, wherein the second pad b is bonded to the first input terminal of the first balun 10 by one or more wires; thereby achieving electrical connection between the first differential amplifying transistor M1 and the second differential amplifying transistor M2 provided on the push-pull power amplifier chip and the first balun 10 provided on the substrate. Likewise, the output terminal of the third differential amplifying transistor M3 is connected to a third pad c of the push-pull power amplifier chip 300, which is wire bonded to the first end of the first coil segment, wherein the third pad c may be wire bonded to the first input terminal of the second balun 20 by one or more wires. And connecting the output terminal of the fourth differential amplifying transistor M4 to a fourth pad d of the push-pull power amplifier chip 300, the fourth pad d being wire-bonded to the second end of the second coil segment, wherein the fourth pad d is wire-bonded to the second input terminal of the second balun 20 by one or more wires; thereby achieving electrical connection between the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 provided on the push-pull power amplifier chip 300 and the second balun 20 provided on the substrate.

A first output terminal of the first balun 10 outputs a radio frequency output signal, a second output terminal of the first balun is connected to a first output terminal of the second balun, and a second output terminal of the second balun 20 is connected to a ground terminal.

In an embodiment, in order to satisfy the impedance matching requirement and the impedance balancing requirement of the rf front-end module, the impedances of the output terminal of the first differential amplifying transistor M1, the output terminal of the second differential amplifying transistor M2, the output terminal of the third differential amplifying transistor M3 and the output terminal of the fourth differential amplifying transistor M4 should be kept in a balanced/same state under an ideal condition. However, in practical application and design processes, signals amplified by the first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 need to be merged and converted by a later-stage circuit, and due to the self-structure characteristics of the later-stage circuit (for example, the first balun and the second balun) or other factors, an impedance imbalance occurs among the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor and the output terminal of the fourth differential amplifying transistor, so that the overall loss of the push-pull power amplifying circuit is too large.

In this regard, the present application provides a first capacitor C1 with one end coupled to the output end of the first differential amplifying transistor M1 and the other end coupled to the output end of the second differential amplifying transistor M2; one end of the second capacitor C2 is coupled to the output end of the third differential amplifying transistor M3, and the other end is coupled to the output end of the fourth differential amplifying transistor M4; wherein the first and second capacitors are configured to balance/equalize impedances between the output terminal of the first differential amplifying transistor, the output terminal of the second differential amplifying transistor, the output terminal of the third differential amplifying transistor, and the output terminal of the fourth differential amplifying transistor.

In this embodiment, one end of the first capacitor is coupled to the output end of the first differential amplifying transistor, and the other end of the first capacitor is coupled to the output end of the second differential amplifying transistor; one end of the second capacitor is coupled to the output end of the third differential amplification transistor, and the other end of the second capacitor is coupled to the output end of the fourth differential amplification transistor; by adjusting the capacitance values of the first capacitor C1 and the second capacitor C2, the first capacitor C1 and the second capacitor C2 can adjust the impedance of the first push-pull power amplifier 100 and the second push-pull power amplifier 200, and at the same time, the output terminals of the first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 can meet the requirement of impedance balance; therefore, the problem that the overall loss of the radio frequency front-end module is overlarge due to the fact that impedance among the output end of the first differential amplification transistor, the output end of the second differential amplification transistor, the output end of the third differential amplification transistor and the output end of the fourth differential amplification transistor is unbalanced is solved, and the overall performance of the radio frequency front-end module is optimized.

Wherein the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are different. In an embodiment, since the first differential amplifying transistor M1, the second differential amplifying transistor M2, the third differential amplifying transistor M3 and the fourth differential amplifying transistor M4 are the same amplifying transistor, in an ideal state, in order to satisfy the impedance matching requirement of the rf front-end module, the first capacitor C1 and the second capacitor C2 are capacitors with the same capacitance value. However, in practical applications, since impedances of the output terminal of the first differential amplifying transistor M1, the output terminal of the second differential amplifying transistor M2, the output terminal of the third differential amplifying transistor M3 and the output terminal of the fourth differential amplifying transistor M4 tend to be unbalanced, in this embodiment, the first capacitor C1 and the second capacitor C2 are set as two capacitors with different capacitance values, so that the impedance imbalance between the output terminal of the first differential amplifying transistor M1, the output terminal of the second differential amplifying transistor M2, the output terminal of the third differential amplifying transistor M3 and the output terminal of the fourth differential amplifying transistor M4 can be compensated, and further, the overall loss of the radio frequency front-end module is reduced.

The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A push-pull power amplifying circuit is characterized by comprising a radio frequency input port, a first push-pull power amplifier and a second push-pull power amplifier, wherein the radio frequency input port is respectively coupled to the input end of the first push-pull power amplifier and the input end of the second push-pull power amplifier;

the first push-pull power amplifier comprises a first differential amplification transistor, a second differential amplification transistor and a first capacitor, and the second push-pull power amplifier comprises a third differential amplification transistor, a fourth differential amplification transistor and a second capacitor; the first differential amplification transistor is arranged on the side far away from the second push-pull power amplifier, and the fourth differential amplification transistor is arranged on the side far away from the first push-pull power amplifier;

2. The push-pull power amplification circuit of claim 1, wherein the first and second capacitors are configured to make an output impedance of the first differential amplification transistor, an output impedance of the second differential amplification transistor, an output impedance of the third differential amplification transistor, and an output impedance of the fourth differential amplification transistor the same.

3. The push-pull power amplification circuit of claim 1, wherein a capacitance value of the first capacitor and a capacitance value of the second capacitor are different.

4. Push-pull power amplification circuit as claimed in claim 1, characterized in that the capacitance value of the first capacitance is larger than the capacitance value of the second capacitance.

5. The push-pull power amplification circuit of claim 4, wherein the capacitance value of the first capacitor is twenty percent greater than the capacitance value of the second capacitor.

6. The push-pull power amplification circuit of claim 1, wherein the radio frequency input port is configured to receive a radio frequency input signal and output a first radio frequency signal to an input of the first differential amplification transistor, a second radio frequency signal to an input of the second differential amplification transistor, a third radio frequency signal to an input of the third differential amplification transistor, and a fourth radio frequency signal to an input of the fourth differential amplification transistor, wherein a phase of the first radio frequency signal is a first phase, a phase of the second radio frequency signal is a second phase, a phase of the third radio frequency signal is a second phase, and a phase of the fourth radio frequency signal is a third phase.

7. The push-pull power amplification circuit of claim 1, wherein the first push-pull power amplifier further comprises a first balun, the second push-pull power amplifier further comprises a second balun;

8. The push-pull power amplification circuit of claim 7, wherein the first balun includes a first primary winding and a first secondary winding, the first primary winding including a first primary coil and a second primary coil; the first secondary winding comprises a first secondary coil and a second secondary coil; the first primary coil and the first secondary coil are coupled to form a first coupling coil, and the second primary coil and the second secondary coil are coupled to form a second coupling coil; the first coupling coil and the second coupling coil are adjacently arranged; the second balun includes a second primary winding and a second secondary winding, the second primary winding including a third primary coil and a fourth primary coil; the second secondary winding comprises a third secondary coil and a fourth secondary coil; the third primary coil and the third secondary coil are coupled to form a third coupling coil, and the fourth primary coil and the fourth secondary coil are coupled to form a fourth coupling coil; the third coupling coil and the fourth coupling coil are adjacently arranged.

9. The push-pull power amplification circuit of claim 7, wherein the first differential amplification transistor is a BJT transistor comprising a base, a collector and an emitter, the base of the first differential amplification transistor receiving an input first radio frequency signal, the collector of the first differential amplification transistor being coupled to the first input terminal of the first balun, the emitter of the first differential amplification transistor being grounded; the second differential amplification transistor is a BJT (bipolar junction transistor) and comprises a base electrode, a collector electrode and an emitter electrode, the base electrode of the second differential amplification transistor receives an input second radio-frequency signal, the collector electrode of the second differential amplification transistor is coupled to the second input end of the first balun, and the emitter electrode of the second differential amplification transistor is grounded; the base of the third differential amplification transistor receives an input third radio frequency signal, the collector of the third differential amplification transistor is coupled to the first input end of the second balun, and the emitter of the third differential amplification transistor is grounded; the base of the fourth differential amplification transistor receives an input fourth radio-frequency signal, the collector of the fourth differential amplification transistor is coupled to the second input end of the second balun, and the emitter of the fourth differential amplification transistor is grounded.

10. A radio frequency front end module is characterized by comprising a substrate, a push-pull power amplification chip arranged on the substrate, a first balun and a second balun arranged on the substrate,

the radio frequency input port is respectively coupled to the input end of the first differential amplification transistor, the input end of the second differential amplification transistor, the input end of the third differential amplification transistor and the input end of the fourth differential amplification transistor;

the first differential amplification transistor is connected with a first bonding pad of the push-pull power amplification chip, and the first bonding pad is in wire bonding with a first input end of the first balun; the second differential amplification transistor is connected with a second bonding pad of the push-pull power amplification chip, and the second bonding pad is in wire bonding with a second input end of the first balun; the third differential amplification transistor is connected with a third bonding pad of the push-pull power amplification chip, and the third bonding pad is in wire bonding with the first input end of the second balun; the fourth differential amplification transistor is connected with a fourth bonding pad of the push-pull power amplification chip, and the fourth bonding pad is in wire bonding with a second input end of the second balun;