CN218447871U - Quantum chip packaging circuit board and packaging box - Google Patents
Quantum chip packaging circuit board and packaging box Download PDFInfo
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- CN218447871U CN218447871U CN202223123467.4U CN202223123467U CN218447871U CN 218447871 U CN218447871 U CN 218447871U CN 202223123467 U CN202223123467 U CN 202223123467U CN 218447871 U CN218447871 U CN 218447871U
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Abstract
The application discloses a quantum chip packaging circuit board and a packaging box, which comprise a substrate for bearing a quantum chip, wherein the quantum chip is provided with a quantum circuit; the isolation element is hermetically connected with the substrate, and the isolation element and the substrate surround to form a sealed cavity, wherein the sealed cavity is used for accommodating the quantum chip; and a first end of the signal transmission element is electrically connected with the quantum circuit, and a second end of the signal transmission element is electrically connected with an external circuit. This application is through setting up isolation element on the base plate, utilizes isolation element and base plate to surround jointly and form sealed cavity, quantum chip install in the sealed cavity to can keep apart quantum chip and atmospheric environment, make quantum chip be in relatively sealed and stable environment, thereby effectively guaranteed quantum chip's performance, delayed quantum chip's performance decline trend greatly, thereby prolong quantum chip's life greatly.
Description
Technical Field
The application belongs to the technical field of quantum computing, and particularly relates to a quantum chip packaging circuit board and a packaging box.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. The quantum chip is a core component of a quantum computer, and the quantum chip is realized by various physical systems, such as a superconducting system, a semiconductor quantum dot, an ion trap, a diamond vacancy, a topological quantum, a photon and the like. The superconducting system is the current popular research direction, the superconducting quantum chip is formed by evaporating a superconducting metal layer on a substrate made of materials such as silicon wafers or sapphire, and then a quantum circuit and a quantum device are prepared on the superconducting metal layer by adopting the processes of exposure, development, etching and the like, so that the quantum chip with the quantum information processing function is obtained.
The quantum chip generally needs to be mounted on the package circuit board during operation, however, the performance of the quantum chip is significantly reduced with the passage of time, and the service life of the quantum chip is short.
It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a quantum chip package circuit board and encapsulation box to solve not enough among the prior art, it provides one kind can keep apart quantum chip and atmospheric environment's quantum chip package circuit board, with the life of extension quantum chip.
An embodiment of the present application provides a quantum chip package circuit board, including:
a substrate for carrying the quantum chip with a quantum circuit thereon;
the isolation element is connected with the substrate in a sealing mode, and the isolation element and the substrate surround to form a sealed cavity;
wherein the sealed cavity is used for accommodating the quantum chip;
and a first end of the signal transmission element is electrically connected with the quantum circuit, and a second end of the signal transmission element is electrically connected with an external circuit.
The quantum chip packaging circuit board as described above, wherein the sealed cavity is internally evacuated.
The quantum chip packaging circuit board as described above, wherein the isolation element is of a curved surface structure.
The quantum chip packaging circuit board as described above, wherein the projection of the isolation element completely covers the quantum chip along a direction perpendicular to the plane of the substrate.
The quantum chip packaging circuit board as described above, wherein the isolation element is a metal shell.
The quantum chip packaging circuit board as described above, wherein the signal transmission element is disposed inside the substrate, and a first end of the signal transmission element is located inside the sealed cavity and a second end of the signal transmission element is located outside the sealed cavity.
The quantum chip packaging circuit board as described above, wherein the isolation element includes an isolation plate and a sealing body located between the isolation plate and the substrate.
The quantum chip packaging circuit board is characterized in that the plane of the isolation plate is parallel to the plane of the substrate.
The quantum chip packaging circuit board as described above, wherein the sealed cavity is filled with a shielding gas.
The quantum chip packaging circuit board as described above, wherein the protective gas is nitrogen or inert gas.
Another embodiment of the present application provides a package, wherein the package comprises a quantum chip package circuit board as described above.
Compared with the prior art, this application has proposed a quantum chip package circuit board, has quantum circuit on the quantum chip, package circuit board includes: the substrate is used for bearing the quantum chip; the isolation element is hermetically connected with the substrate, and the isolation element and the substrate surround to form a sealed cavity, wherein the sealed cavity is used for accommodating the quantum chip; and a first end of the signal transmission element is electrically connected with the quantum circuit, and a second end of the signal transmission element is electrically connected with an external circuit. In this application, through set up isolation element on the base plate, utilize isolation element and base plate to surround jointly and form sealed cavity, quantum chip install in the sealed cavity, thereby can keep apart quantum chip and atmospheric environment, make quantum chip be in relatively closed and stable environment, thereby avoid quantum circuit isotructure on the quantum chip to directly expose in the atmospheric environment, with the hydrone in the atmospheric environment, oxygen molecule, material contact such as dust and impaired, thereby quantum chip's performance has effectively been guaranteed, quantum chip's performance decline trend has been delayed greatly, thereby quantum chip's life is prolonged greatly.
Drawings
Fig. 1 is a schematic structural diagram of a quantum chip package circuit board according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a second quantum chip packaging circuit board according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a third quantum chip packaging circuit board according to an embodiment of the present disclosure.
Description of reference numerals: 1-a substrate, 2-a quantum chip, 3-an isolation element, 4-a sealed cavity, 5-a signal transmission element and 6-a bonding wire;
31-partition board, 32-sealing body.
Detailed Description
The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to without contradiction.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of a quantum chip package circuit board according to an embodiment of the present disclosure.
With reference to fig. 1, a quantum chip packaging circuit board provided in an embodiment of the present application includes:
the substrate 1 is used for bearing the quantum chip 2, the quantum chip 2 is provided with structures such as a quantum circuit and a quantum element, in specific implementation, the surface of the substrate 1 is provided with a bearing area, and the quantum chip 2 is installed in the bearing area;
the isolation element 3 is hermetically connected with the substrate 1, the isolation element 3 and the substrate 1 enclose to form a sealed cavity 4, wherein the sealed cavity 4 is used for accommodating the quantum chip 2, and a projection of the isolation element 3 completely covers the quantum chip 2 along a direction perpendicular to a plane of the substrate 1, and exemplarily, the isolation element 3 is a shell structure that is reversely buckled on the substrate 1, the shell structure covers the quantum chip 2, and the shell structure is hermetically connected with the substrate 1; the projection of the shell structure completely covers the quantum chip 2, so that the quantum chip 2 is completely covered under the protection of the shell structure, specifically, the edge of the shell structure may be welded to the surface of the substrate 1, so that the inside of the shell structure and the substrate 1 surround to form a sealed cavity 4, and the shell structure is used to isolate the external atmospheric environment, so that the external atmospheric environment cannot be communicated with the inside of the sealed cavity 4; in the scheme, the quantum chip 2 is accommodated by the sealed cavity 4, so that the quantum chip 2 is isolated from the external atmospheric environment, and the aging and damage of structures such as a quantum circuit, a quantum element and the like on the quantum chip 2 caused by the contact of water molecules, oxygen molecules, dust and other substances in the atmospheric environment with the quantum chip 2 are avoided, so that the performance of the quantum chip 2 is effectively ensured, and the performance decline trend of the quantum chip 2 in the long-term storage process is greatly delayed;
the signal transmission element 5 has a first end for electrically connecting with the quantum circuit, and a second end for electrically connecting with an external circuit, for example, the signal transmission element 5 and the quantum circuit may be connected together by using a bonding wire 6, in a specific implementation, one end of the bonding wire 6 is welded with the first end of the signal transmission element 5, and the other end of the bonding wire 6 is welded with a connection terminal on the quantum circuit.
In this embodiment, through set up isolation element 3 on base plate 1, utilize isolation element 3 and base plate 1 to enclose jointly and form sealed cavity 4, quantum chip 2 install in sealed cavity 4, thereby can keep apart quantum chip 2 and atmospheric environment, make quantum chip 2 be in the environment that is relatively sealed and stable, thereby prevent that structures such as quantum circuit, quantum element on the quantum chip 2 from directly exposing in the atmospheric environment, and it is impaired with material contact such as hydrone in the atmospheric environment, oxygen molecule, dust, thereby effectively guaranteed the performance of quantum chip 2, quantum chip 2's performance decline trend has been delayed greatly, thereby greatly prolonged the life of quantum chip 2.
Fig. 2 is a schematic structural diagram of a second quantum chip packaging circuit board according to an embodiment of the present disclosure.
With reference to fig. 2, in some embodiments of the present application, for example, the quantum chip 2 may be mounted on the substrate 1 in a vacuum environment, the signal transmission element 5 and the quantum circuit are connected together by using the bonding wire 6, and the isolation element 3 is buckled on the substrate 1 in an inverted manner, so that the isolation element 3 and the substrate 1 surround to obtain the vacuum inside the sealed cavity 4, in specific implementation, the isolation element 3 adopts a curved surface structure, as an example, the isolation element 3 may adopt a thin shell structure, the thin shell structure has high stability, the atmospheric pressure acts on the isolation element 3 of the thin shell structure, and the isolation element 3 is uniformly stressed and is not easily deformed, thereby ensuring the safety of the quantum chip 2.
In this embodiment, the sealed cavity 4 is vacuum inside, so that the quantum chip 2 is in a vacuum environment, aging and damage of structures such as a quantum circuit and a quantum element on the quantum chip 2 are further delayed, and the service life of the quantum chip 2 is greatly prolonged.
In some embodiments of the present application, the signal transmission element 5 is disposed inside the substrate 1, and the first end of the signal transmission element 5 is located inside the sealed cavity 4, and the second end of the signal transmission element 5 is located outside the sealed cavity 4, for example, in a specific manner, the substrate 1 is a multilayer board, the signal transmission element 5 is a signal transmission line disposed inside the multilayer board, and the first end and the second end of the signal transmission line are respectively led out to the surface of the multilayer board for wiring, wherein the first end of the signal transmission line is located inside the sealed cavity 4, the first end of the signal transmission line is electrically connected to the quantum circuit on the quantum chip 2 through a bonding wire 6, and the second end of the signal transmission line is located outside the sealed cavity 4 for electrically connecting to an external circuit.
In this embodiment, the signal transmission element 5 is disposed inside the substrate 1, so that the quantum chip 2 and the external circuit can be electrically connected, and the sealing environment of the sealed cavity 4 can be prevented from being damaged.
Fig. 3 is a schematic structural diagram of a third quantum chip package circuit board according to an embodiment of the present disclosure.
Referring to fig. 3, in some embodiments of the present application, the isolation component 3 includes an isolation plate 31 and a sealing body 32 located between the isolation plate 31 and the substrate 1, as an example, the sealing body 32 is annular, and the sealing body 32 is used to fill a gap between the edge of the isolation plate 31 and the substrate 1, so as to obtain the sealed cavity 4, illustratively, a specific manner is that the isolation plate 31 may be a metal plate or a non-metal plate, the sealing body 32 is a sealing adhesive, in particular, in implementation, a plane where the isolation plate 31 is located is parallel to the substrate 1, and is perpendicular to the direction of the substrate 1, and the quantum chip 2 is located within a projection range of the sealing body 32, so as to ensure that the quantum chip 2 is located in the sealed cavity 4.
In this embodiment, utilize division board 31, seal 32 to build sealed cavity 4, greatly reduced sealed cavity 4's the difficulty of building, exemplary, with division board 31 with 1 parallel opposition of base plate fills the round sealed glue between division board 31's edge and base plate 1, treats sealed glue solidification back and can obtain sealed cavity 4, because quantum chip 2 is located in sealed cavity 4, can further prolong quantum chip 2's shelf life to quantum chip 2's life has been prolonged greatly.
In some embodiments of the present application, the inside of the sealed cavity 4 is filled with a shielding gas, the sealed cavity 4 is filled with the shielding gas, and the quantum chip 2 is further protected from being connected with air.
In this embodiment, the sealed cavity 4 is filled with a protective gas with stable properties, and for example, the sealed cavity 4 is filled with nitrogen or an inert gas, which has stable properties and does not react with structures such as a quantum circuit and a quantum element on the quantum chip 2, so that the storage life of the quantum chip 2 is further prolonged, and the service life of the quantum chip 2 is greatly prolonged.
This application on the other hand provides a packaging box, the packaging box includes above-mentioned embodiment quantum chip package circuit board, during concrete implementation, the packaging box includes detachable lid and box body, quantum chip package circuit board install in the box body.
In this embodiment, by using the quantum chip package circuit board, the package box has a function of prolonging the shelf life of the quantum chip 2, so that the service life of the quantum chip 2 installed in the package box is greatly prolonged. Here, it should be noted that: the quantum chip packaging circuit board arranged in the packaging box has a structure similar to that of the quantum chip packaging circuit board embodiment, and has the same beneficial effects as the quantum chip packaging circuit board embodiment.
The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.
Claims (11)
1. A quantum chip package circuit board, comprising:
a substrate (1) for carrying a quantum chip (2), the quantum chip (2) having a quantum circuit thereon;
the isolation element (3) is connected with the substrate (1) in a sealing mode, and a sealed cavity (4) is formed by the isolation element (3) and the substrate (1) in a surrounding mode;
wherein the sealed cavity (4) is used for accommodating the quantum chip (2);
the signal transmission element (5), the first end of signal transmission element (5) is used for with the quantum circuit electricity is connected, the second end of signal transmission element (5) is used for with external circuit electricity.
2. The quantum chip package circuit board of claim 1, wherein the sealed cavity (4) is evacuated.
3. The quantum chip package circuit board of claim 2, wherein the isolation element (3) adopts a curved surface structure.
4. A quantum chip package circuit board according to claim 3, characterized in that the projection of the spacer element (3) completely covers the quantum chip (2) in a direction perpendicular to the plane of the substrate (1).
5. The quantum chip package circuit board of claim 1, wherein the spacer element (3) is a metal housing.
6. The quantum chip package circuit board according to claim 5, wherein the signal transmission element (5) is arranged inside the substrate (1), and wherein a first end of the signal transmission element (5) is located inside the sealed cavity (4) and a second end of the signal transmission element (5) is located outside the sealed cavity (4).
7. The quantum chip package circuit board according to claim 1, wherein the spacer element (3) comprises a spacer plate (31) and a seal (32) between the spacer plate (31) and the substrate (1).
8. The quantum chip package circuit board of claim 7, wherein the plane of the isolation plate (31) and the plane of the substrate (1) are parallel to each other.
9. The quantum chip package circuit board according to any of claims 5 to 8, wherein the sealed cavity (4) is filled with a shielding gas inside.
10. The quantum chip packaging circuit board of claim 9, wherein the shielding gas is nitrogen or an inert gas.
11. A package comprising a quantum chip packaging circuit board according to any of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223123467.4U CN218447871U (en) | 2022-11-24 | 2022-11-24 | Quantum chip packaging circuit board and packaging box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223123467.4U CN218447871U (en) | 2022-11-24 | 2022-11-24 | Quantum chip packaging circuit board and packaging box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218447871U true CN218447871U (en) | 2023-02-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223123467.4U Active CN218447871U (en) | 2022-11-24 | 2022-11-24 | Quantum chip packaging circuit board and packaging box |
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| Country | Link |
|---|---|
| CN (1) | CN218447871U (en) |
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- 2022-11-24 CN CN202223123467.4U patent/CN218447871U/en active Active
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