CN111627870A

CN111627870A - Semiconductor packaging device

Info

Publication number: CN111627870A
Application number: CN202010470531.2A
Authority: CN
Inventors: 谢建友; 马晓波
Original assignee: Technology Research and Development Branch of Tongfu Microelectronics Co Ltd
Current assignee: Technology Research and Development Branch of Tongfu Microelectronics Co Ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-09-04

Abstract

The application discloses semiconductor package device, this semiconductor package device includes: the chip packaging structure comprises a substrate, a main chip, a conductive piece, a plastic packaging layer, a first packaging module and a bonding wire; the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surface of the conductive piece; the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip; and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic packaging layer and the first packaging module. Through the mode, the functional surface of the main chip of the semiconductor packaging device is protected below the plastic packaging layer, the air tightness of the surface of the main chip is better, the conductive piece is electrically connected with the connecting pad on the functional surface of the main chip and electrically connected with the first packaging module, and the connecting structure is more stable and reliable.

Description

Semiconductor packaging device

Technical Field

The present application relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor package device.

Background

In the existing system-level packaging, a plurality of active elements or passive elements which have different functions and are prepared by different processes are packaged firstly, then are connected with a chip in a routing mode after being manufactured into a packaging module, and are glued at bonding points of routing on a functional surface of the chip, but the strength and the air tightness of the gluing position are poor, the influences of stress and water vapor are great, and the reliability of the formed semiconductor packaging device is low.

Disclosure of Invention

The technical problem that this application mainly solved provides a semiconductor package device, can make the gas tightness on main chip surface better with the protection of the functional surface of main chip under the plastic envelope layer, and electrically conductive piece is connected with the connection pad electricity on the functional surface of main chip and is connected with first encapsulation module electricity, makes connection structure more reliable and more stable.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: the chip packaging structure comprises a substrate, a main chip, a conductive piece, a plastic packaging layer, a first packaging module and a bonding wire; the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surfaces of the conductive pieces; the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip; and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic package layer and the first packaging module.

The plastic packaging layer is provided with a first opening at a position corresponding to the connecting pad, the conductive piece is a conductive column, and the conductive column fills the first opening.

Wherein, the position department that the plastic envelope layer corresponds the connection pad is provided with first opening, electrically conductive piece includes: sputtering a metal layer to cover the inner wall of the first opening; and the conductive column is positioned on the sputtering metal layer and fills the first opening.

Wherein the semiconductor package device further comprises: and the soft plating layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the soft plating layer.

The soft coating comprises a nickel layer and a gold layer which are sequentially stacked, wherein the nickel layer is positioned between the conductive piece and the gold layer.

Wherein the semiconductor package device further comprises: further comprising: and the solder layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the solder layer.

Wherein the semiconductor package device further comprises: further comprising: and the non-conductive adhesive layer is positioned on the surface of one side, facing the substrate, of the main chip and the surface of one side, facing the substrate, of the first packaging module.

Wherein the semiconductor package device further comprises: further comprising: the protective shell is positioned on one side of the substrate, and the main chip, the conductive piece, the plastic package layer, the first packaging module and the bonding wire are contained in the containing space of the protective shell.

The bonding wire is one of a gold wire, a silver wire, a copper wire, an aluminum wire and an aluminum-clad copper wire.

The first packaging module is a pre-packaged micro-electro-mechanical system, and the main chip is an application-specific integrated chip.

The beneficial effect of this application is: the utility model provides a semiconductor package device, its main chip protection is under the plastic envelope layer, and the functional surface of main chip is not directly exposed, has improved the gas tightness of main chip functional surface to electrically conductive on the connection pad on the main chip functional surface, pass through the bonding wire electricity with the first encapsulation module that has packaged in advance and be connected, improved main chip and first encapsulation module connection structure's stability, reduced the influence of stress, make and connect more reliably.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic diagram of a semiconductor package device according to an embodiment of the present application;

FIG. 2 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of FIG. 1;

FIG. 3 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 2;

FIG. 4 is a schematic flowchart of an embodiment corresponding to step S101 in FIG. 2;

FIG. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 4;

FIG. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 4;

FIG. 5c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 4;

FIG. 6 is a flowchart illustrating an embodiment corresponding to step S204 in FIG. 4;

FIG. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in FIG. 6;

FIG. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 6;

FIG. 8 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 2;

FIG. 9 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;

FIG. 10 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of FIG. 9;

FIG. 11 is a schematic structural diagram of an embodiment corresponding to step S401 in FIG. 10;

FIG. 12 is a flowchart illustrating an embodiment corresponding to step S402 in FIG. 10;

FIG. 13a is a schematic structural diagram of an embodiment corresponding to step S501 in FIG. 12;

FIG. 13b is a schematic structural diagram of an embodiment corresponding to step S502 in FIG. 12;

FIG. 14 is a schematic structural diagram of yet another embodiment of a semiconductor package device of the present application;

FIG. 15 is a schematic structural diagram of yet another embodiment of a semiconductor package device of the present application;

fig. 16 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of fig. 15;

FIG. 17a is a schematic structural diagram of an embodiment corresponding to step S601 in FIG. 16;

FIG. 17b is a schematic structural diagram of an embodiment corresponding to step S602 in FIG. 16;

FIG. 17c is a schematic structural diagram of an embodiment corresponding to step S603 in FIG. 16;

FIG. 17d is a schematic structural diagram of an embodiment corresponding to step S604 in FIG. 16;

fig. 17e is a schematic structural diagram of an embodiment corresponding to the step S604 in fig. 16.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor package device 300 according to the present application, including: substrate 20, main chip 10, conductive member 12, molding compound 14, first package module 200 and bonding wire 22. The main chip 10 is located on one side of the substrate 20, the non-functional surface of the main chip 10 faces the substrate 20, the conductive member 12 is located on a connection pad (not shown) on the functional surface of the main chip 10 and electrically connected to the connection pad, and the molding compound layer 14 covers the main chip 10 and the side surface of the conductive member 12. The first package module 200 is located at one side of the substrate 20 and is disposed on the same layer as the main chip 10, and two ends of the bonding wire 22 are electrically connected to the surface of the conductive member 12 exposed from the molding compound layer 14 and the first package module 200, respectively.

Specifically, the main chip 10 and the first package module 200 are disposed on the same side of the substrate 20, the first package module 200 is a pre-packaged integrated module, and the main chip 10 and the first package module 200 are attached to the substrate 20 by a non-conductive adhesive. Therefore, in practical applications, the semiconductor package device 300 further includes a non-conductive adhesive layer (not shown), which is a relatively thin adhesive layer, not shown, located on the surface of the main chip 10 facing the substrate 20 and the surface of the first package module 200 facing the substrate 20. The non-conductive adhesive layer can protect the circuit structure on the substrate 20 and reduce the probability of short circuit of the circuit structure on the substrate 20.

In the semiconductor package device 300 provided by this embodiment, the main chip 10 is protected under the molding layer 14, the functional surface of the main chip 10 is not directly exposed, so that the air tightness of the functional surface of the main chip 10 is improved, and the conductive member 12 on the connection pad on the functional surface of the main chip 10 is electrically connected to the first package module 200 that has been packaged in advance through the bonding wire 22, so that the stability of the connection structure between the main chip 10 and the first package module 200 is improved, the influence of stress is reduced, and the connection is more reliable.

Specifically, referring to fig. 2, fig. 2 is a schematic flow chart of an embodiment of forming the semiconductor package device of fig. 1, including:

step S101: and forming a conductive piece on the connecting bonding pad on the functional surface of the main chip, forming a plastic package layer on the side surface and the functional surface of the main chip, and exposing one end of the conductive piece from the plastic package layer.

Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 2, wherein molding layers 14 are disposed on two sides and functional surfaces of a main chip 10, a circuit structure (not shown) on the functional surface of the main chip 10 is covered under the molding layers 14, the main chip 10 is not directly exposed, and the air tightness and the waterproof rating thereof are improved, and further, a conductive member 12 is disposed on a connection pad on the surface of the main chip 10, and the conductive member 12 is electrically connected to the connection pad on the main chip 10, and one end surface of the conductive member is exposed from the molding layers 14 for electrically connecting the main chip 10 under the molding layers 14 to other electrical components.

In an application manner, please refer to fig. 4 in combination with fig. 1, where fig. 4 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 2, and step S101 specifically includes:

step S201: and forming photoresist on the functional surface of the main chip, and forming a first opening at the position of the photoresist corresponding to the connecting pad.

Specifically, referring to fig. 5a, fig. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 4, in which a non-functional surface of a main chip 10 is attached to a substrate 20, a photoresist 16 is coated on the functional surface of the main chip 10, the photoresist 16 covers the functional surface of the main chip 10, in other embodiments, the side surfaces of the main chip 10 may be covered together, the photoresist 16 corresponding to the connection pad position on the functional surface of the main chip 10 is exposed, and a first opening (not shown) is formed on the molding layer 14 on the connection pad by using a chemical developer.

Step S202: and forming a conductive member in the first opening.

Specifically, referring to fig. 5b, fig. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 4, where the photoresist 16 protects the functional surface of the main chip 10 except for the connection pads, and the conductive member 12 is formed in the first opening.

In this application, the conductive member 12 shown in fig. 1 is a conductive pillar, which fills the first opening, and the conductive pillar may be made of at least one of copper, silver, nickel, tin, and other metals, and may be formed by electroplating.

Step S203: and removing the photoresist.

Specifically, referring to fig. 5c, fig. 5c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 4, and the photoresist 16 in fig. 5b is removed to expose the functional surface and the side surface of the main chip 10 and the surface and the side surface of the conductive member 12.

Step S204: and forming a plastic package layer on the side surface of the main chip and the side surface of the conductive piece, wherein one end of the conductive piece is exposed out of the plastic package layer.

In a specific application scenario, please refer to fig. 6, fig. 6 is a flowchart illustrating an embodiment corresponding to step S204 in fig. 4, where step S204 specifically includes:

step S301: and forming plastic packaging layers on the side surface and the functional surface of the main chip, wherein the plastic packaging layers cover the conductive parts.

Specifically, referring to fig. 7a, fig. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in fig. 6, a molding layer 14 is formed on a side surface and a functional surface of the main chip 10, the molding layer 14 covers the conductive member 12 as a whole, and if the molding layer 14 is directly controlled to be formed, it is difficult to completely cover the side surface of the conductive member 12 but expose a surface of one end of the conductive member 12 away from the main chip 10, so that the entire conductive member 12 is covered first to ensure that the side surface of the conductive member 12 is completely covered by the molding layer 14.

Step S302: and grinding one side of the plastic packaging layer, which is far away from the functional surface of the main chip, so that the plastic packaging layer is flush with the conductive piece, and the conductive piece is exposed out of the plastic packaging layer.

Specifically, referring to fig. 7b, fig. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in fig. 6, a side of the molding layer 14 away from the functional surface of the main chip 10 is ground, and further, the side surface of the main chip 10 and the side surface of the conductive member 12 are covered by the molding layer 14, and one end of the conductive member 12 is exposed from the molding layer 14, that is, the molding layer 14 does not cover the surface of one end of the conductive member 12, so that the conductive member 12 is electrically connected to other electrical components.

Step S102: one end of the conductive piece is electrically connected with the first packaging module by a routing mode.

Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 2, in which a first package module 200 is attached to a substrate 20, and two ends of a bonding wire 22 are electrically connected to one end of a conductive member 12 and the first package module 200 respectively in a wire bonding manner. The main chip 10 is under the plastic packaging layer 14, the conductive piece 12 on the connecting pad of the main chip is exposed out of the plastic packaging layer 14, the whole structure of the main chip 10 is more stable, and the structure of the bonding position of the bonding wire 22 and the conductive piece 12 is more stable relative to the structure of direct bonding on the connecting pad of the main chip 10, so that the influence of stress on the bonding point is reduced.

In the semiconductor package device 300 provided in this embodiment, the plastic package layer 14 is provided with a first opening at a position corresponding to the connection pad, the conductive member 12 is a conductive pillar, the conductive pillar fills the first opening, a material of the conductive pillar may be selected according to a cost and a signal transmission requirement, copper may be usually selected, and one end of the conductive member 12 is exposed from the plastic package layer 14 and electrically connected to the bonding wire 22.

Further, in the semiconductor package device 300, the bonding wire 22 is one of a gold wire, a silver wire, a copper wire, an aluminum wire, and an aluminum-clad copper wire, and the material thereof can be selected according to the requirements of cost and signal transmission rate.

Referring to fig. 9, fig. 9 is a schematic structural diagram of another embodiment of a semiconductor package device 300a of the present application, which has a structure similar to that of the semiconductor package device 300 of fig. 1, and also includes a substrate 20, a main chip 10, a molding compound 14, a first package module 200, and a bonding wire 22. The difference between the two is that conductive member 12a in fig. 9 includes sputtered metal layer 120 and conductive post 122.

Referring to fig. 10, fig. 10 is a schematic flow chart illustrating one embodiment of forming the semiconductor package device of fig. 9, including:

step S401: and forming a plastic packaging layer on the side surface and the functional surface of the main chip, and forming a second opening at the position of the plastic packaging layer corresponding to the connecting pad.

Specifically, referring to fig. 11, fig. 11 is a schematic structural view of an embodiment corresponding to step S401 in fig. 10, in which a non-functional surface of the main chip 10 is attached to the substrate 20, and a molding layer 14 is formed on a side surface and a functional surface of the main chip 10, the molding layer 14 can effectively fix the position of the main chip 10, so that the main chip 10 is more stable on the substrate 20, a second opening (not shown) is formed in the molding layer 14 corresponding to the connection pad, and a blank portion in the middle of the molding layer 14 is the second opening on the molding layer 14.

Step S402: and forming a conductive member in the second opening.

Specifically, referring to fig. 12, fig. 12 is a flowchart illustrating an embodiment corresponding to step S402 in fig. 10, where step S402 specifically includes:

step S501: and forming a sputtering metal layer in the second opening and on the surface of the plastic packaging layer adjacent to the second opening.

Specifically, referring to fig. 13a, fig. 13a is a schematic structural view of an embodiment corresponding to step S501 in fig. 12, wherein a sputtered metal layer 120, such as a thin copper layer, is formed in the second opening. Fig. 13a is merely schematic, and in practical applications, the sputtered metal layer 120 is thin, and for illustration in the figure, the thickness of the sputtered metal layer 120 is relatively thick. Due to the sputtering process, a sputtered metal layer 120 is also formed on the molding layer 14 adjacent to the second opening, and the sputtered metal layer 120 adheres more closely to the molding layer 14.

Step S502: and forming the conductive columns on the sputtered metal layer at the positions corresponding to the second openings.

Specifically, referring to fig. 13b, fig. 13b is a schematic structural view of an embodiment corresponding to step S502 in fig. 12, electroplating is performed on the sputtered metal layer 120 in the second opening to form a conductive pillar 122, and the conductive pillar 122 fills the second opening to increase a contact surface capable of being electrically connected to other electrical elements.

Step S503: and etching to remove the sputtered metal layer on the surface of the plastic package layer.

Specifically, referring to fig. 9 again, the conductive element 12a includes a conductive pillar 122 and a sputtered metal layer 120 located below the conductive pillar 122. The sputtered metal layer 120 on the surface of the molding compound layer 14 is etched away, and if the conductive pillar 122 protrudes from the molding compound layer 14, the portion of the conductive pillar 122 protruding from the molding compound layer 14 is etched together, so that the conductive pillar 122 and the sputtered metal layer 120 are flush with the surface of the molding compound layer 14 on the side away from the main chip 10.

Further, a wire bonding process is performed between the conductive member 12a and the first package module 200, so that the conductive member 12a is electrically connected to the first package module 200

In the semiconductor package device 300a, the molding layer 14 is provided with a first opening at a position corresponding to the connection pad, the conductive member 12a includes a sputtered metal layer 120 and a conductive pillar 122, the sputtered metal layer 120 covers an inner wall of the first opening, and the conductive pillar 122 is located on the sputtered metal layer 120 and fills the first opening. Sputtered metal layer 120 can be more tightly bonded to molding layer 14, and conductive pillar 122 formed by electroplating on sputtered metal layer 120 is more firmly bonded to sputtered metal layer 120.

Referring to fig. 14, fig. 14 is a schematic structural diagram of a semiconductor package device according to still another embodiment of the present application, and a semiconductor package device 300b in fig. 14 has a structure similar to that of the semiconductor package device 300 in fig. 1, and also includes a substrate 20, a main chip 10, a conductive member 12, a molding compound layer 14, a first package module 200, and a bonding wire 22. The semiconductor package device 300b further includes a soft plated layer 24, the soft plated layer 24 is disposed on the surface of the conductive member 12 exposed from the molding layer 14, and the bonding wire 22 is electrically connected to the soft plated layer 24.

Specifically, one end surface of the conductive member 12 is treated to make the one end surface softer for wire bonding. The conductor at one end of the conductive element 12 is plated with the nickel layer 26 and then with the gold layer 28, so that a softer soft plating layer 24 is formed on one end of the conductive element 12 for subsequent wire bonding.

Specifically, the soft plating layer 24 includes a nickel layer 26 and a gold layer 28, which are sequentially stacked, wherein the nickel layer 26 is located between the conductive member 12 and the gold layer 28. Nickel layer 26 prevents diffusion between gold layer 28 and conductive device 12, particularly when conductive device 12 is made of copper. The gold layer 28 is spherical or wedge-shaped and is flexible, so that the bonding wire 22 and the gold layer 28 are more easily bonded and firmly connected during wire bonding. For the semiconductor package device 300b in fig. 14, a wire bonding process is also required between the conductive member 12 and the first package module 200, and the bonding wires 22 are selected to bond gold wires and the gold layer 28.

In other embodiments, the surface of the end of the conductive device 12 exposed out of the molding layer 14 may also be coated with molten tin or lead and flattened by heated and compressed air, so that, in other embodiments, the semiconductor package device 300 in fig. 1 may further include a solder layer (not shown) on the surface of the conductive device 12 exposed out of the molding layer 14, the bonding wires 22 are electrically connected to the solder layer, and the solder layer may make the bonding wires 22 and the solder layer easier to bond and lower in cost in the subsequent wire bonding.

Referring to fig. 15, fig. 15 is a schematic structural diagram of a semiconductor package device 300c in fig. 15 according to still another embodiment of the present invention, which is similar to the semiconductor package device 300 in fig. 1 in structure and includes a substrate 20b, a main chip 10b, a conductive member 12b, a molding compound layer 14b, a first package module 200b, and a bonding wire 22 b. The difference between the two is that the semiconductor package device 300c further includes: a protective shell 40.

Specifically, referring to fig. 16, fig. 16 is a schematic flow chart of an embodiment of forming the semiconductor package device of fig. 15, including:

step S601: and pasting the non-functional surface of at least one main chip on the carrier plate.

Specifically, referring to fig. 17a, fig. 17a is a schematic structural diagram of an embodiment corresponding to step S601 in fig. 16, the carrier 11 in fig. 17a only schematically shows one of the regions, in practical applications, the carrier 11 may be a larger region divided into a plurality of small regions, a main chip 10b is attached in each small region, the number of the main chips 10b on the carrier 11 may indicate that self-powered equipment is actually required, and the carrier 11 is formed of a hard material such as metal, plastic, and the like.

Step S602: and forming conductive parts on the connecting bonding pads on the functional surface of the main chip and forming a plastic package layer on the side surface and the functional surface of the main chip.

Specifically, please refer to fig. 17b, fig. 17b is a schematic structural diagram of an embodiment corresponding to step S602 in fig. 16, and this step corresponds to step S101 in fig. 2, a conductive component 12b and a plastic package layer 14b are formed on a main chip 10b in multiple regions on a carrier board 11.

Step S603: removing the carrier plate; and cutting off a part of the plastic packaging layer between the adjacent main chips to obtain a first packaging body containing the single main chip, the conductive piece and the plastic packaging layer.

Specifically, referring to fig. 17c, fig. 17c is a schematic structural diagram of an embodiment corresponding to step S603 in fig. 16, the carrier 11 is removed, and when at least two main chips 10b are attached to the carrier 11, the molding layer 14b between the main chips 10b is cut to obtain a single first package 100, where the first package 100 includes at least one main chip 10b, a conductive member 12b, and a molding layer 14 b.

Step S604: the first packaging body and the first packaging module are pasted on the substrate, and one end of the conductive piece is electrically connected with the first packaging module in a routing mode.

Specifically, referring to fig. 17d, fig. 17d is a schematic structural view of an embodiment corresponding to step S604 in fig. 16, in which the first package body 100 and the first package module 200b are adhered to the substrate 20b, and the first package body 100 and the first package module 200b are electrically connected by wire bonding, which refers to step S102.

Further, referring to fig. 17e, fig. 17e is a structural schematic diagram of an embodiment corresponding to the step S604 in fig. 16, where a protective shell 40 is disposed on the periphery of the first package body 100 and the first package module 200b, so that the first package body 100 and the first package module 200b are accommodated in the protective shell 40. The first package body 100 and the first package module 200b are disposed on the substrate 20b, and the protective shell 40 prevents the first package body 100 and the first package module 200b from being exposed to the outside, so as to be suitable for application scenarios with higher requirements on waterproof and dustproof levels.

In a specific Application scenario, the main chip 10b is an Application Specific Integrated Circuit (ASIC), the first package module 200b is a pre-packaged Micro-Electro-Mechanical System (MEMS), and further the connection between the ASIC and the MEMS is more stable and the signal transmission is stable, and the computing power and the computing efficiency of the ASIC are directly customized according to the requirement of a specific algorithm, so that the ASIC can have a small size, low power consumption, high reliability, high security, high computing performance, and high computing efficiency, and when used in combination with the MEMS, the semiconductor package device 300c has a smaller size, but has more excellent performance for a specific function.

In other embodiments, the first package module 200b may include any one of active devices, passive devices, optoelectronic chips, and biochips, and the main chip 10b may be any one of a CPU chip, a GPU chip, an FPGA chip, an SOC chip, and an MCU chip.

In the semiconductor package device 300c provided by this embodiment, the first package body 100 and the first package module 200b are protected under the protective case 40, so that the first package body 100 and the first package module 200b are not exposed outside, and the main chip 10b in the first package body 100 is protected under the molding layer 14b and is electrically connected to the first package module 200b through the conductive member 12b, and the main chip 10b has high waterproof and dustproof level, good air tightness and stable structure, and is suitable for scenes with high requirements on the structure and the air tightness level, such as a vehicle-mounted environment and an outdoor environment.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A semiconductor package device, comprising:

a substrate;

the chip comprises a main chip, a conductive piece and a plastic package layer, wherein the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surfaces of the conductive pieces;

the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip;

and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic packaging layer and the first packaging module.

2. The semiconductor package device of claim 1,

3. The semiconductor package device of claim 1,

the position department that the plastic envelope layer corresponds the connection pad is provided with first opening, electrically conductive piece includes:

sputtering a metal layer to cover the inner wall of the first opening;

and the conductive column is positioned on the sputtering metal layer and fills the first opening.

4. The semiconductor package device of claim 1, further comprising: and the soft plating layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the soft plating layer.

5. The semiconductor package device of claim 4,

6. The semiconductor package device of claim 1, further comprising:

and the solder layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the solder layer.

7. The semiconductor package device of claim 1, further comprising:

and the non-conductive adhesive layer is positioned on the surface of one side, facing the substrate, of the main chip and the surface of one side, facing the substrate, of the first packaging module.

8. The semiconductor package device of claim 1, further comprising:

the protective shell is positioned on one side of the substrate, and the main chip, the conductive piece, the plastic package layer, the first packaging module and the bonding wire are contained in the containing space of the protective shell.

9. The semiconductor package device of claim 1, wherein the bonding wire is one of a gold wire, a silver wire, a copper wire, an aluminum wire, and an aluminum-clad copper wire.

10. The semiconductor package device of claim 1, wherein the first package module is a pre-packaged mems and the main chip is an asic chip.