CN218383556U

CN218383556U - Mask, array substrate and display panel

Info

Publication number: CN218383556U
Application number: CN202222422129.4U
Authority: CN
Inventors: 王光加; 黄世帅; 康报虹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-09-13
Filing date: 2022-09-13
Publication date: 2023-01-24
Anticipated expiration: 2032-09-13

Abstract

The application discloses a mask, an array substrate and a display panel, wherein the mask comprises a substrate, a second mask area and a first mask area are arranged on the substrate, the second mask area and the first mask area respectively comprise a source electrode exposure area, a drain electrode exposure area and a channel exposure area, and the channel exposure area of the first mask area comprises a first light transmission area; the channel exposure area of the second mask area comprises a first light transmission area and a second light transmission area, the second light transmission area is arranged in the first light transmission area, and the light transmittance of the second light transmission area is greater than that of the first light transmission area. The luminousness through setting up first printing opacity district and second printing opacity district in the channel exposure area in second mask district is greater than the luminousness in first printing opacity district in this application to luminousness when promoting the preparation of gate drive district reduces the luminousness difference of gate drive district in the operating area, avoids unable reasonable setting gate drive district and operating area in thin film transistor's the channel width.

Description

Mask, array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to a mask, an array substrate and a display panel.

Background

The array substrate line scanning driving circuit is manufactured by manufacturing a series of thin film transistors on an array substrate to realize the line-by-line scanning function of the grid electrode. The array substrate is generally provided with a display region, an operable region, a gate driving region, and the like. When the thin film transistor is designed by adopting the 4mask process, the number of the thin film transistors in the operable area is extremely small because the gate driving area comprises a plurality of dense thin film transistors. Under the condition that the areas of the gate driving area and the operable area are the same, the gate driving area is basically composed of a half-tone mask plate and a metal layer, and only a small part of the area penetrates 100%; while the majority of the operable zone is 100% penetrated. The light transmittance of the metal layer in the source and drain electrode exposure area on the mask plate is 0, and the light transmittance of the semi-permeable membrane is 30-50%, so that the transmittance of the mask area corresponding to the gate drive area is far lower than that of the mask area corresponding to the operable area.

Due to the light transmittance difference, if the channel width of the thin film transistor in the operable region is within a reasonable range, the channel width of the thin film transistor in the gate drive region becomes very small; if the channel width of the thin film transistor in the gate driving region is within a reasonable range, the channel width of the thin film transistor in the operable region is large, so that the channel widths of the thin film transistor in the gate driving region and the thin film transistor in the operable region cannot be guaranteed to be within the reasonable range, and finally, the display picture of the display is abnormal.

The above is only for the purpose of assisting understanding of the technical solutions of the present application, and does not represent an admission that the above is prior art.

SUMMERY OF THE UTILITY MODEL

The main aim at of this application provides a mask version, array substrate and display panel, sets up the second printing opacity district through the channel exposure district in the mask district that the gate drive district corresponds, and it is too big to reduce gate drive district and operational area luminousness difference, has solved among the prior art unable reasonable technical problem who sets up thin film transistor's in gate drive district and the operational area channel width.

In order to achieve the above object, the present application provides a mask for manufacturing an array substrate, the mask includes a substrate, a first mask region and a second mask region are disposed on the substrate, the first mask region is located at the periphery of the second mask region,

the first mask area is used for manufacturing a first switch unit of the array substrate, the second mask area is used for manufacturing a second switch unit of the array substrate, and the first mask area and the second mask area respectively comprise a source electrode exposure area, a drain electrode exposure area and a channel exposure area; the channel exposure region of the first mask region comprises a first light transmission region, and the channel exposure region of the second mask region comprises a first light transmission region and a second light transmission region; the second light transmission area is arranged in the first light transmission area, and the light transmittance of the second light transmission area is greater than that of the first light transmission area.

Optionally, the source exposure region comprises a first metal arm; the drain exposure region includes: a second metal arm, a third metal arm and a connecting metal arm;

the second metal arm, the third metal arm and the connecting metal arm form a U-shaped groove, and the first metal arm is positioned in the U-shaped groove;

the second light-transmitting area comprises a first through hole and a second through hole;

the first through hole is located between the first metal arm and the second metal arm, and the second through hole is located between the first metal arm and the third metal arm.

Optionally, the distance from the first via to the first metal arm and the second metal arm is the same; the distance from the second through hole to the first metal arm and the third metal arm is the same.

Optionally, the light-transmitting region further includes a connecting via disposed between the first metal arm and the connecting metal arm;

the connecting through hole, the first through hole and the second through hole form a U-shaped through hole.

Optionally, the width of the first through hole is between 1/3 and 1/2 of the interval width between the first metal arm and the second metal arm;

the width of the second through hole is between 1/3 and 1/2 of the interval width between the first metal arm and the third metal arm.

In addition, in order to achieve the above object, the present application further provides an array substrate, the array substrate is manufactured by using the above mask, and is provided with a display area and a non-display area, the non-display area is provided with a first switch unit, and the display area is provided with a second switch unit; the non-display area corresponds to the first mask area, and the display area corresponds to the second mask area; the source electrode, the drain electrode and the channel of the switch unit are respectively in one-to-one correspondence with the source electrode exposure area, the drain electrode exposure area and the channel exposure area, and the channel width of the first switch unit is equal to the channel width of the second switch unit.

In addition, in order to achieve the above object, the present application further provides a display panel, where the display panel includes a color film substrate, a liquid crystal layer, and the array substrate, and the liquid crystal layer is located between the color film substrate and the array substrate.

The application provides a mask, an array substrate and a display panel, wherein the mask comprises a substrate, a first mask area and a second mask area are arranged on the substrate, the first mask area is located on the periphery of the second mask area, the second mask area and the first mask area respectively comprise a source electrode exposure area, a drain electrode exposure area and a channel exposure area, and the channel exposure area of the first mask area comprises a first light transmission area; the channel exposure area of second mask district includes first printing opacity district and second printing opacity district, second printing opacity district is located in the first printing opacity district, just the luminousness in second printing opacity district is greater than the luminousness in first printing opacity district. Set up first printing opacity district and second printing opacity district just through the channel exposure district in second mask district in this application the luminousness in second printing opacity district is greater than the luminousness in first printing opacity district, the channel exposure district in first mask district only sets up first printing opacity district to luminousness when promoting the preparation of gate drive district reduces the luminousness difference of gate drive district in the operating area, avoids unable reasonable setting gate drive district and operating area in thin film transistor's channel width.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only the first embodiment, the second embodiment, and the third embodiment of the array substrate of the present application, the embodiment of the display panel, and the corresponding drawings of the embodiment of the display, and for those skilled in the art, other drawings can be obtained according to the structures shown in these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a second mask region of a mask according to a first embodiment of the mask of the present application;

FIG. 2 is a cross-sectional view of a second masked region of a mask according to a first embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of an array substrate according to the present application;

FIG. 4 (A) is a cross-sectional view of the thin film transistor of the present application for fabricating an active region;

FIG. 4 (B) is a cross-sectional view of a prior art gate driver TFT;

FIG. 5 is a cross-sectional view of a gate-driven thin film transistor according to the present application;

fig. 6 is a cross-sectional view of a first mask region in a second mask embodiment of the present application;

FIG. 7 is a schematic diagram of a first structure of a second mask region according to a second embodiment of the mask of the present application;

fig. 8 is a schematic diagram of a second structure of a second mask region according to a second embodiment of the mask of the present application;

FIG. 9 is a first cross-sectional view of a second mask region according to a second embodiment of the mask of the present application;

fig. 10 is a schematic diagram of a third structure of a second mask region according to a second embodiment of the mask of the present application;

FIG. 11 is a second cross-sectional view of a second masked region according to a second embodiment of the mask of the present application;

FIG. 12 is a schematic flow chart illustrating a first method of fabricating a thin film transistor according to the present application;

FIG. 13 is a schematic flow chart illustrating a first method of fabricating a thin film transistor according to the present application;

fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present application.

The reference numbers illustrate:

reference numerals	Name(s)	Reference numerals	Name(s)
				1	Substrate	21	A first light-transmitting region
2	Channel exposure region	31	Source electrode exposure area
				32	Drain exposed region	32	Channel region
211	First through hole	212	Second through hole
				213	Connecting through hole	311	A first metal arm
312	Second metal arm	313	Third metal arm
				314	Connecting metal arm	100	Substrate
200	Grid electrode	300	Gate insulating layer
				400	Active layer	500	Source and drain electrodes
401	Channel region	600	Photoresist
				22	Second light-transmitting region	40	Array substrate
50	Liquid crystal layer	60	Color film substrate

The implementation, functional features and advantages of the object of the present application will be further explained with reference to the embodiments, and with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Example one

Referring to fig. 1 and 2, fig. 1 is a schematic structural view of a second mask region of a mask in a first embodiment of the mask, and fig. 2 is a cross-sectional view of the second mask region of the mask in the first embodiment of the mask. A first embodiment of the thin film transistor of the present application is proposed based on fig. 1 and fig. 2.

In the first embodiment, a substrate 1 of the mask is provided with a second mask region and a first mask region, the second mask region of the mask comprises the substrate 1, and the second mask region and the first mask region of the mask comprise a source exposure region 31, a drain exposure region 32 and a channel exposure region 2 which are arranged on the substrate;

the channel exposure region of the first mask region comprises a first light-transmitting region 21; the channel exposure region of the second mask region includes the first light transmission region 21 and the second light transmission region 22.

A semi-permeable membrane may be disposed in the first light-transmitting region 21, and a membrane having a higher light transmittance may be disposed in the second light-transmitting region 22, or a diaphragm may not be disposed therein.

The second mask area on the mask is used for manufacturing a thin film transistor arranged in the grid driving area, and the first mask area is used for manufacturing a thin film transistor in the operable area.

Referring to fig. 1, it should be understood that the Mask is a commonly used Mask structure for designing a thin film transistor by a 4Mask process. The light transmittance of the semi-permeable membrane in the first light-transmitting region 21 of the mask is usually between 30% and 50%. An opaque metal material, which may be a metal chromium electrode, may be disposed in the source exposure region 31 and the drain exposure region 32. Referring to fig. 3, the gate driving region is required to drive each sub-pixel in the display region on the array substrate, and therefore, many thin film transistors for driving the sub-pixels are generally disposed in the gate driving region; and the operable area is usually provided with only a few corresponding thin film transistors for the user to operate, so the corresponding structures for manufacturing the gate driving area and the thin film transistors in the operable area are different. Since the number of thin film transistors provided in the gate driving region is large, the ratio of the metal material in the gate driving region in the source exposure region 31 and the drain exposure region 32 is large. Under the condition of the same area, the light transmittance of the second mask area for manufacturing the thin film transistor in the gate driving area is far lower than that of the first mask area for manufacturing the thin film transistor in the operable area. The first mask area can be used for manufacturing a thin film transistor of an operable area on the array substrate, and the second mask area can be used for manufacturing a thin film transistor of a grid driving area. Due to the large difference of the light transmittance, the channel widths of the thin film transistors in the gate driving region and the operable region cannot be guaranteed to be within a reasonable range of 4-10 micrometers, and finally, the display picture of the display is abnormal. Referring to fig. 4 and fig. 6, fig. 4 (a) shows a tft structure of an operational area in the present application, and fig. 4 (B) shows a tft structure in a gate driving area in the prior art. The semiconductor device comprises a substrate 100, a gate 200, a gate insulating layer 300, an active layer 400, a channel region 401, a source and drain 500 and photoresist 600. For example, when the channel width of the thin film transistor in the gate driving region is too large, low-temperature picture variation is easy to occur; when the channel width of the thin film transistor in the gate driving region is too small, high temperature picture difference is easy to occur. When the channel width of the thin film transistor in the operable area is too large, image abnormalities such as insufficient charging, dim taste display color, easy color mixing and the like can occur; when the channel width of the thin film transistor in the operable region is too small, abnormalities such as picture crosstalk and picture flicker may occur.

It should be noted that, in a general mask manufacturing process, the substrate 1 may be set first, in order to avoid influence of the substrate 1 on the light transmittance of the mask, the substrate 1 may be a transparent substrate made of a glass material, then the source exposure region 31 and the drain exposure region 32 are set on the second mask region and the operable driving region on the substrate 1, and then the channel exposure region 2 is set with a semi-permeable membrane as the first light-transmitting region 21. And finally, arranging a second light-transmitting area 22 in the channel exposure area 3 of the second mask area. Of course, in this embodiment, the second light-transmitting region may be directly etched in the semi-transparent film of the first light-transmitting region 21. The light transmittance of the semi-permeable membrane of the first light-transmitting region 21 of the channel exposure region 2 is between 30 and 50%, and the light transmittance in the second light-transmitting region 22 is 100%.

It can be understood that, when the second light-transmitting region 22 is located in the channel exposure region 2, the light transmittance of the corresponding position of the second light-transmitting region 21 can be increased from 30-50% to 100%, and the light transmittance in the corresponding process of manufacturing the thin film transistor in the gate driving region is increased to a certain extent. Therefore, if part of or all of the thin film transistors in the gate driving area are manufactured by adopting the second mask area, the light transmittance of the whole structure of the gate driving area is improved. The thin film transistor in the operable area is manufactured by adopting the first mask area which does not comprise the second light transmission area, so that the light transmittance of the whole structure in the operable area is not changed, and the light transmittance difference between the grid driving area and the operable area can be reduced. Referring to fig. 4 and 5, the difference in channel size between the gate driving region and the operable region can be effectively reduced by disposing the first light-transmitting region and the second light-transmitting region in the channel exposure region in the second mask region on the mask. For example, the size of the channel region 401 of the tft in the operational area is 5 microns, the size of the channel region 401 of the tft in the gate driving area in the related art is 4.5 microns, and the size of the channel region 401 of the tft in the gate driving area can be increased to 4.9 microns by using the mask in this application.

In the first embodiment, a mask is provided, which includes a substrate, and a second mask region and a first mask region are disposed on the substrate, where the second mask region and the first mask region both include a source exposure region, a drain exposure region and a channel exposure region, and the channel exposure region of the first mask region includes a first light-transmitting region; and the channel exposure region of the second mask region comprises the first light transmission region and the second light transmission region. Set up first printing opacity district and second printing opacity district through the channel exposure area in the second mask zone at the mask version in this application, the second printing opacity district is located in the first printing opacity district, just the luminousness in second printing opacity district is greater than the luminousness in first printing opacity district to luminousness when promoting the preparation of gate drive district reduces the luminousness difference of gate drive district in the operatable area, avoids unable reasonable thin film transistor's in setting up gate drive district and the operatable area channel width.

Example two

Referring to fig. 7 and 8, fig. 7 is a first structural schematic diagram of a mask according to a second embodiment of the mask of the present application, and fig. 8 is a second structural schematic diagram of the mask according to the second embodiment of the mask of the present application. Based on the first embodiment of the mask, a second embodiment of the mask of the present application is provided.

In the second embodiment, the metal electrode 31 includes a first metal arm 311, a second metal arm 312, a third metal arm 313 and a connecting metal arm 314;

the second metal arm 312, the third metal arm 313 and the connecting metal arm 314 form a U-shaped groove, and the first metal arm 311 is located in the U-shaped groove;

the light-transmitting region 21 includes a first through hole 211 and a second through hole 212;

the projection of the first via 211 on the metal layer 30 is between the first metal arm 311 and the second metal arm 312, and the projection of the second via 212 on the metal layer 3 is between the first metal arm 311 and the third metal arm 313.

It should be understood that in the process of designing and manufacturing a thin film transistor by using a 4Mask process, a related flow operation needs to be performed by using a Mask. The size of the second light-transmitting area 22 should be set within a certain variation range, and if the second light-transmitting area 22 is set too large, the proportion of the first light-transmitting area 21 is relatively small, which may affect the fabrication of the mask and the fabrication of the thin film transistor; if the second light-transmitting area 22 is too small, the effect of improving the light transmittance of the whole mask is not obvious, and therefore, the ratio between the second light-transmitting area 22 and the first light-transmitting area 21 should be considered in the process of setting the second light-transmitting area 22. For example, if the area of the second transparent region 22 exceeds 1/3 of the total area of the channel exposure region, the related process of designing the thin film transistor by the 4Mask process will be affected, and even the process cannot be performed normally, the area ratio of the corresponding second transparent region 22 should be lower than 1/3 of the total area ratio of the channel exposure region. In the second embodiment, the second transparent region 22 may be divided into a number of through-hole structures, and the through-holes are located at different positions, so as to maintain the overall structure of the semi-permeable membrane 2.

The through hole is a hole-like structure obtained by etching through the first light-transmitting region 21 in the channel exposure region. The through holes may be strip-shaped holes, circular holes, square holes, etc., and are not specifically limited herein. Referring to fig. 7, in the second embodiment, a plurality of via structures may be disposed on the first light-transmitting region 21 in the channel exposure region, so that the occupation ratio of the second light-transmitting region 22 may be further improved. In fig. 7, in the case that the first through hole 211 can be disposed in the channel exposure region between the first metal arm 311 and the second metal arm 312, the second through hole 212 can also be disposed in the channel region 31 between the first metal arm 311 and the third metal arm 313, so that the light transmittance of the whole structure of the thin film transistor can be further improved.

Of course, in a specific setting process, a greater number of via structures may be provided, and each via may be provided between the first metal arm 311 and the second metal arm 312 or between the first metal arm 311 and the third metal arm 313. For example, through holes with different sizes are formed, wherein the width of the first through hole 211 is the same as the width of the second through hole 212, in this case, the first through hole 211 may be located on the semi-permeable membrane 2 at a position corresponding to the channel exposure region between the first metal arm 311 and the second metal arm 312, and the second through hole 212 and the third through hole may be located on the first light-transmitting region 21 at a position corresponding to the channel exposure region between the first metal arm 311 and the third metal arm 313 with a certain distance therebetween.

It can be understood that, in order to avoid the influence of the oversize via on the related flow of the 4Mask process design, the width of the first via 211 should be between 1/3 and 1/2 of the spacing width between the first metal arm 311 and the second metal arm 312; similarly, the width of the second via 212 is between 1/3 and 1/2 of the interval width between the first metal arm 311 and the third metal arm 313. The width of a single through hole should be between 0.5 and 2.5 um. When the width of a single via is greater than 1/2 of the width between adjacent metal arms, the overall structure of the semi-permeable membrane 2 is affected. And under the condition that the width of a single through hole is too small, the light transmittance of the whole structure of the thin film transistor is not obviously improved. In the second embodiment, the width of a single through hole is selected to be 1/3-1/2 of the interval width between adjacent metal arms, so that the light transmittance of the whole structure can be effectively increased, and the influence on the flow of 4Mask process design can be avoided.

In the second embodiment, the distance from the first via 211 to the first metal arm 311 and the second metal arm 312 is the same; the distance from the second via 212 to the first metal arm 311 and the third metal arm 313 is the same.

It should be understood that the through hole is located in the channel exposure region, but in the metal etching process of the source exposure region and the drain exposure region, in order to avoid the influence that the etched source exposure region and the etched drain exposure region may have on the through hole, the through hole may be set to have the same distance from the metal arms corresponding to the two sides of the channel exposure region. Referring to fig. 7, in fig. 7, the distance between the first through hole 211 and the first metal arm 311 is the same as the distance between the second metal arm 312, and the etched metal electrode 31 does not block the through hole at all.

Of course, the via may not be in the middle when the metal arm is etched, but the edge of the via should be at a distance from the metal arm.

In addition, in the second embodiment, the light-transmitting region 21 further includes a connection via 213, and the connection via 213 is disposed between the first metal arm 311 and the connection metal arm 314;

the connection through hole 213, the first through hole 211, and the second through hole 212 constitute a U-shaped through hole.

Referring to fig. 8, the light-transmitting region 21 may be provided in a U-shaped via structure in fig. 8, further increasing the occupation ratio of the light-transmitting region 21. Since the second metal arm 312, the third metal arm 313 and the connecting metal arm 314 of the tft form a U-shaped structure therebetween, in a specific setting process, referring to fig. 9, when the second light-transmitting region 22 is set to be a corresponding U-shaped through hole structure, the light transmittance of a corresponding single tft structure is increased most. Referring to fig. 10 and 11, when the light-transmitting regions in all the tfts in the gate driving region are U-shaped, the light transmittance of the whole structure of the gate driving region is improved most effectively.

In this embodiment, the second light-transmitting region 22 is set to be U-shaped, and the width of the through hole in the light-transmitting region of the U-shaped structure is limited, so that the light transmittance of the gate driving region of the mask can be further improved without affecting the process flow of the thin film transistor manufacturing process, and the difference between the light transmittance of the gate driving region and the light transmittance of the operable region is minimized.

EXAMPLE III

In a third embodiment, the method for manufacturing the array substrate by using the mask specifically includes:

step S10: and coating a photoresist layer on the substrate provided with the active layer.

It should be understood that, in the manufacturing process of the array substrate, it is required to select a substrate, then respectively dispose a gate structure on the substrate, dispose a gate insulating layer to protect the gate from being insulated, and then dispose an active layer on the gate insulating layer. The fabrication of the substrate with active layer can refer to the prior art, and is not described herein. Wherein the photoresist layer is used for photoetching a channel structure. And the active layer, the source and drain metal and the like are etched by utilizing the characteristics of the photoresist through the pattern incident light source on the mask plate, so that the corresponding channel is obtained.

Step S20: and obtaining a mask plate, wherein the channel exposure area of the second mask area in the mask plate comprises a first light transmission area and a second light transmission area, and the channel exposure area of the first mask area comprises a first light transmission area.

It should be understood that in the process of manufacturing the thin film transistor by the 4Mask process, the active layer or the metal needs to be etched by photolithography using a Mask. The mask plate is provided with a first light transmission area and a second light transmission area in a channel exposure area of the second mask area, and only the first light transmission area is arranged in the channel exposure area of the first mask area. This first printing opacity district can be the pellicle, and second printing opacity district can be the through-hole of setting on the pellicle.

Step S30: and etching the active layer through the mask plate so as to form respective corresponding channels on the gate drive region and the operable region on the active layer.

After the mask structure is obtained, the mask can be directly used for covering the photoresist layer, and then the structures of the gate driving area and the operable area on the array substrate are etched through the structure on the mask to form corresponding channels.

Step S40: and processing the upper part of the etched active layer to form the array substrate.

It should be understood that after the trench etching is completed, a process, such as cleaning the photoresist, disposing an oxidation-resistant protective layer, etc., needs to be performed on the active layer to form a complete array substrate structure.

In the third embodiment, a method for manufacturing an array substrate is provided, in which a first light-transmitting region and a second light-transmitting region are arranged in a channel exposure region of a second mask region, and a mask in which only the first light-transmitting region is arranged in the channel exposure region of the first mask region is used for performing channel etching, so that light transmittance during manufacturing of a gate driving region is improved, light transmittance difference of the gate driving region in an operable region is reduced, and unreasonable setting of channel widths of thin film transistors in the gate driving region and the operable region is avoided.

Example four

Referring to fig. 13, fig. 13 is a schematic flowchart illustrating a second embodiment of the array substrate manufacturing method of the present application.

Based on the third embodiment, in the fourth embodiment, in the process of manufacturing the array substrate by using the mask, the step S20 includes:

step S201: and obtaining the substrate provided with the second mask area and the first mask area.

Step S202: and arranging the first light-transmitting area in the channel exposure area in the second mask area and the first mask area.

Step S203: and arranging the second light-transmitting area in the channel exposure area of the second mask area.

It should be understood that, in the process of manufacturing the mask, a substrate needs to be manufactured, and the substrate may be a transparent substrate, such as a glass substrate, or may be a transparent substrate made of other materials, which is not limited in this respect. The metal material can be formed by chromium rack plating or sputtering.

In specific implementation, after a transparent substrate is obtained, structures corresponding to a source exposure region and a drain exposure region are arranged on the channel exposure regions of the second mask region and the first mask region, then first light transmission regions are arranged in the corresponding channel exposure regions, and finally, second light transmission regions are arranged in the channel exposure regions of the second mask region, for example, etching is carried out through etching of a semi-permeable membrane in the second mask region, so that second light transmission regions are obtained.

It can be understood that, when the second light-transmitting region is located in the channel exposure region, the light transmittance of the corresponding position of the second light-transmitting region can be increased from 30 to 50% to 100%, and the light transmittance of the corresponding second mask region is increased to a certain extent. Therefore, if part of or all of the thin film transistors in the gate driving region are manufactured by using the mask, the size of the channel region in the gate driving region can be increased to a certain extent. The thin film transistor in the operable area is not manufactured by adopting a channel exposure area structure comprising a second light transmission area, so that the light transmittance of a mask for manufacturing the thin film transistor in the operable area is not changed, and the difference of the thin film transistor channel area between the gate driving area and the operable area can be reduced.

In a fourth embodiment, the step S203 specifically includes:

step S2031: and acquiring the size information of the channel exposure area of the second mask area.

It should be noted that, in the fourth embodiment, the size information of the channel exposure region refers to the channel width information of the channel exposure region in the second masked region. The size information of the exposure area can be directly determined according to the size of the etched metal material, and certainly, the size information between adjacent metal arms can also be determined according to the size of the metal electrode.

Step S2032: and determining the size information and the shape information of the second light transmission region according to the size information of the channel exposure region.

In the fourth embodiment, the size of the second light-transmitting region should be set within a certain variation range, and the second light-transmitting region is too large, so that the structure of the first light-transmitting region is relatively small, which may affect the fabrication of the mask and the fabrication of the thin film transistor; if the setting of second printing opacity district is too little, the effect of the luminousness promotion to whole mask is not obvious, consequently, in the setting process of second printing opacity district, should consider the occupation ratio of printing opacity district on whole pellicle. For example, if the area of the second transparent region exceeds 1/3 of the entire channel exposure region, the related process of designing the thin film transistor by the 4Mask process is affected, and even the normal implementation is impossible, the area ratio of the corresponding transparent region should be lower than 1/3 of the entire channel exposure region. In the second embodiment, the second light-transmitting region may be divided into a number of through-hole structures, and the through-holes are located at different positions, so as to maintain the overall structure of the semi-permeable membrane.

Wherein the size information refers to width information of the second light-transmitting area, and the shape information refers to a shape of an entire structure of the second light-transmitting area. A number of via structures may be in the second light transmissive region. The width of the via should be between 1/3 and 1/2 of the width of a single channel region. Therefore, after the size information of the channel exposure region is determined, the specific size information and the corresponding shape information of the second light-transmitting region through hole can be determined according to the width of the channel exposure region. For example, the channel exposure region is a U-shaped groove region formed by the second metal arm, the third metal arm and the connecting metal arm, and at this time, when the second light-transmitting region is in a corresponding U-shaped structure, the area of the through hole can be increased to the maximum, so that when the channel exposure region is in a U-shaped structure, the corresponding light-transmitting region can be also in a U-shaped structure.

Step S2033: and setting the second light-transmitting area in the second mask area according to the size information and the shape information of the light-transmitting area.

It is to be understood that, after determining the size information and the shape information of the second light-transmitting region, the corresponding second light-transmitting region and the first light-transmitting region may be disposed within the channel exposure region according to the size information and the shape information of the second light-transmitting region.

In this embodiment, by defining the shape information and the size information of the second light-transmitting area, the light transmittance of the gate driving structure for manufacturing the gate driving area can be further improved without affecting the process flow of the thin film transistor manufacturing process, so that the light transmittance difference between the second mask area and the first mask area for manufacturing the thin film transistor is minimized.

EXAMPLE five

Referring to fig. 3, in this embodiment, an array substrate is provided, where the array substrate is manufactured by using the mask described above, the array substrate is provided with a display area and a non-display area, the non-display area is provided with a first switch unit, and the display area is provided with a second switch unit; the non-display area corresponds to the first mask area, and the display area corresponds to the second mask area; the source, the drain and the channel of the switch unit are respectively in one-to-one correspondence with the source exposure region, the drain exposure region and the channel exposure region, and the channel width of the first switch unit is equal to the channel width of the second switch unit.

Example six

Referring to fig. 14, the present application further provides a display panel, where the display panel includes a color filter substrate 60, a liquid crystal layer 50, and the array substrate 40, and the liquid crystal layer 50 is located between the color filter substrate 60 and the array substrate 40.

Since the display adopts all technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and are not described in detail herein.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that all directional indicators (such as up, down, left, right, front, back \8230;) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

Furthermore, the descriptions in this application that refer to "first," "second," etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not be within the protection scope of the present application.

Claims

1. The utility model provides a mask version, is applied to preparation array substrate, mask version includes the basement, be equipped with first mask zone and second mask zone on the basement, first mask zone is located second mask zone is peripheral, its characterized in that:

the first mask area is used for manufacturing a first switch unit of the array substrate, the second mask area is used for manufacturing a second switch unit of the array substrate, and the first mask area and the second mask area respectively comprise a source electrode exposure area, a drain electrode exposure area and a channel exposure area; the channel exposure region of the first mask region comprises a first light transmission region, and the channel exposure region of the second mask region comprises a first light transmission region and a second light transmission region; the second light-transmitting area is arranged in the first light-transmitting area of the channel exposure area in the second mask area, and the light transmittance of the second light-transmitting area is greater than that of the first light-transmitting area.

2. The reticle of claim 1, wherein the source exposure region comprises a first metal arm; the drain exposure region includes: a second metal arm, a third metal arm and a connecting metal arm;

the first via is located between the first metal arm and the second metal arm, and the second via is located between the first metal arm and the third metal arm.

3. The reticle of claim 2, wherein a distance between the first via to the first metal arm and the second metal arm is the same; the distance from the second through hole to the first metal arm and the third metal arm is the same.

4. The reticle of claim 3, wherein the light-transmissive region further comprises a connecting via disposed between the first metal arm and the connecting metal arm;

5. The reticle of claim 4, wherein the width of the first via is between 1/3 and 1/2 of the width of the space between the first metal arm and the second metal arm;

the width of the second through hole is between 1/3 and 1/2 of the interval width of the first metal arm and the third metal arm.

6. An array substrate manufactured by using the mask plate of any one of claims 1 to 5, wherein the array substrate is provided with a display area and a non-display area, the non-display area is provided with a first switch unit, and the display area is provided with a second switch unit; the non-display area corresponds to the first mask area, and the display area corresponds to the second mask area; the source electrode, the drain electrode and the channel of the switch unit are respectively in one-to-one correspondence with the source electrode exposure area, the drain electrode exposure area and the channel exposure area, and the channel width of the first switch unit is equal to the channel width of the second switch unit.

7. A display panel, comprising a color film substrate, a liquid crystal layer and the array substrate of claim 6, wherein the liquid crystal layer is located between the color film substrate and the array substrate.