CN218122174U - Pulse back bias test system - Google Patents
Pulse back bias test system Download PDFInfo
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- CN218122174U CN218122174U CN202221937905.8U CN202221937905U CN218122174U CN 218122174 U CN218122174 U CN 218122174U CN 202221937905 U CN202221937905 U CN 202221937905U CN 218122174 U CN218122174 U CN 218122174U
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Abstract
The utility model discloses a pulse anti-test system that partially inclines, including the input power V +, a plurality of quilt survey devices that are used for providing electric power, be used for providing test voltage for the quilt survey device pulse power supply, be used for providing test environment and being used for gathering the ageing cabinet of each item test data of quilt survey device and be used for fixed ageing board of quilt survey device, every quilt survey device is electric connection respectively and be fixed in the erection site on the ageing board, in the ageing board is fixed in the ageing room in the ageing cabinet, pulse power supply's output and ageing board's test signal input electric connection, the output of input power V + respectively with pulse power supply's input and ageing board's power input electric connection. The utility model overcomes the traditional chip aging testing system who exists does not set up the pulse test system's of chip problem among the prior art. The utility model has the advantages of following beneficial effect simple structure, detect accuracy and convenient operation.
Description
Technical Field
The utility model relates to a chip test system field, more specifically say, relate to a pulse reverse bias test system.
Background
With the development of science and technology, the life of people is more and more free from a semiconductor integrated circuit, the core of the integrated circuit is a semiconductor chip, and in order to enable the chip to run more stably, parameters of the semiconductor chip are analyzed, and the semiconductor chip is processed under the conditions of constant voltage and high temperature in the past; in order to make the chip capable of operating normally under more complex circuits, more and more semiconductor chips are now required to operate normally under pulse voltage and high temperature.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an overcome the traditional chip aging testing system who exists among the prior art and do not set up the pulse test system's of chip problem, now provide and have a pulse reverse bias test system that can carry out the pulse test to the chip.
The utility model discloses a pulse anti-test system that partially inclines, including the input power V +, a plurality of quilt survey devices that are used for providing electric power, be used for providing test voltage for the quilt survey device pulse power supply, be used for providing test environment and being used for gathering the ageing cabinet of each item test data of quilt survey device and be used for fixed ageing board of quilt survey device, every quilt survey device is electric connection respectively and is fixed in the installation position on the ageing board, in the ageing board is fixed in the ageing room in the ageing cabinet, pulse power supply's output and ageing board's test signal input electric connection, the output of input power V + respectively with pulse power supply's input and the power input electric connection of ageing board.
Preferably, a relay K1 for controlling the pulse power supply is arranged between the input power supply V + and the pulse power supply, one end of the relay K1 is electrically connected with the output end of the pulse power supply, and the other end of the relay K1 is electrically connected with the input end of the pulse power supply.
Preferably, the pulse power supply comprises a pulse signal generator for generating pulse signals, the pulse signal generator is integrally fixed on the inner wall of the aging room, a pulse signal modulator PWM for adjusting the width of the pulse signals is arranged beside the pulse signal generator, the power input end of the pulse signal generator is electrically connected with one end of the relay K1, the signal output end of the pulse signal modulator PWM is electrically connected with the signal input end of the pulse signal generator, and the signal output end of the pulse signal generator is electrically connected with the signal input end of each tested device respectively.
Preferably, a fuse FU for protecting the device under test is respectively arranged between each device under test and the pulse signal generator, one end of the fuse FU is electrically connected with one end of the device under test, the other end of the fuse FU is electrically connected with the signal output end of the pulse signal generator, and the other end of the device under test is grounded.
Before working, the device to be tested is fixed in the installation position of the aging board, and then the aging board provided with the device to be tested is fixed in the aging room of the aging cabinet.
During operation, firstly to starting input power V + and relay K1 on the control platform of ageing cabinet, pulse signal generator begins to produce high frequency pulse signal this moment, then open the heater in the ageing room and set up required test temperature, the required extreme environment of beginning simulation test, the chip under test passes through high frequency pulse signal under high temperature ceaselessly at this moment, integrated each item data collection ware such as voltage collector, current collector, circuit temperature collector etc. can carry out data acquisition to each chip under test respectively in the ageing room in the test process until the test finishes.
When the tested chip is abnormal in the test process, the fuse can be automatically fused to cut off the circuit, so that the tested chip is protected.
The utility model discloses following beneficial effect has: simple structure, accurate detection and convenient operation.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
A device under test 1, a pulse signal generator 2.
Detailed Description
The technical solution of the present invention is further specifically described below by way of examples and with reference to the accompanying drawings.
Example (b): the pulse back bias test system of the present embodiment is further described with reference to fig. 1, which includes an input power source V + for providing power, a plurality of devices under test 1, a pulse power source for providing test voltage to the devices under test 1, an aging cabinet for providing test environment to the devices under test 1 and for collecting various test data of the devices under test 1, and an aging board for fixing the devices under test 1, wherein each device under test 1 is electrically connected and fixed in a mounting position on the aging board, the aging board is fixed in an aging room in the aging cabinet, an output terminal of the pulse power source is electrically connected to a test signal input terminal of the aging board, and an output terminal of the input power source V + is electrically connected to an input terminal of the pulse power source and a power input terminal of the aging board.
The pulse power supply control circuit is characterized in that a relay K1 used for controlling the pulse power supply is arranged between the input power supply V + and the pulse power supply, one end of the relay K1 is electrically connected with the output end of the pulse power supply, and the other end of the relay K1 is electrically connected with the input end of the pulse power supply.
Pulse power supply including the pulse signal generator 2 that is used for producing pulse signal, pulse signal generator 2 integrated being fixed in ageing house inner wall on, pulse signal generator 2 other pulse signal modulation ware PWM that is used for adjusting pulse signal's width, pulse signal generator 2's power input end and relay K1's one end electric connection, pulse signal modulation ware PWM's signal output part and pulse signal generator 2's signal input part electric connection, pulse signal generator 2's signal output part respectively with every signal input part electric connection that is surveyed device 1.
A fuse FU for protecting the device under test 1 is respectively arranged between each device under test 1 and the pulse signal generator 2, one end of the fuse FU is electrically connected with one end of the device under test 1, the other end of the fuse FU is electrically connected with the signal output end of the pulse signal generator 2, and the other end of the device under test 1 is grounded.
The above description is only for the specific embodiment of the present invention, but the structural features of the present invention are not limited thereto, and any person skilled in the art can make changes or modifications within the scope of the present invention.
Claims (4)
1. A pulse reverse bias test system comprises an input power supply V + for providing power, a plurality of tested devices (1), a pulse power supply for providing test voltage for the tested devices (1), an aging cabinet for providing test environment for the tested devices (1) and acquiring various test data of the tested devices (1), and an aging board for fixing the tested devices (1), and is characterized in that each tested device (1) is electrically connected and fixed in a mounting position on the aging board, the aging board is fixed in an aging room in the aging cabinet, the output end of the pulse power supply is electrically connected with the test signal input end of the aging board, and the output end of the input power supply V + is electrically connected with the input end of the pulse power supply and the power supply input end of the aging board.
2. The pulse reverse bias test system according to claim 1, wherein a relay K1 for controlling the pulse power supply is arranged between the input power supply V + and the pulse power supply, one end of the relay K1 is electrically connected with the output end of the pulse power supply, and the other end of the relay K1 is electrically connected with the input end of the pulse power supply.
3. The pulse back-bias test system according to claim 2, wherein the pulse power supply comprises a pulse signal generator (2) for generating a pulse signal, the pulse signal generator (2) is integrally fixed on the inner wall of the aging room, a pulse signal modulator PWM for adjusting the width of the pulse signal is arranged beside the pulse signal generator (2), the power input end of the pulse signal generator (2) is electrically connected with one end of the relay K1, the signal output end of the pulse signal modulator PWM is electrically connected with the signal input end of the pulse signal generator (2), and the signal output end of the pulse signal generator (2) is electrically connected with the signal input end of each device under test (1).
4. A pulse reverse bias test system according to claim 3, wherein a fuse FU for protecting the device under test (1) is respectively disposed between each device under test (1) and the pulse signal generator (2), one end of the fuse FU is electrically connected to one end of the device under test (1), the other end of the fuse FU is electrically connected to the signal output end of the pulse signal generator (2), and the other end of the device under test (1) is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221937905.8U CN218122174U (en) | 2022-07-26 | 2022-07-26 | Pulse back bias test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221937905.8U CN218122174U (en) | 2022-07-26 | 2022-07-26 | Pulse back bias test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218122174U true CN218122174U (en) | 2022-12-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221937905.8U Active CN218122174U (en) | 2022-07-26 | 2022-07-26 | Pulse back bias test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218122174U (en) |
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2022
- 2022-07-26 CN CN202221937905.8U patent/CN218122174U/en active Active
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| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 311107 No.16, No.2 Yongtai Road, Renhe Street, Yuhang District, Hangzhou, Zhejiang Patentee after: Hangzhou Gaoyu Electronic Technology Co.,Ltd. Address before: 311107 building 16, No. 2, Yongtai Road, Renhe street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: HANGZHOU GAOYU ELECTRONIC TECHNOLOGY CO.,LTD. |
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| CP03 | Change of name, title or address |