CN113092987A - Current chip step test system - Google Patents
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- CN113092987A CN113092987A CN202110225117.XA CN202110225117A CN113092987A CN 113092987 A CN113092987 A CN 113092987A CN 202110225117 A CN202110225117 A CN 202110225117A CN 113092987 A CN113092987 A CN 113092987A
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
Abstract
The invention discloses a current chip step test system which comprises a main control system, a first isolation circuit, a second isolation circuit, a first large-current switch, a second large-current switch, a signal amplification module and a power input interface, wherein the main control system comprises a main control circuit, a first voltage circuit, a second voltage circuit, a first voltage circuit, a second voltage circuit; the master control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the first isolation circuit is connected with a first high-current switch, and the first high-current switch can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch, and the second high-current switch can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load. The current chip step test system provided by the invention can reduce the price of test equipment and can carry out multiple tests on the current chip.
Description
Technical Field
The invention belongs to the technical field of chip testing, relates to a testing system, and particularly relates to a current chip step testing system.
Background
Along with the development of artificial intelligence and automation, more and more sensors are needed, the states of equipment or specific current values need to be monitored or sensed in the fields of high-power inverters, elevator door machines, charging piles, electric vehicles, automobile EPS, motor monitoring, intelligent electric meters and the like, and the current on the occasions is very large, high in power and difficult to measure, and the current is hundreds of amperes at most.
The traditional mode is to use a small-resistance resistor plus a linear hall for measurement, but the temperature characteristic is large, the cost is high, and the test current is limited, so that a current hall or a magnetic resistance sensing chip is developed in recent years, and the problems are perfectly solved.
The current sensor chip is divided into a signal input end and a signal output end, and a plurality of key parameters need to be tested: signal output rise time, signal output transmission delay and signal response time, wherein the parameters are currently no schemes proposed by test equipment at home and abroad: the signal generator and the high-frequency high-power amplifier form step signals, the current clamp is used as a trigger signal for testing, the rise time of a source end signal can reach 1us, and the testing problem is solved.
In view of the above, there is an urgent need to design a new large current step test method to overcome the above defects and to meet the test requirements to the maximum extent.
Disclosure of Invention
The invention provides a current chip step test system which can reduce the price of test equipment and simultaneously can carry out multiple tests on a current chip.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a current chip step test system, the test system comprising: the device comprises a main control system, a first isolation circuit, a second isolation circuit, a first large-current switch, a second large-current switch, a virtual load, a test load, a signal amplification module and a power input interface;
the master control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit;
the first isolation circuit is respectively connected with the power input interface and the first high-current switch; the second isolation circuit is respectively connected with the power input interface and the second high-current switch;
the virtual load is respectively connected with the test load, the power input interface and the first high-current switch; the test load is respectively connected with the power input interface and the second high-current switch; the signal amplification module is respectively connected with a test load and a power input interface;
the power input interface provides required electric energy for the main control system, the first isolation circuit, the second isolation circuit, the first high-current switch, the second high-current switch, the virtual load, the test load and the signal amplification module;
the master control system comprises a master control CPU, a crystal oscillator circuit, a reset circuit, a signal button, an AVCC filter circuit and a burning interface; the master control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the indicator lamp, the signal button, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the master control CPU; the AVCC filter circuit is respectively connected with the first power supply and the master control CPU and provides an analog power supply for the master control CPU;
the indicating lamp is respectively connected with the main control CPU and the first power supply and indicates the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as test trigger;
the reset circuit is respectively connected with the first power supply and the master control CPU and controls the master control CPU to reset; the burning interface is respectively connected with an external burner and a master control CPU for a master control burning program to use;
the first isolation circuit and the second isolation circuit comprise isolation chips and buffer circuits; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with a master control system signal;
the virtual load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as a load the same as the test load and is used for switching current;
the test load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal;
the signal amplification module comprises an operational amplifier chip, a matching resistor, a positive signal matching circuit and a negative signal matching circuit; the operational amplification chip is respectively connected with a positive signal matching circuit, a negative signal matching circuit, a first power supply and an external oscilloscope, the positive signal matching circuit acquires positive signals, and the negative signal matching circuit acquires negative signals;
the power input interface comprises a first power input interface, a second power input interface and a high-current constant current source; the second power input interface is connected during an isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be detected, the reset circuit, the burning interface, the master control CPU, the signal button and the signal indicator lamp.
According to another aspect of the invention, the following technical scheme is adopted: a current chip step test system, the test system comprising: the main control system comprises a main control system, a first isolation circuit, a second isolation circuit, a first large-current switch, a second large-current switch, a signal amplification module and a power input interface;
the master control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the power input interface is respectively connected with the first isolating circuit, the second isolating circuit, the first heavy-current switch, the second heavy-current switch and the signal amplification module, and can also be connected with a virtual load and a test load;
the first isolation circuit is connected with a first high-current switch, and the first high-current switch can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch, and the second high-current switch can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load.
As an embodiment of the present invention, the master control system includes a master control CPU, a crystal oscillator circuit, a reset circuit, an AVCC filter circuit, and a burning interface; the master control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the master control CPU; the AVCC filter circuit is respectively connected with the first power supply and the master control CPU and provides an analog power supply for the master control CPU;
the reset circuit is respectively connected with the first power supply and the master control CPU and controls the master control CPU to reset; the burning interface is respectively connected with an external burner and a master control CPU for the use of a master control burning program.
As an embodiment of the present invention, the master control system further includes an indicator light and a signal button; the indicating lamp is respectively connected with the main control CPU and the first power supply and indicates the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as test trigger.
As an embodiment of the present invention, each of the first isolation circuit and the second isolation circuit includes an isolation chip and a buffer circuit; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with signals of the master control system.
As an embodiment of the present invention, the virtual load includes a switch tube, a trigger chip, and a chip to be tested, the switch tube is respectively connected to a switch signal and the test chip, the test chip is connected to the trigger chip, the trigger chip is connected to an external heavy current constant current source, and the virtual load is only used as a load the same as the test load for switching current.
As an embodiment of the present invention, the test load includes a switch tube, a trigger chip, and a chip to be tested, the switch tube is respectively connected to a switch signal and the test chip, the test chip is connected to the trigger chip and a first power supply, the trigger chip is respectively connected to an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal.
As an embodiment of the present invention, the signal amplification module includes an operational amplifier chip, a matching resistor, a positive signal matching circuit, and a negative signal matching circuit; the operational amplification chip is respectively connected with the positive signal matching circuit, the negative signal matching circuit, the first power supply and the external oscilloscope, the positive signal matching circuit collects positive signals, and the negative signal matching circuit collects negative signals.
As an embodiment of the present invention, the power input interface includes a first power input interface, a second power input interface, and a large current and constant current source; the second power input interface is connected during an isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be detected, the reset circuit, the burning interface, the master control CPU, the signal button and the signal indicator lamp.
The invention has the beneficial effects that: the current chip step test system provided by the invention can reduce the price of test equipment and can carry out multiple tests on the current chip.
Drawings
Fig. 1 is a schematic diagram illustrating a current chip step test system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a configuration of a main control system according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating an isolation circuit according to an embodiment of the invention.
Fig. 4 is a schematic diagram illustrating a composition of a dummy load according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a test load according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating a signal amplification module according to an embodiment of the invention.
Fig. 7 is a schematic diagram illustrating a power input interface according to an embodiment of the invention.
FIG. 8 is a flowchart illustrating a testing method of a test system according to an embodiment of the present invention.
FIG. 9 is a waveform diagram of a test system according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The term "connected" in the specification includes both direct connection and indirect connection.
The invention discloses a current chip step test system, and fig. 1 is a schematic composition diagram of the current chip step test system in one embodiment of the invention; referring to fig. 1, the test system includes: the main control system comprises a main control system 1, a first isolation circuit 2, a second isolation circuit 3, a first large-current switch 4, a second large-current switch 5, a signal amplification module 6 and a power input interface 7. In an embodiment, the test system may further comprise a virtual load 8; in another embodiment, the test system may further comprise a test load 9.
The main control system 1 is respectively connected with the power input interface 7, the first isolation circuit 2 and the second isolation circuit 3; the power input interface 7 is respectively connected with the first isolation circuit 2, the second isolation circuit 3, the first high-current switch 4, the second high-current switch 5 and the signal amplification module 6, and the power input interface 7 can also be connected with a virtual load 8 and a test load 9.
The first isolation circuit 2 is connected with a first high-current switch 4, and the first high-current switch 4 can be connected with a virtual load 8; the second isolation circuit 3 is connected with a second high-current switch 5, and the second high-current switch 5 can be connected with a test load 9; the virtual load 8 can be connected with a test load 9; the signal amplification module 6 can be connected with a test load 9.
FIG. 2 is a schematic diagram of a host system according to an embodiment of the present invention; referring to fig. 2, in an embodiment of the present invention, the main control system 1 includes a main control CPU 101, a crystal oscillator circuit 102, a reset circuit 103, an AVCC filter circuit 104, and a burning interface 105; the main control CPU 101 is respectively connected with a crystal oscillator circuit 102, a reset circuit 103, an AVCC filter circuit 104 and a burning interface 105. The crystal oscillator circuit 102 provides a system clock for the master control CPU 101; the AVCC filter circuit 104 is connected to a first power supply (which may be a 5V power supply) and the main control CPU 101, respectively, to provide an analog power supply for the main control CPU 101. The reset circuit 103 is respectively connected with the first power supply and the main control CPU 101 and controls the main control CPU 101 to reset; the burning interface 105 is respectively connected with an external burner and the master control CPU 101 for the use of a master control burning program.
In an embodiment of the present invention, the main control system 1 further includes an indicator light 106, a signal button 107; the indicator lamp 106 is respectively connected with the main control CPU 101 and the first power supply and indicates the system state and the first power supply state; the signal button 107 is respectively connected with the first power supply and the main control CPU 101 and is used as test trigger.
FIG. 3 is a schematic diagram of an isolation circuit according to an embodiment of the present invention; referring to fig. 3, in an embodiment of the present invention, the first isolation circuit 2 and the second isolation circuit 3 both include an isolation chip 201 and a buffer circuit 202; the isolation chip 201 is respectively connected with a buffer circuit 202 and corresponding high-current switches (a first high-current switch 4 and a second high-current switch 5), and the buffer circuit 202 is connected with signals of a main control system.
FIG. 4 is a schematic diagram illustrating the components of a dummy load according to an embodiment of the present invention; referring to fig. 4, in an embodiment of the present invention, the dummy load 8 includes a first switch tube 801, a first trigger chip 802, and a first chip to be tested 803, the first switch tube 801 is respectively connected to a switch signal and the first chip to be tested 803, the first chip to be tested 803 is connected to the first trigger chip 802, the first trigger chip 802 is connected to an external large-current constant current source, and the dummy load 8 is only used as a load the same as the test load 9 for switching current.
FIG. 5 is a schematic diagram illustrating the components of a test load according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the present invention, the test load 9 includes a second switch tube 901, a second trigger chip 902, and a second chip 903 to be tested, where the second switch tube 901 is connected to a switch signal and the second test chip 903, the test chip 903 is connected to the second trigger chip 902 and a first power supply, the second trigger chip 902 is connected to an external large-current constant current source and the first power supply, the second trigger chip 902 generates a trigger signal, and the second test chip 903 generates a test signal.
FIG. 6 is a schematic diagram illustrating a signal amplification module according to an embodiment of the present invention; referring to fig. 6, in an embodiment of the present invention, the signal amplifying module 6 includes an operational amplifier chip 601, a matching resistor 602, a positive signal matching circuit 603, and a negative signal matching circuit 604; the operational amplifier chip 601 is respectively connected with the positive signal matching circuit 603, the negative signal matching circuit 604, the first power supply and the external oscilloscope 10, wherein the positive signal matching circuit 603 acquires positive signals, and the negative signal matching circuit 604 acquires negative signals.
FIG. 7 is a schematic diagram of a power input interface according to an embodiment of the invention; referring to fig. 7, in an embodiment of the present invention, the power input interface 7 includes a 12V power input interface, a ± 5V power input interface, and a large-current constant current source. The 12V power input interface is connected in an isolation period; the +/-5V power interface is respectively connected with the operational amplifier, the trigger sensor, a chip to be detected (such as a sensor chip), the reset circuit, the burning interface, the master control CPU, the signal button and the signal indicator lamp.
FIG. 8 is a flowchart of a method for testing a test system according to an embodiment of the present invention; referring to fig. 8, in an embodiment of the present invention, a method for testing a current chip step test system includes:
firstly, pressing a signal button once, sending a virtual load switch signal after a main control system receives the button signal, and electrifying a virtual load through a current switch;
and then delaying for a period of time to wait for the current to be stable (the step rise of the common large current source is slow), and after the current is stable, the main control system performs current switching: the test load is electrified, and the virtual load current is cut off, so that a rapid step current can be generated on the test load; due to the existence of the virtual load, the current on the test load can be unlimited by the large-current constant current source.
The invention discloses a step performance test of a current chip by using a common device and common equipment, which comprises the following steps: the chip signal output rise time (the time when the signal rises from 10% output to 90% output), the signal output transmission delay (the time delay when the sensing signal rises to 20% and the current chip output signal rises to 20%), and the chip output response time (the time delay when the sensing signal rises to 80% and the current chip output signal rises to 80%).
In a use scene of the invention, the tested signal speed is very fast, ns level, the injection current is very large (the loop resistance is very small), the parasitic capacitance of the loop is easy to be coupled, and the parasitic inductance is easy to generate induced electromotive force. Through version change and ingenious layout, the invention effectively avoids the problems. The main control system in the invention is controlled by signal switching, and the isolation optocoupler isolates a large current signal to be detected from the main control system, thereby avoiding the generation of board-level system interference and coupling, because the parasitic parameters of MOS are very large. The invention selects the high-power surface mounted MOS and matches with the peripheral resistor, thereby eliminating the influence generated by MOS parasitic parameters. In an embodiment of the present invention, a workflow of a test system includes: powering on the system through an external direct current power supply; powering up a common large-current direct-current source; the oscilloscope performs corresponding setting; pressing a trigger switch; the master control system starts to operate; the master control system switches the virtual load and the signal to be tested; and measuring the required waveform by an oscilloscope, and recording the required waveform (as shown in figure 9).
The system has no special requirements on a high-power direct-current source, and has no special requirements on an oscilloscope. Because the test injection current is very large, the main control system processes the large current signal skillfully, and the danger is avoided.
In summary, the current chip step test system provided by the invention can reduce the price of test equipment and simultaneously perform multiple tests on the current chip. In a use scene of the invention, the master control system is used for signal control, the optical coupler is used for master control system and isolation of a signal to be tested, the MOS tube is used as a heavy current switch, the trigger signal sensor uses a common quick response sensor, the large direct current source uses a common direct current source and then an oscilloscope to test corresponding parameters, the embarrassment that no equipment is available on a current sensor chip (even if the cost is high) is solved, and meanwhile, the invention provides safety guarantee for a high-power inverter, an elevator door motor, a charging pile, an electric automobile, an automobile EPS, motor monitoring and an intelligent electric meter.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, it may be implemented using Application Specific Integrated Circuits (ASICs), general purpose computers, or any other similar hardware devices. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. As such, the software programs (including associated data structures) of the present application can be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented using hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (9)
1. A current chip step test system, the test system comprising: the device comprises a main control system, a first isolation circuit, a second isolation circuit, a first large-current switch, a second large-current switch, a virtual load, a test load, a signal amplification module and a power input interface;
the master control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit;
the first isolation circuit is respectively connected with the power input interface and the first high-current switch; the second isolation circuit is respectively connected with the power input interface and the second high-current switch;
the virtual load is respectively connected with the test load, the power input interface and the first high-current switch; the test load is respectively connected with the power input interface and the second high-current switch; the signal amplification module is respectively connected with a test load and a power input interface;
the power input interface provides required electric energy for the main control system, the first isolation circuit, the second isolation circuit, the first high-current switch, the second high-current switch, the virtual load, the test load and the signal amplification module;
the master control system comprises a master control CPU, a crystal oscillator circuit, a reset circuit, a signal button, an AVCC filter circuit and a burning interface; the master control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the indicator lamp, the signal button, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the master control CPU; the AVCC filter circuit is respectively connected with the first power supply and the master control CPU and provides an analog power supply for the master control CPU;
the indicating lamp is respectively connected with the main control CPU and the first power supply and indicates the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as test trigger;
the reset circuit is respectively connected with the first power supply and the master control CPU and controls the master control CPU to reset; the burning interface is respectively connected with an external burner and a master control CPU for a master control burning program to use;
the first isolation circuit and the second isolation circuit comprise isolation chips and buffer circuits; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with a master control system signal;
the virtual load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as a load the same as the test load and is used for switching current;
the test load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal;
the signal amplification module comprises an operational amplifier chip, a matching resistor, a positive signal matching circuit and a negative signal matching circuit; the operational amplification chip is respectively connected with a positive signal matching circuit, a negative signal matching circuit, a first power supply and an external oscilloscope, the positive signal matching circuit acquires positive signals, and the negative signal matching circuit acquires negative signals;
the power input interface comprises a first power input interface, a second power input interface and a high-current constant current source; the second power input interface is connected during an isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be detected, the reset circuit, the burning interface, the master control CPU, the signal button and the signal indicator lamp.
2. A current chip step test system, the test system comprising: the main control system comprises a main control system, a first isolation circuit, a second isolation circuit, a first large-current switch, a second large-current switch, a signal amplification module and a power input interface;
the main control system is used for controlling current switching, firstly, the main control system can send out a control signal to enable the virtual load to be electrified, and after a period of time delay (the rising speed of the direct current source current is relatively slow), the main control system controls current switching: the virtual load current is cut off immediately after the test load current is switched on in a short time, and the virtual load and the test load use the same direct current source, so that the switching process is fast, the direct current source cannot feel the load change, the problem that the rise time is not fast enough at the moment of starting the direct current source is solved, and the ordinary equipment can be used for generating fast current step. The main control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the power input interface is respectively connected with the first isolating circuit, the second isolating circuit, the first heavy-current switch, the second heavy-current switch and the signal amplification module, and can also be connected with a virtual load and a test load;
the first isolation circuit is connected with a first high-current switch, and the first high-current switch can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch, and the second high-current switch can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load.
3. The current chip step test system of claim 2, wherein:
the master control system comprises a master control CPU, a crystal oscillator circuit, a reset circuit, an AVCC filter circuit and a burning interface; the master control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the master control CPU; the AVCC filter circuit is respectively connected with the first power supply and the master control CPU and provides an analog power supply for the master control CPU;
the reset circuit is respectively connected with the first power supply and the master control CPU and controls the master control CPU to reset; the burning interface is respectively connected with an external burner and a master control CPU for the use of a master control burning program.
4. The current chip step test system of claim 3, wherein:
the master control system also comprises an indicator light and a signal button; the indicating lamp is respectively connected with the main control CPU and the first power supply and indicates the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as test trigger.
5. The current chip step test system of claim 2, wherein:
the first isolation circuit and the second isolation circuit comprise isolation chips and buffer circuits; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with signals of the master control system.
6. The current chip step test system of claim 2, wherein:
the virtual load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the chip to be tested, the chip to be tested is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as a load the same as the test load and used for switching current.
7. The current chip step test system of claim 2, wherein:
the test load comprises a switch tube, a trigger chip and a chip to be tested, the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external high-current constant-current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal.
8. The current chip step test system of claim 2, wherein:
the signal amplification module comprises an operational amplifier chip, a matching resistor, a positive signal matching circuit and a negative signal matching circuit; the operational amplification chip is respectively connected with the positive signal matching circuit, the negative signal matching circuit, the first power supply and the external oscilloscope, the positive signal matching circuit collects positive signals, and the negative signal matching circuit collects negative signals.
9. The current chip step test system of claim 2, wherein:
the power input interface comprises a first power input interface, a second power input interface and a high-current constant current source; the second power input interface is connected during an isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be detected, the reset circuit, the burning interface, the master control CPU, the signal button and the signal indicator lamp.
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| CN116736090A (en) * | 2023-08-16 | 2023-09-12 | 深圳市南方硅谷半导体股份有限公司 | Method and device for testing critical point bad chip and storage medium |
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| CN116736090A (en) * | 2023-08-16 | 2023-09-12 | 深圳市南方硅谷半导体股份有限公司 | Method and device for testing critical point bad chip and storage medium |
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