CN113092987B - Current chip step test system - Google Patents
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- CN113092987B CN113092987B CN202110225117.XA CN202110225117A CN113092987B CN 113092987 B CN113092987 B CN 113092987B CN 202110225117 A CN202110225117 A CN 202110225117A CN 113092987 B CN113092987 B CN 113092987B
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- 238000012360 testing method Methods 0.000 title claims abstract description 110
- 238000002955 isolation Methods 0.000 claims abstract description 61
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- 239000013078 crystal Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 15
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- 238000005859 coupling reaction Methods 0.000 description 2
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- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
Abstract
The invention discloses a current chip step test system which comprises a main control system, a first isolation circuit, a second isolation circuit, a first high-current switch, a second high-current switch, a signal amplification module and a power input interface, wherein the main control system is connected with the first high-current switch; the main control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the first isolation circuit is connected with a first high-current switch which can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch which can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load. The current chip step test system provided by the invention can reduce the price of test equipment and can perform multiple tests on the current chip.
Description
Technical Field
The invention belongs to the technical field of chip testing, relates to a testing system, and particularly relates to a current chip step testing system.
Background
Along with the development of artificial intelligence and automation, more and more sensors are needed, and the fields of high-power inverters, elevator door machines, charging piles, electric vehicles, automobile EPS, motor monitoring, intelligent electric meters and the like all need to monitor the state of equipment or induce specific current values, so that the current in the occasions is very high, the power is high, the current is hundreds of amperes at maximum, and the measurement is difficult.
The conventional method is to use a small-resistance resistor and a linear Hall for measurement, but the temperature characteristic is large, the cost is high, the test current is limited, and then a current Hall or a magnetic resistance sensing chip is developed in recent years, so that the problems are perfectly solved.
The current sensor chip is divided into a signal input end and a signal output end, and several key parameters need to be tested: the parameters of signal output rise time, signal output transmission delay and signal response time are not provided by testing equipment at all at home and abroad at present: the signal generator and the high-frequency high-power amplifier form a step signal, the current clamp is used as a trigger signal for testing, the rising time of the source end signal can reach 1us, the testing problem is solved, but the power amplifier and the current clamp are high in price, no equipment exists at home, the foreign countries have few types of equipment, and the domestic construction is very difficult.
In view of this, there is an urgent need to design a new high-current step test mode to overcome the above drawbacks and meet the test requirements to the maximum extent.
Disclosure of Invention
The invention provides a step test system for a current chip, which can reduce the price of test equipment and can test the current chip for multiple times.
In order to solve the technical problems, according to one aspect of the present invention, the following technical scheme is adopted:
a current chip step test system, the test system comprising: the system comprises a main control system, a first isolation circuit, a second isolation circuit, a first high-current switch, a second high-current switch, a virtual load, a test load, a signal amplification module and a power input interface;
the main control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit;
the first isolation circuit is respectively connected with the power input interface and the first high-current switch; the second isolation circuit is respectively connected with the power input interface and the second high-current switch;
the virtual load is respectively connected with the test load, the power input interface and the first high-current switch; the test load is respectively connected with the power input interface and the second high-current switch; the signal amplifying module is respectively connected with the test load and the power input interface;
the power input interface provides required electric energy for the main control system, the first isolation circuit, the second isolation circuit, the first high-current switch, the second high-current switch, the virtual load, the test load and the signal amplification module;
the main control system comprises a main control CPU, a crystal oscillator circuit, a reset circuit, a signal button, an AVCC filter circuit and a burning interface; the main control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the indicator light, the signal button, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the main control CPU; the AVCC filter circuit is respectively connected with the first power supply and the main control CPU and provides an analog power supply for the main control CPU;
the indicator light is respectively connected with the main control CPU and the first power supply and used for indicating the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as a test trigger;
the reset circuit is respectively connected with the first power supply and the main control CPU and controls the main control CPU to reset; the burning interface is respectively connected with an external burner and a main control CPU for being used by a main control burning program;
the first isolation circuit and the second isolation circuit comprise isolation chips and buffer circuits; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with a main control system signal;
the virtual load comprises a switching tube, a trigger chip and a chip to be tested, wherein the switching tube is respectively connected with a switching signal and a test chip, the test chip is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as the load same as the test load for switching current;
the test load comprises a switching tube, a trigger chip and a chip to be tested, wherein the switching tube is respectively connected with a switching signal and a test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal;
the signal amplifying module comprises an operational amplifier chip, a matching resistor, a positive signal matching circuit and a negative signal matching circuit; the operational amplification chip is respectively connected with a positive signal matching circuit, a negative signal matching circuit, a first power supply and an external oscilloscope, wherein the positive signal matching circuit collects positive signals, and the negative signal matching circuit collects negative signals;
the power input interface comprises a first power input interface, a second power input interface and a high-current constant current source; the second power input interface is connected with the isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be tested, the reset circuit, the burning interface, the main control CPU, the signal button and the signal indicator lamp.
According to another aspect of the invention, the following technical scheme is adopted: a current chip step test system, the test system comprising: the system comprises a main control system, a first isolation circuit, a second isolation circuit, a first high-current switch, a second high-current switch, a signal amplification module and a power input interface;
the main control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the power input interface is respectively connected with the first isolation circuit, the second isolation circuit, the first high-current switch, the second high-current switch and the signal amplifying module, and can also be connected with a virtual load and a test load;
the first isolation circuit is connected with a first high-current switch which can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch which can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load.
As one implementation mode of the invention, the main control system comprises a main control CPU, a crystal oscillator circuit, a reset circuit, an AVCC filter circuit and a burning interface; the main control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the main control CPU; the AVCC filter circuit is respectively connected with the first power supply and the main control CPU and provides an analog power supply for the main control CPU;
the reset circuit is respectively connected with the first power supply and the main control CPU and controls the main control CPU to reset; the burning interface is respectively connected with an external burner and a main control CPU for the main control burning program.
As one embodiment of the invention, the main control system further comprises an indicator light and a signal button; the indicator light is respectively connected with the main control CPU and the first power supply and used for indicating the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as a test trigger.
As one embodiment of the present invention, the first isolation circuit and the second isolation circuit each include an isolation chip and a buffer circuit; the isolation chip is respectively connected with the buffer circuit and the corresponding heavy current switch, and the buffer circuit is connected with the main control system signal.
As one implementation mode of the invention, the virtual load comprises a switching tube, a trigger chip and a chip to be tested, wherein the switching tube is respectively connected with a switching signal and a test chip, the test chip is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as the load same as the test load for switching current.
As one implementation mode of the invention, the test load comprises a switch tube, a trigger chip and a chip to be tested, wherein the switch tube is respectively connected with a switch signal and the test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal.
As one embodiment of the present invention, the signal amplifying module includes an operational amplifier chip, a matching resistor, a positive signal matching circuit, and a negative signal matching circuit; the operational amplification chip is respectively connected with a positive signal matching circuit, a negative signal matching circuit, a first power supply and an external oscilloscope, wherein the positive signal matching circuit collects positive signals, and the negative signal matching circuit collects negative signals.
As one embodiment of the present invention, the power input interface includes a first power input interface, a second power input interface, and a high-current constant current source; the second power input interface is connected with the isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be tested, the reset circuit, the burning interface, the main control CPU, the signal button and the signal indicator lamp.
The invention has the beneficial effects that: the current chip step test system provided by the invention can reduce the price of test equipment and can perform multiple tests on the current chip.
Drawings
FIG. 1 is a schematic diagram of a step test system for a current chip according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a master control system according to an embodiment of the invention.
FIG. 3 is a schematic diagram showing the components of a isolation circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating the composition of a dummy load according to an embodiment of the invention.
FIG. 5 is a schematic diagram showing the composition of a test load according to an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating a signal amplifying module according to an embodiment of the invention.
Fig. 7 is a schematic diagram of a power input interface according to an embodiment of the invention.
FIG. 8 is a flow chart of a testing method of a testing system according to an embodiment of the invention.
FIG. 9 is a waveform diagram of a test system according to an embodiment of the invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the present invention, preferred embodiments of the invention are described below in conjunction with the examples, but it should be understood that these descriptions are merely intended to illustrate further features and advantages of the invention, and are not limiting of the claims of the invention.
The description of this section is intended to be illustrative of only a few exemplary embodiments and the invention is not to be limited in scope by the description of the embodiments. It is also within the scope of the description and claims of the invention to interchange some of the technical features of the embodiments with other technical features of the same or similar prior art.
"connected" in the specification includes both direct and indirect connections.
FIG. 1 is a schematic diagram illustrating a current chip step test system according to an embodiment of the present invention; referring to fig. 1, the test system includes: the main control system 1, the first isolation circuit 2, the second isolation circuit 3, the first high-current switch 4, the second high-current switch 5, the signal amplifying module 6 and the power input interface 7. In an embodiment, the test system may further comprise a dummy load 8; in another embodiment, the test system may further comprise a test load 9.
The main control system 1 is respectively connected with a power input interface 7, a first isolation circuit 2 and a second isolation circuit 3; the power input interface 7 is respectively connected with the first isolation circuit 2, the second isolation circuit 3, the first high-current switch 4, the second high-current switch 5 and the signal amplifying module 6, and the power input interface 7 can also be connected with the virtual load 8 and the test load 9.
The first isolation circuit 2 is connected with a first high-current switch 4, and the first high-current switch 4 can be connected with a virtual load 8; the second isolation circuit 3 is connected with a second high-current switch 5, and the second high-current switch 5 can be connected with a test load 9; the virtual load 8 can be connected with a test load 9; the signal amplification module 6 can be connected to a test load 9.
FIG. 2 is a schematic diagram of a master control system according to an embodiment of the invention; referring to fig. 2, in an embodiment of the present invention, the main control system 1 includes a main control CPU 101, a crystal oscillator circuit 102, a reset circuit 103, an AVCC filter circuit 104, and a burning interface 105; the main control CPU 101 is respectively connected with the crystal oscillator circuit 102, the reset circuit 103, the AVCC filter circuit 104 and the burning interface 105. The crystal oscillator circuit 102 provides a system clock for the main control CPU 101; the AVCC filter circuit 104 is respectively connected to a first power supply (which may be a 5V power supply) and the main control CPU 101, and provides an analog power supply for the main control CPU 101. The reset circuit 103 is respectively connected with the first power supply and the main control CPU 101 and controls the main control CPU 101 to reset; the recording interface 105 is respectively connected to the external recorder and the main control CPU 101 for use in the main control recording program.
In an embodiment of the present invention, the master control system 1 further includes an indicator light 106 and a signal button 107; the indicator light 106 is respectively connected with the main control CPU 101 and the first power supply, and indicates the system state and the first power supply state; the signal button 107 is connected to the first power supply and the main control CPU 101, respectively, and is used as a test trigger.
FIG. 3 is a schematic diagram showing the components of a isolation circuit according to an embodiment of the present invention; referring to fig. 3, in an embodiment of the invention, the first isolation circuit 2 and the second isolation circuit 3 each include an isolation chip 201 and a buffer circuit 202; the isolation chip 201 is respectively connected with a buffer circuit 202 and corresponding heavy current switches (a first heavy current switch 4 and a second heavy current switch 5), and the buffer circuit 202 is connected with a main control system signal.
FIG. 4 is a schematic diagram illustrating the composition of a dummy load according to an embodiment of the present invention; referring to fig. 4, in an embodiment of the present invention, the dummy load 8 includes a first switching tube 801, a first trigger chip 802, and a first chip to be tested 803, the first switching tube 801 is connected to a switching signal and the first test chip 803 respectively, the first test chip 803 is connected to the first trigger chip 802, the first trigger chip 802 is connected to an external high-current constant current source, and the dummy load 8 is only used as the same load as the test load 9 for switching current.
FIG. 5 is a schematic diagram showing the composition of a test load according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the invention, the test load 9 includes a second switch tube 901, a second trigger chip 902, and a second chip to be tested 903, the second switch tube 901 is connected to the switch signal and the second test chip 903, the test chip 903 is connected to the second trigger chip 902 and the first power supply, the second trigger chip 902 is connected to the external high-current constant current source and the first power supply, the second trigger chip 902 generates the trigger signal, and the second test chip 903 generates the test signal.
FIG. 6 is a schematic diagram illustrating a signal amplifying module according to an embodiment of the invention; referring to fig. 6, in an embodiment of the invention, the signal amplifying module 6 includes an operational amplifier chip 601, a matching resistor 602, a positive signal matching circuit 603, and a negative signal matching circuit 604; the operational amplifier chip 601 is respectively connected with a positive signal matching circuit 603, a negative signal matching circuit 604, a first power supply and an external oscilloscope 10, wherein the positive signal matching circuit 603 collects positive signals, and the negative signal matching circuit 604 collects negative signals.
FIG. 7 is a schematic diagram illustrating the components of a power input interface according to an embodiment of the invention; referring to fig. 7, in an embodiment of the present invention, the power input interface 7 includes a 12V power input interface, a ±5v power input interface, and a high current constant current source. The 12V power input interface is connected during the isolation period; the + -5V power interface is respectively connected with an operational amplifier, a trigger sensor, a chip to be tested (for example, a sensor chip), a reset circuit, a burning interface, a main control CPU, a signal button and a signal indicator lamp.
FIG. 8 is a flow chart of a testing method of a testing system according to an embodiment of the invention; referring to fig. 8, in an embodiment of the invention, a testing method of a current chip step test system of the invention includes:
firstly, pressing a signal button once, and sending a virtual load switch signal after the main control system receives the button signal, and electrifying a virtual load through a current switch;
and then delaying for a period of time to wait for current stabilization (the step rise of a common large current source is slower), and after the current stabilization, the main control system performs current switching: the test load is electrified, and the virtual load current is cut off, so that a rapid step current can be generated on the test load; the current on the test load may not be limited to a high current constant current source due to the presence of the dummy load.
The invention discloses a step performance test of a current chip, which can be performed by using a common device and common equipment: the signal output rise time of the chip (time when the signal rises from 10% output to 90% output), the signal output transmission delay (time delay when the sense signal rises to 20% and the current chip output signal rises to 20%), the chip output response time (time delay when the sense signal rises to 80% and the current chip output signal rises to 80%).
In a use scene of the invention, the signal speed of the test is very fast, ns level, and the current is very large (loop resistance is very small), the parasitic capacitance of the loop is easy to generate coupling, and the parasitic inductance is easy to generate induced electromotive force. Through modification and ingenious layout, the invention effectively avoids the problems. The main control system is controlled by signal switching, the isolation optocoupler isolates the large-current signal to be detected from the main control system, and board-level system interference and coupling are avoided, and parasitic parameters of MOS are large. The invention selects the high-power patch MOS and matches the peripheral resistor, thereby eliminating the influence of MOS parasitic parameters. In one embodiment of the present invention, the workflow of the test system comprises: powering up the system through an external direct current power supply; powering on a common high-current direct current source; the oscilloscopes are correspondingly arranged; pressing a trigger switch; the main control system starts to operate; the main control system switches the virtual load and the signal to be detected; the oscilloscope detects the required waveform and records the required waveform (as shown in fig. 9).
The system has no special requirements on a high-power direct current source, is common, and has no special requirements on an oscilloscope. Because the test current is very large, the main control system skillfully processes the large current signal, and the danger is avoided.
In summary, the step test system for the current chip provided by the invention can reduce the price of test equipment and can perform multiple tests on the current chip. In the application scene of the invention, the main control system is utilized to control signals, the optocoupler is utilized to isolate the main control system and signals to be tested, the MOS tube is used as a large current switch, the trigger signal sensor uses a common quick response sensor, the large direct current source uses a common direct current source and then an oscilloscope is added to test corresponding parameters, the embarrassment that no equipment is available for a current sensor chip (even if the cost is high) is solved, and meanwhile, the safety guarantee is provided for a high-power inverter, an elevator door machine, a charging pile, an electric automobile, an automobile EPS and a motor monitoring and intelligent ammeter.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, an Application Specific Integrated Circuit (ASIC), a general purpose computer, or any other similar hardware device may be employed. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. Likewise, the software programs of the present application (including related data structures) may be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented in hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The description and applications of the present invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be embodied in the embodiments due to interference of various factors, and description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternatives and equivalents of the various components of the embodiments are known to those of ordinary skill in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other assemblies, materials, and components, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (4)
1. A current chip step test system, the test system comprising: the system comprises a main control system, a first isolation circuit, a second isolation circuit, a first high-current switch, a second high-current switch, a virtual load, a test load, a signal amplification module and a power input interface;
the main control system is used for current switching control, and firstly, the main control system sends out a control signal to enable the virtual load to be electrified, and after a period of time, the main control system controls current switching;
the main control system is respectively connected with the power input interface, the first isolation circuit and the second isolation circuit; the power input interface is respectively connected with the first isolation circuit, the second isolation circuit, the first high-current switch, the second high-current switch and the signal amplifying module, and can also be connected with a virtual load and a test load;
the first isolation circuit is connected with a first high-current switch which can be connected with a virtual load; the second isolation circuit is connected with a second high-current switch which can be connected with a test load; the virtual load can be connected with a test load; the signal amplification module can be connected with a test load;
the first isolation circuit and the second isolation circuit comprise isolation chips and buffer circuits; the isolation chip is respectively connected with a buffer circuit and a corresponding high-current switch, and the buffer circuit is connected with a main control system signal;
the virtual load comprises a switching tube, a trigger chip and a chip to be tested, wherein the switching tube is respectively connected with a switching signal and the chip to be tested, the chip to be tested is connected with the trigger chip, the trigger chip is connected with an external heavy current constant current source, and the virtual load is only used as the load same as the test load for switching current;
the test load comprises a switching tube, a trigger chip and a chip to be tested, wherein the switching tube is respectively connected with a switching signal and a test chip, the test chip is connected with the trigger chip and a first power supply, the trigger chip is respectively connected with an external heavy current constant current source and the first power supply, the trigger chip generates a trigger signal, and the test chip generates a test signal;
the signal amplifying module comprises an operational amplifier chip, a matching resistor, a positive signal matching circuit and a negative signal matching circuit; the operational amplification chip is respectively connected with a positive signal matching circuit, a negative signal matching circuit, a first power supply and an external oscilloscope, wherein the positive signal matching circuit collects positive signals, and the negative signal matching circuit collects negative signals.
2. The current chip step test system according to claim 1, wherein:
the main control system comprises a main control CPU, a crystal oscillator circuit, a reset circuit, an AVCC filter circuit and a burning interface; the main control CPU is respectively connected with the crystal oscillator circuit, the AVCC filter circuit, the reset circuit and the burning interface;
the crystal oscillator circuit provides a system clock for the main control CPU; the AVCC filter circuit is respectively connected with the first power supply and the main control CPU and provides an analog power supply for the main control CPU;
the reset circuit is respectively connected with the first power supply and the main control CPU and controls the main control CPU to reset; the burning interface is respectively connected with an external burner and a main control CPU for the main control burning program.
3. The current chip step test system according to claim 2, wherein:
the main control system also comprises an indicator light and a signal button; the indicator light is respectively connected with the main control CPU and the first power supply and used for indicating the system state and the first power supply state; the signal button is respectively connected with the first power supply and the main control CPU and used as a test trigger.
4. The current chip step test system according to claim 1, wherein:
the power input interface comprises a first power input interface, a second power input interface and a high-current constant current source; the second power input interface is connected with the isolation period; the first power interface is respectively connected with the operational amplifier, the trigger sensor, the sensor to be tested, the reset circuit, the burning interface, the main control CPU, the signal button and the signal indicator lamp.
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| CN116736090B (en) * | 2023-08-16 | 2023-11-07 | 深圳市南方硅谷半导体股份有限公司 | Method and device for testing critical point bad chip and storage medium |
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| CN111679236A (en) * | 2020-05-11 | 2020-09-18 | 国网江苏省电力有限公司营销服务中心 | Direct current transient state step response delay test method, system and device |
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