CN108287301B - IGBT driver testing system and method - Google Patents
IGBT driver testing system and method Download PDFInfo
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Abstract
The invention discloses a test system and a test method of an IGBT driver, wherein the system comprises the following components: the system comprises an upper computer, an FPGA control module, an input signal module and an output signal module, wherein the FPGA control module is respectively connected with the upper computer, the input signal module and the output signal module, and the upper computer is connected with the FPGA control module through a bus; the input signal module includes: the device comprises a driving secondary side voltage detection module, a secondary side short circuit protection threshold detection module, a fault detection module, a synchronous detection module, a dead zone detection module and a gate level voltage detection module; the output signal module includes: PWM output module, fault enabling module, output power module. The test system and the test method have the characteristics of multifunction, modularization and automation, can be suitable for different types of IGBT drivers, have expansibility and reduce test cost.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a test system and a test method of an IGBT driver.
Background
The IGBT driver is an important component in the new energy field, and is very important for the reliability and safety of the power switching device IGBTs widely used in the field. Therefore, before IGBT drivers are pushed into the market, they need to be tested in detail to ensure the function and performance of the IGBT drivers.
At present, the domestic and foreign IGBT driver test scheme mainly aims at designing a corresponding IGBT driver tester for a certain IGBT driver to carry out batch test. Because the IGBT driver has different types, the test control program is specific and has limitation; the IGBT drivers are various, and the tester needs to be replaced in the process of testing different IGBT drivers, so that the testing time and the testing cost are increased.
Disclosure of Invention
In order to solve the problems, the invention provides a system and a method for testing a general IGBT driver, which have perfect functions, high performance and automation.
The test system of the IGBT driver provided by the invention comprises: the system comprises an upper computer, an FPGA control module, an input signal module and an output signal module, wherein the FPGA control module is respectively connected with the upper computer, the input signal module and the output signal module, and the upper computer is connected with the FPGA control module through a bus; the input signal module includes: the device comprises a driving secondary side voltage detection module, a secondary side short circuit protection threshold detection module, a fault detection module, a synchronous detection module, a dead zone detection module and a gate level voltage detection module; the output signal module includes: PWM output module, fault enabling module, output power module.
The test method of the IGBT driver provided by the invention comprises the following steps: s1, inquiring a test model, and judging whether a corresponding test model exists according to test data; if yes, entering a step S3, otherwise entering a step S2; s2, setting a topological structure of the IGBT module, selecting test items, performing project configuration, setting qualified product judgment conditions, and generating a configuration file of a newly built test model; s3, loading configuration files corresponding to the test models, and updating a test model table; s4, scanning a product serial number, and automatically testing the selected test item; s5, judging whether the test result passes or not, if so, classifying the driver into a good product area, and if not, classifying the driver into a fault area.
The invention has the beneficial effects that: the whole system is modularized, the upper computer, the input signal module and the output signal module are connected through the FPGA control module, and test items of the IGBT driver can be expanded by modifying FPGA software according to different IGBT drivers by utilizing the characteristic of rich ports. The test system and the test method have the characteristics of multifunction, modularization and automation, can be suitable for different types of IGBT drivers, have expansibility and reduce test cost.
Drawings
Fig. 1 is a system block diagram of an IGBT driver test system in an embodiment of the invention.
Fig. 2 is a flowchart of a test method of an IGBT driver according to an embodiment of the invention.
Fig. 3 is a block diagram of an output power module according to an embodiment of the invention.
Fig. 4 is a block diagram of a PWM output module according to an embodiment of the present invention.
FIG. 5 is a block diagram of a fail-enable module in an embodiment of the invention.
FIG. 6 is a block diagram of a fault detection module in an embodiment of the invention.
Fig. 7 is a block diagram of a driving secondary side voltage detection module according to an embodiment of the invention.
Fig. 8 is a block diagram of a secondary side short-circuit protection threshold detection module in an embodiment of the invention.
Fig. 9 is a block diagram of a synchronization detection module in an embodiment of the invention.
Fig. 10 is a block diagram of a dead zone detection module in an embodiment of the invention.
Fig. 11 is a block diagram of a gate voltage detection module according to an embodiment of the invention.
Fig. 12 is a block diagram of a voltage detection unit in an embodiment of the invention.
Detailed Description
The invention will now be described in further detail with reference to the following detailed description and with reference to the accompanying drawings, it being emphasized that the following description is merely exemplary in nature and is not intended to limit the scope of the invention and its application.
As shown in fig. 1, the IGBT driver test system provided by the invention includes: the system comprises an upper computer, an FPGA control module, an input signal module and an output signal module; the FPGA control module is respectively connected with the upper computer, the input signal module and the output signal module, the upper computer is connected with the FPGA control module through a bus, and the bus can be specifically: 485 bus. The output signal module includes: the system comprises a PWM output module, a fault enabling module and an output power module. The input signal module includes: the device comprises a driving secondary side voltage detection module, a secondary side short-circuit protection threshold detection module, a fault detection module, a synchronous detection module, a dead zone detection module and a gate level voltage detection module. The whole system utilizes the characteristics of modularization and abundant ports, and can expand test items of the IGBT driver by modifying FPGA software.
The FPGA control module is a main control module of the system, and is used for realizing communication with an upper computer, PWM output setting, square wave output setting, voltage and current detection data conversion and time detection and providing a channel selection signal of a multi-channel selection chip.
According to the IGBT driver test system as described above, the test method of the system is as shown in fig. 2, and includes the steps of:
s11: the upper computer judges whether the test model flag bit is in a locking state, if so, the step S18 is carried out, and if not, the step S12 is carried out;
s12: executing all test items according to the maximum parallel series and the maximum level number structure;
s13: inquiring a test model table, judging whether a corresponding test model exists according to the test data, if so, entering a step S16, and if not, entering a step S14;
s14: judging whether an IGBT driver test model is newly built, if so, entering a step S15, and if not, entering a step S11;
s15: setting the topology structure of the IGBT module, selecting test items, performing project configuration, and setting qualified product judgment conditions;
s16: loading configuration files corresponding to the test models, and updating the test model table;
s17: if the locking test type operation is carried out, the step S18 is carried out, and if the locking test type operation is not carried out, the step S11 is carried out;
s18: and scanning the serial number of the product, automatically testing the selected test item, and storing the detailed data and the result of the test on a local server and a network server.
S19: judging whether the test result passes or not, if so, entering a step S20, and if not, entering a step S21;
s20: classifying IGBT drivers into good product areas;
s21: judging whether the test result fails for a plurality of times, if so, entering a step S22, and if not, entering a step S18;
s22: IGBT drivers are classified into fault regions.
Specifically, a universal IGBT driver test system is designed, only one test point adapting plate is needed for IGBT drivers of different models, and three parallel three-level IGBT drivers can be measured.
As shown in fig. 3, the output power module includes: the device comprises a power supply, a DC-DC power supply conversion module, an adjustable voltage module, a multi-channel selection chip and an output voltage and current detection unit. The DC-DC power supply conversion module is connected with the adjustable voltage module in parallel, and a power supply is connected with the DC-DC power supply conversion module and the adjustable voltage module; and the output voltage and current detection unit detects the output voltage and current and outputs the detected voltage and current to the FPGA control module. And the selection signal of the multi-channel selection chip is given by the FPGA control module.
As shown in fig. 4, the PWM output module includes: the FPGA control module, the level conversion unit and the one-more-channel selection chip are sequentially connected. The working principle is that the FPGA control module sends out PWM waveforms required by the system, the PWM level voltage is improved through level conversion, and PWM signals are output by the selected channels through the multi-channel selection chip. And the selection signal of the multi-channel selection chip is given by the FPGA control module.
As shown in fig. 5, the fail-enabling module includes: the level conversion unit, the multiple-channel selection chip and the output optocoupler; the FPGA control module, the level conversion unit, the multi-channel selection chip and the output optocoupler are connected in sequence; the working principle is that the FPGA control module sends out square waves required by the system, the level voltage of the square waves is increased through level conversion, and square wave signals are output through a selected channel through a multi-channel chip. Wherein, the selection signal of the multi-channel selection chip is given by the FPGA control module; the output optocoupler comprises a linear optocoupler.
As shown in fig. 6, the fault detection module includes: and the fault signal input port is connected with the FPGA control module. The working principle is that the IGBT driver sends out a fault signal when in fault, and the fault signal is transmitted to the FPGA control module through a fault signal input port of the tester.
As shown in fig. 7, the driving secondary side voltage detection module includes: the input optical coupler, the voltage detection unit and the FPGA control module are sequentially connected; the working principle is that the secondary side voltage signal is driven to be isolated through the input optocoupler, and the FPGA control module inputs the voltage signal through the voltage detection unit; the input optocoupler comprises a linear optocoupler.
As shown in fig. 8, the secondary side short-circuit protection threshold detection module includes: the device comprises an input optocoupler, a multi-channel selection chip and a voltage detection unit; the input optocoupler, the multiple-channel selection chip, the voltage detection unit and the FPGA control module are sequentially connected. The working principle is that a secondary side short-circuit protection voltage signal is isolated through an input optical coupler, an optical coupler output signal is output to a voltage detection unit through a selected channel through a multi-channel selection chip, and an FPGA control module analyzes the input signal to obtain a voltage value; and the selection signal of the multi-channel selection chip is given by the FPGA control module, and the input optocoupler comprises a linear optocoupler.
As shown in fig. 9, the synchronization detection module includes: inputting an optocoupler and selecting a channel selection chip; the input optocoupler, the one-way-in-one channel selection chip and the FPGA control module are sequentially connected. The working principle is that the driving output signal is isolated through the input optical coupler, the input optical coupler output signal realizes the output of the selected channel to the FPGA control module through the multi-channel selection chip, and the FPGA control module analyzes the input signal to obtain the synchronous time. And the selection signal of the multi-channel selection chip is given by the FPGA control module, and the input optocoupler comprises a linear optocoupler.
As shown in fig. 10, the dead zone detection module includes: inputting an optocoupler and selecting a channel selection chip; the input optocoupler, the one-way-in-one channel selection chip and the FPGA control module are sequentially connected. The working principle is that the driving output signal is isolated through the input optical coupler, the input optical coupler output signal realizes the output of the selected channel to the FPGA control module through the multi-channel selection chip, and the FPGA control module analyzes the input signal to obtain dead time. And the selection signal of the multi-channel selection chip is given by the FPGA control module, and the input optocoupler comprises a linear optocoupler.
As shown in fig. 11, the gate level voltage detection module includes: the device comprises an input optocoupler, a multi-channel selection chip and a voltage detection unit; the input optocoupler, the multiple-channel selection chip, the voltage detection unit and the FPGA control module are sequentially connected. The working principle is that the driving output signal is isolated through the input optical coupler, the input optical coupler output signal realizes the output of the selected channel to the voltage detection unit through the multi-channel selection chip, and the FPGA control module analyzes the input signal to obtain the voltage value. And the selection signal of the multi-channel selection chip is given by the FPGA control module, and the input optocoupler comprises a linear optocoupler.
In each of the above input signal modules, all of the voltage detecting units involved may be conventional voltage detecting units, but in order to improve the detection accuracy of the voltage detecting units, the following circuits are employed, as shown in fig. 12, the voltage detecting units include: the comparison circuit, the proportion circuit and the analog-to-digital conversion chip; the working principle is that a measured voltage signal is compared with a set value through a comparison circuit to obtain a proportional circuit enabling signal, and whether the voltage belongs to a high voltage range or a low voltage range is judged; the voltage signal passes through the proportional circuit at the same time, if the enabling signal of the proportional circuit is effective, the voltage signal is scaled and enters the analog-to-digital conversion chip for conversion; if the enabling signal of the proportional circuit is invalid, the voltage signal directly enters the analog-to-digital conversion chip for conversion. In the prior art, for one voltage signal, an analog-to-digital converter with the same sampling precision is generally adopted, but in the system, the voltage class of the same test voltage signal is different in different test models; firstly, grading the voltage signal by using a comparison circuit, and enabling the voltage signal with high voltage grade to enter a scaling circuit for scaling and then enter an analog-to-digital converter; the voltage signal with low voltage level directly enters the analog-to-digital converter, so that the accurate measurement of different voltage levels can be realized by using a high-precision analog-to-digital converter with low voltage range.
In the IGBT driver testing method, the configuration file and the operation instruction are issued to the FPGA control module by the upper computer through the 485 bus.
In step S11, it is determined whether the test model flag is in a locked state to determine whether the tester is testing a product of a particular test model.
In step S12, all test items are sequentially executed in a three-parallel series and three-level series structure.
In the judging process of steps S13 and S14, for the newly built IGBT driver model, step S15 is required to be entered, and for the newly built IGBT driver model, the topology structure of the IGBT module may be set, specifically including the parallel series number of IGBT modules, the level series number of IGBT modules, and the NTC (Negative Temperature Coefficient) detection series number. The IGBT drivers to be tested each have a unique serial number. Different test items and qualified product judgment conditions can be flexibly selected according to IGBT drivers of different models. The test items cover most of test items of the IGBT driver, and comprise static power consumption, on/off delay, on/off synchronous time, short-circuit protection time, fault locking time, dead time, undervoltage protection threshold, undervoltage recovery threshold, on voltage, off voltage, short-circuit protection threshold, secondary side voltage measurement, NTC detection and the like. For example: and in the newly-built IGBT driver model, setting the test items of the newly-built IGBT driver model to comprise all 13 test items, independently setting each test item, setting qualified product judgment conditions, and generating a corresponding parameter configuration file.
In step S16, since the test items of each IGBT driver model are different, the configuration file corresponding to the selected test model needs to be loaded.
In step S17, for different products of the same test model, in order to save time and improve test efficiency, the test model needs to be locked. The locked state may cause the next product to skip the step of detecting the test model, i.e., steps S12, S13, S14, S15, S16, S17. And unlocking the test model, and detecting and judging the test model.
In step S18, each IGBT driver has a unique serial number. And the test system automatically tests the selected test items, the test is completed, the test machine generates a table file to record test data, and a text file is generated to upload test results to the network server so as to facilitate data analysis and product state tracking.
In step S19, the test result generated by the example corresponds to 13 test items, and only if all 13 test items are qualified, the IGBT test driver can be judged to be qualified, and step S20 is entered to classify the IGBT test driver into a qualified product class; if at least one test item is unqualified and the IGBT driver is not tested before, the step S21 is carried out to judge that the IGBT driver is a retest item, and the step S18 is carried out to detect again; if the driver has a failure for a plurality of times, the IGBT driver is determined to be a failure, and the routine proceeds to step S22 to classify the IGBT driver into a failure class.
In order to adapt to the testing machine to independently test 13 test items and realize the universality of the testing machine, the system main circuit is configured with the 10 independent modules: the device comprises an output power supply module, an FPGA control module, a PWM output module, a fault enabling module, a fault detection module, a driving secondary side voltage detection module, a secondary side short circuit protection threshold detection module, a synchronous detection module, a dead zone detection module and a gate electrode voltage detection module. In order to achieve high accuracy of voltage detection due to different voltage levels tested by different driver models, the voltage detection involved in the above modules all employ a high accuracy detection circuit as shown in fig. 12. The relevant configuration of the 13 test items is transmitted to the FPGA control module by the upper computer through a communication bus.
When static power consumption measurement is carried out, the FPGA control module controls the output power supply module to output 15V power supply voltage according to configuration file setting, and converts and reads voltage and current signals transmitted back by the output power supply module.
When the on/off delay measurement is carried out, according to the configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to shield faults, and meanwhile, the on/off delay time is obtained by detecting the difference value of the PWM signal and the gate driving signal through the synchronous detection module.
When the on/off synchronization time is measured, according to the configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to shield faults, and meanwhile, the difference value of the parallel gate level driving signals is detected through the synchronization detection module to obtain the on/off synchronization time.
When short-circuit protection time measurement is carried out, according to configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to trigger faults, and meanwhile, the time difference from the on time to the off time of the gate electrode is detected through the synchronous detection module, and the time difference is the short-circuit protection time.
When fault locking time measurement is carried out, according to configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selection signal, the PWM signal, the fault enabling signal and the channel selection signal are respectively given to the PWM output module and the fault enabling module to trigger faults, and meanwhile, the fault detection module detects that the time difference from the falling edge moment to the rising edge moment of the fault signal of the driver is the fault locking time.
When dead time measurement is carried out, according to configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to shield faults, and meanwhile, the dead time of a driver is detected through the dead time detection module.
When the undervoltage protection threshold value is measured, the FPGA control module generates an adjustable voltage signal, a power channel selection signal and a fault enabling signal according to configuration file setting, the adjustable voltage signal, the power channel selection signal and the fault enabling signal are respectively given to the output power module and the fault enabling module, meanwhile, the fault detection module detects a driver fault signal, and when the driver fault signal is triggered, the output value of the output power module is measured to be the undervoltage protection threshold value.
When under-voltage recovery threshold measurement is carried out, according to configuration file setting, the FPGA control module generates an adjustable voltage signal, a power channel selection signal and a fault enabling signal, the adjustable voltage signal, the power channel selection signal and the fault enabling signal are respectively given to the output power module and the fault enabling module, meanwhile, a driver fault signal is detected, and when the driver fault signal disappears, the output value of the measured adjustable voltage is the under-voltage recovery threshold.
When the open voltage is measured, according to the configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to shield faults, and meanwhile, the gate voltage detection module detects the gate voltage signal to obtain the corresponding IGBT open voltage.
When the turn-off voltage is measured, according to the configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to shield faults, and meanwhile, the gate-level voltage detection module detects the gate-level voltage signal to obtain corresponding IGBT turn-off voltage.
When short-circuit protection threshold measurement is carried out, according to configuration file setting, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to trigger faults, and meanwhile, the short-circuit protection threshold is obtained through the secondary side short-circuit protection threshold detection module.
When the driving secondary side voltage is measured, the FPGA control module generates a PWM signal for testing, a fault enabling signal and a channel selecting signal according to configuration file setting, the PWM signal, the fault enabling signal and the channel selecting signal are respectively given to the PWM output module and the fault enabling module to trigger faults, and meanwhile, the driving secondary side voltage is obtained through the driving secondary side voltage detection module.
When NTC detection is carried out, according to configuration file setting, the FPGA control module generates fault enabling signals and channel selection signals for testing, the fault enabling signals and the channel selection signals are respectively given to the fault enabling module, and meanwhile driving fault signals are detected. If the driving fault is detected under the condition of enabling fault, and if the driving fault is not detected under the condition of shielding fault, the NTC function is considered to be normal, otherwise, the NTC function is considered to be faulty.
The foregoing is a further detailed description of the invention in connection with specific/preferred embodiments, and it is not intended that the invention be limited to such description. It will be apparent to those skilled in the art that several alternatives or modifications can be made to the described embodiments without departing from the spirit of the invention, and these alternatives or modifications should be considered to be within the scope of the invention.
Claims (9)
1. An IGBT driver test system, comprising: the system comprises an upper computer, an FPGA control module, an input signal module and an output signal module, wherein the FPGA control module is respectively connected with the upper computer, the input signal module and the output signal module, and the upper computer is connected with the FPGA control module through a bus; the input signal module includes: the device comprises a driving secondary side voltage detection module, a secondary side short circuit protection threshold detection module, a fault detection module, a synchronous detection module, a dead zone detection module and a gate level voltage detection module; the output signal module includes: the system comprises a PWM output module, a fault enabling module and an output power module;
the output power module includes: the device comprises a power supply, a DC-DC power supply conversion module, an adjustable voltage module, a multi-channel selection chip and an output voltage and current detection unit; the power supply is connected with the DC-DC power supply conversion module and the adjustable voltage module in parallel, the power supply supplies power to the DC-DC power supply conversion module and the adjustable voltage module, and the power supply voltage required by system control is given through the one-way selection chip; the selection signal of the multi-channel selection chip is given by the FPGA control module;
the PWM output module comprises a level conversion unit and a multi-channel selection chip, and the FPGA control module, the level conversion unit and the multi-channel selection chip are sequentially connected; the selection signal of the multi-channel selection chip is given by the FPGA control module;
the fault enabling module comprises a level conversion unit, a multi-channel selection chip and an output optocoupler; the FPGA control module, the level conversion unit, the multi-channel selection chip and the output optocoupler are connected in sequence; and the selection signal of the multi-channel selection chip is given by the FPGA control module.
2. The system of claim 1, wherein the fault detection module comprises a fault signal input port, the fault signal input port being connected with the FPGA control module.
3. The system of claim 1, wherein the driving secondary side voltage detection module comprises an input optocoupler and a voltage detection unit, the input optocoupler, the voltage detection unit and the FPGA control module are sequentially connected, the driving secondary side voltage signal is isolated by the input optocoupler, and the FPGA control module inputs the voltage signal through the voltage detection unit;
the secondary side short-circuit protection threshold detection module comprises an input optocoupler, a multi-channel selection chip and a voltage detection unit; the input optocoupler, the multiple-channel selection chip, the voltage detection unit and the FPGA control module are sequentially connected; and the selection signal of the multi-channel selection chip is given by the FPGA control module.
4. The system of claim 1, wherein the synchronous detection module comprises an input optocoupler, a multiple-channel selection chip; the input optocoupler, the multi-channel selection chip and the FPGA control module are sequentially connected, and the selection signal of the multi-channel selection chip is given by the FPGA control module.
5. The system of claim 1, wherein the dead zone detection module comprises an input optocoupler, a one-out-of-multiple channel selection chip; the input optocoupler, the multi-channel selection chip and the FPGA control module are sequentially connected, and the selection signal of the multi-channel selection chip is given by the FPGA control module.
6. The system of claim 1, wherein the gate level voltage detection module comprises an input optocoupler, a one-out-of-multiple channel selection chip, and a voltage detection unit; the input optocoupler, the multi-channel selection chip, the voltage detection unit and the FPGA control module are sequentially connected, and a selection signal of the multi-channel selection chip is given by the FPGA control module.
7. A method of testing a system according to any one of claims 1 to 6, comprising the steps of:
s1, inquiring a test model, and judging whether a corresponding test model exists according to test data; if yes, entering a step S3, otherwise entering a step S2;
s2, setting a topological structure of the IGBT module, selecting test items, performing project configuration, setting qualified product judgment conditions, and generating a configuration file of a newly built test model;
s3, loading configuration files corresponding to the test models, and updating a test model table;
s4, scanning a product serial number, and automatically testing the selected test item;
s5, judging whether the test result passes or not, if so, classifying the driver into a good product area, and if not, classifying the driver into a fault area.
8. The test method of claim 7, wherein the test item comprises: static power consumption, on/off delay, on/off synchronization time, short-circuit protection time, fault locking time, dead time, under-voltage protection threshold, under-voltage recovery threshold, on voltage, off voltage, short-circuit protection threshold, secondary side voltage measurement, NTC detection.
9. The test method of claim 7, wherein the topology comprises: IGBT module parallel series, IGBT module level series, NTC detection series.
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| CN101413983A (en) * | 2008-12-04 | 2009-04-22 | 吉林大学 | IGBT bridge circuit and drive protective circuit detection device |
| JP2012039458A (en) * | 2010-08-09 | 2012-02-23 | Honda Motor Co Ltd | Device and method of driving semiconductor element |
| CN202522687U (en) * | 2012-03-22 | 2012-11-07 | 广州三晶电气有限公司 | Detection device of frequency converter power supply board |
| CN104237761A (en) * | 2013-06-13 | 2014-12-24 | 通用电气公司 | Failure mode detection and protection system and method of insulated gate bipolar transistor |
| CN203561714U (en) * | 2013-09-20 | 2014-04-23 | 中国第一汽车股份有限公司 | A IGBT power module driving real-time monitoring apparatus |
| CN106597245A (en) * | 2016-11-04 | 2017-04-26 | 山东科技大学 | IGBT fault monitoring device and method |
| CN107329071A (en) * | 2017-07-11 | 2017-11-07 | Tcl空调器(中山)有限公司 | A kind of performance test circuit, test device and the method for IGBT drivers |
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