CN217935593U - Frequency band calibration circuit based on tuning voltage and frequency offset - Google Patents
Frequency band calibration circuit based on tuning voltage and frequency offset Download PDFInfo
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- CN217935593U CN217935593U CN202123297244.5U CN202123297244U CN217935593U CN 217935593 U CN217935593 U CN 217935593U CN 202123297244 U CN202123297244 U CN 202123297244U CN 217935593 U CN217935593 U CN 217935593U
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Abstract
The utility model relates to an electronic communication technical field discloses frequency band calibration circuit based on tuning voltage and frequency deviation, including tuning voltage generation unit, tuning voltage detecting element, two-way subband counting unit, regulation amplitude control unit and voltage controlled oscillator, be the output frequency subband through two-way subband counting unit's output signal control voltage controlled oscillator when in actual use, and two-way subband counting unit's output signal is decided by count direction and regulation amplitude, wherein the count direction is input by tuning voltage detecting element, the regulation amplitude is input by regulation amplitude control unit, consequently, do not need one-level adjustment when the frequency of adjusting the phase-locked loop, can be according to the difference multistage adjustment of the output frequency of reference frequency and voltage controlled oscillator, and then shorten the subband selection time of phase-locked loop.
Description
Technical Field
The utility model relates to an electronic communication technical field, concretely relates to frequency band calibration circuit based on tuning voltage and frequency deviation.
Background
The pll is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target frequency, has a very high frequency purity, and is often applied in the fields of frequency stabilization, communication modulation and demodulation of a radio transceiver.
Since the existing phase-locked loop needs a settling time from start-up to settling, the settling time is crucial for the receiver to respond quickly. The stability time of the current phase-locked loop includes a sub-band selection time and a dynamic response time determined by the characteristics of the phase-locked loop, wherein the sub-band selection time accounts for a large proportion of the stability time of the phase-locked loop, so that the prior art mostly reduces the sub-band selection time by a scheme based on tuning voltage detection or a scheme based on digital counting. The first scheme is simple in circuit in low-cost application, and high reliability of the first scheme is favored by most designers, but the main problems are that a long time is needed to detect whether the voltage is stable in the detection process, and the first scheme is switched to an ideal sub-band in a one-level-to-one mode, so that a long time is consumed.
SUMMERY OF THE UTILITY MODEL
In view of the deficiency of the background art, the utility model provides a frequency band calibration circuit based on tuning voltage and frequency deviation, except detecting the tuning voltage, still through calculating the output frequency of voltage controlled oscillator and the frequency deviation of reference frequency come the switching process of integrated control subband, can adjust the subband scope of voltage controlled oscillator with suitable amplitude to reduce the time that is used for the subband to select among the phase-locked loop locking process.
For solving the technical problem, the utility model provides a following technical scheme: the frequency band calibration circuit based on the tuning voltage and the frequency deviation comprises a tuning voltage generation unit, a tuning voltage detection unit, a bidirectional subband counting unit, an amplitude adjustment control unit and a voltage-controlled oscillator, wherein the tuning voltage generation unit generates the tuning voltage according to the phase difference between the input reference frequency and the output frequency of the voltage-controlled oscillator, the tuning voltage detection unit inputs a counting direction control signal to the bidirectional subband counting unit according to the tuning voltage, the bidirectional subband counting unit adjusts the counting direction according to the counting direction control signal, the amplitude adjustment control unit is used for calculating the difference value between the output frequency of the voltage-controlled oscillator and a set target frequency and inputting an amplitude adjustment control signal to the bidirectional subband counting unit according to the difference value, the bidirectional subband counting unit responds to the counting direction control signal and the amplitude adjustment control signal and inputs a frequency adjustment signal to the voltage-controlled oscillator, and the voltage-controlled oscillator responds to the frequency adjustment signal and adjusts the frequency of the output signal.
Optionally, in a certain embodiment, the tuning voltage generation unit includes a phase frequency detector, a charge pump, and a loop filter, where a reference frequency is input to the phase frequency detector, an output frequency of the voltage-controlled oscillator is input to the phase frequency detector through the frequency divider, the phase frequency detector is electrically connected to the charge pump, the charge pump is electrically connected to the loop filter, and the loop filter outputs the tuning voltage.
Optionally, in a certain embodiment, the tuning voltage detection unit includes at least two voltage comparison units, the tuning voltages are respectively input to each voltage comparison unit, and each voltage comparison unit inputs a counting direction control signal to the bidirectional subband counter according to the magnitude of the tuning voltage.
Optionally, in a certain embodiment, the bidirectional subband counting unit includes an adder/subtractor and a register, a counting direction input end of the adder/subtractor inputs the counting direction control signal, an adjustment amplitude input end of the adder/subtractor is electrically connected to the adjustment amplitude control unit, an output end of the adder/subtractor is electrically connected to the register, and the register is electrically connected to the voltage-controlled oscillator.
Optionally, in a certain embodiment, the adjustment amplitude control unit includes a counter, a timer, and a multi-path comparator, where the timer is used for timing, the counter counts an output signal of the voltage-controlled oscillator within a timing time, an output terminal of the counter is electrically connected to an input terminal of the multi-path comparator, and an output terminal of the multi-path comparator is electrically connected to an adjustment amplitude input terminal of the adder/subtractor.
Optionally, in a certain embodiment, the voltage-controlled oscillator includes a voltage-to-current converter and a current-controlled ring oscillator, the tuning voltage is input to a voltage input terminal of the voltage-to-current converter, the voltage-to-current converter inputs a control current of a corresponding magnitude to the current-controlled ring oscillator according to an output state of the register, and the current-controlled ring oscillator outputs a corresponding frequency according to the magnitude of the control current.
Optionally, in a certain embodiment, the voltage-to-current converter includes a current mirror circuit, the current mirror circuit includes a sampling circuit and a mirror circuit, the tuning voltage is input to the sampling circuit, the mirror circuit includes at least two mirror branches, each mirror branch is provided with a control switch, and an output signal of the register controls on/off of the control switch. Each mirror branch is equivalent to a subband, and the subbands in the voltage-controlled oscillator are selected by controlling the conduction of a control switch in the mirror branch.
Optionally, in a certain embodiment, the current-controlled ring oscillator includes at least two differential inverters, all of which are connected in series in sequence, and an output terminal of the last differential inverter is electrically connected to an input terminal of the first differential inverter.
Compared with the prior art, the utility model beneficial effect who has is: the utility model discloses be the output frequency who controls voltage controlled oscillator through the output signal of two-way subband counting unit when in actual use, and the output signal of two-way subband counting unit is decided by counting direction and amplitude modulation, wherein the counting direction is input by tuning voltage detection unit, amplitude modulation is input by amplitude modulation control unit, consequently, the one-level adjustment is not used when adjusting the frequency of phase-locked loop, can be according to the difference multistage adjustment of reference frequency and voltage controlled oscillator's output frequency, and then shorten the subband select time of phase-locked loop.
Drawings
The utility model discloses there is following figure:
FIG. 1 is a schematic view of the present invention;
FIG. 2 is a schematic view of the present invention;
fig. 3 is a schematic structural diagram of the regulated voltage detection unit of the present invention;
fig. 4 is a schematic structural diagram of the bidirectional subband counting unit according to the present invention;
fig. 5 is a schematic structural diagram of the amplitude-adjusting control unit of the present invention;
fig. 6 is a schematic structural diagram of the current control voltage-controlled oscillator of the present invention;
fig. 7 is a schematic structural diagram of the voltage-to-current converter of the present invention;
fig. 8 is an adjustment diagram of the present invention in practical application.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic drawings, which illustrate the basic structure of the present invention in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 1, the band calibration circuit based on tuning voltage and frequency offset includes a tuning voltage generation unit 1, a tuning voltage detection unit 2, a bidirectional subband counting unit 3, an adjustment amplitude control unit 4, and a voltage controlled oscillator 5, wherein the tuning voltage generation unit 1 generates a tuning voltage VTUNE according to a phase difference between an input reference frequency Fref and an output frequency Fback of the voltage controlled oscillator 5, the tuning voltage detection unit 2 inputs a counting direction control signal to the bidirectional subband counting unit 3 according to a magnitude of the tuning voltage VTUNE, the bidirectional subband counting unit 3 adjusts a counting direction according to the counting direction control signal, the adjustment amplitude control unit 4 calculates a difference between an output frequency of the voltage controlled oscillator 5 and a set target frequency and inputs an adjustment amplitude control signal to the bidirectional subband counting unit 3 according to the difference, the bidirectional subband counting unit 3 responds to the counting direction control signal and the adjustment amplitude control signal and inputs a frequency adjustment signal to the voltage controlled oscillator 5, and the voltage controlled oscillator responds to the frequency adjustment signal and adjusts a frequency of the output signal.
Referring to fig. 2, in this embodiment, the tuning voltage generating unit 1 includes a phase frequency detector, a charge pump, and a loop filter, where a reference frequency Fref is input to the phase frequency detector, an output frequency of the voltage-controlled oscillator 5 is input to the phase frequency detector through a frequency divider, the phase frequency detector is electrically connected to the charge pump, the charge pump is electrically connected to the loop filter, and the loop filter outputs the tuning voltage VTUNE. In practical use, when the phase frequency detector detects that the reference frequency Fref leads or lags behind the output frequency of the voltage-controlled oscillator 5, the charge pump is controlled to discharge or discharge the loop filter, and then a variable tuning voltage VTUNE is generated.
Referring to fig. 3, in this embodiment, the tuning voltage detection unit 2 includes at least two voltage comparison units, where the two voltage comparison units are comparators COMP, each voltage comparison unit inputs a lower limit voltage VREF _ LOW, each voltage comparison unit inputs an upper limit voltage VREF _ HIGH, the tuning voltage VTUNE is input to each voltage comparison unit, and each voltage comparison unit inputs a counting direction control signal to the bidirectional subband counter according to the magnitude of the tuning voltage.
In this embodiment, the tuning voltage detection unit 2 is configured to detect a relationship between the tuning voltage VTUNE and the lower limit voltage VREF _ LOW and the upper limit voltage VREF _ HIGH, and since the tuning voltage VTUNE and the lower limit voltage VREF _ LOW and the upper limit voltage VREF _ HIGH have only three pieces of status information, which are: the tuning voltage VTUNE is smaller than the lower limit voltage VREF _ LOW, the tuning voltage VTUNE is between the lower limit voltage VREF _ LOW and the upper limit voltage VREF _ HIGH, and the tuning voltage VYUNE is larger than the upper limit voltage VREF _ HIGH, so that the three states can be represented by only two voltage comparison units.
In practical use, if the tuning voltage VTUNE is less than the lower limit voltage VREF _ LOW, STATE <1 > =00, which means that the phase of the feedback output frequency Fback of the voltage-controlled oscillator 5 passing through the frequency divider lags behind the reference frequency Fref, that is, the current sub-band is higher than the target sub-band, and the value of the bidirectional self-band counting unit 3 needs to be decreased to decrease the output frequency of the voltage-controlled oscillator 5.
If the tuning voltage VTUNE is between the lower limit voltage VREF _ LOW and the upper limit voltage VREF _ HIGH, STATE <1 > =01, which means that the current subband of the voltage controlled oscillator 5 is in a suitable interval, the phase locked loop can lock normally, and the subband of the voltage controlled oscillator does not need to be adjusted.
If the tuning voltage VTUNE is greater than the upper limit voltage VREF _ HIGH, STATE <1 > =11, which means that the phase of the feedback output frequency Fback of the voltage-controlled oscillator 5 passing through the frequency divider still leads the phase of the reference frequency Fref, i.e. the current sub-band is higher than the target sub-band, the value of the bidirectional self-band counting unit 3 needs to be increased to increase the output frequency of the voltage-controlled oscillator 5.
Therefore, in this embodiment, the tuning voltage detection unit 2 has two functions, namely, determining whether the output frequency of the current voltage-controlled oscillator 5 is within the target subband, and determining the subband adjusting direction of the current voltage-controlled oscillator 5. In one embodiment, the voltage comparison unit may select the remaining voltage comparison circuits, or may output two or more bits of mostly encoded information as long as the state information can detect the range of the section of the tuning voltage VTUNE.
Referring to fig. 4, in the present embodiment, the bidirectional subband counting unit 3 includes an adder/subtractor and a register, the counting direction input terminal of the adder/subtractor inputs the counting direction control signal, the adjustment amplitude input terminal of the adder/subtractor is electrically connected to the adjustment amplitude control unit 4, the output terminal of the adder/subtractor is electrically connected to the register, and the register is electrically connected to the voltage-controlled oscillator 5.
When the voltage-controlled oscillator is actually used, the adder/subtracter counts according to the counting direction input by the tuning voltage detection unit 2 and the adjusting amplitude input by the adjusting amplitude control unit 4, a counting result is sent to a register after counting is finished, and an output signal of the register is triggered and input to the voltage-controlled oscillator through a synchronous adjusting signal. In addition, the register is also provided with a SET (SET event) RESET end and a RESET RESET end, and an initial value can be given to the register to be close to a target sub-band when a trigger signal is electrified so as to accelerate loop locking.
Referring to fig. 5, in the present embodiment, the adjustment amplitude control unit 4 includes a counter, a timer, and a multi-path comparator, the timer is used for timing, the counter counts the output signal of the voltage controlled oscillator within a timing period, an output terminal of the counter is electrically connected to an input terminal of the multi-path comparator, and an output terminal of the multi-path comparator is electrically connected to an adjustment amplitude input terminal of the adder/subtractor.
The working principle of the amplitude control unit 4 is as follows: when the tuning voltage VTUNE is smaller than the lower limit voltage VREF _ LOW or the tuning voltage VYUNE is larger than the upper limit voltage VREF _ HIGH, in a timing period T of the timer, firstly delaying the time of 1/4T and resetting the value K of the counter, then starting to count the number of clocks of the feedback output frequency Fback of the voltage-controlled oscillator 5 after frequency division by the frequency divider until the end of the period, comparing the count value of the counter with the standard clock count value, and when K4/3T is larger than M Δ f and smaller than (M + 1) Δ f, confirming that M or M +1 is the most appropriate adjustment amplitude.
In addition, the reason why the counting is delayed by 1/4T period in this embodiment is that the control voltage generates a step response in a period of time after the subband switching, and thus the output frequency of the vco 5 is not stable, and therefore, the counting needs to be delayed by a period of time.
In addition, considering the response time relationship of bandwidth to loop lock:
wherein, Δ fThe frequency difference before and after jumping (under the same VTUNE voltage control, the frequency difference of different sub-bands), zeta is the equivalent damping coefficient of the phase-locked loop, epsilon error To the maximum frequency error, ω, tolerated close to the target frequency BW For the loop bandwidth of the phase-locked loop, the timing time T of the timer is generally taken as 4 × tlock to ensure that the counter is given enough time to perform frequency calculation.
Referring to fig. 2, in the present embodiment, the voltage-controlled oscillator 5 includes a voltage-to-current converter to which the tuning voltage VTUNE is input, and a current-controlled ring oscillator to which a control current of a corresponding magnitude is input according to an output state of the register, and which outputs a corresponding frequency according to the magnitude of the control current.
Referring to fig. 7, in this embodiment, the voltage-current converter includes a current mirror circuit, the current mirror circuit includes a sampling circuit 50 and a mirror circuit 51, the tuning voltage VTUNE is input to the sampling circuit 50, the mirror circuit 51 includes at least two mirror branches 52, each mirror branch 52 is provided with a control switch K1, and an output signal of the register controls on/off of the control switch K1. Wherein each mirror branch 52 corresponds to a subband and the subband in the voltage controlled oscillator 5 is selected by controlling the control switch K1 in the mirror branch 52 to be conductive.
Specifically, in this embodiment, the voltage-to-current converter is a common-source amplifier, converts an input voltage signal into a current signal and outputs the current signal, amplifies the current by a current mirror and then inputs the amplified current signal to the current-controlled ring oscillator, and can control the sub-band by controlling the on/off of the control switch K1 in the mirror-image branch 52, and simultaneously convert the change of the tuning voltage VTUNE into the current change of each output current tube, and also accomplish the fine tuning of the output frequency of the current-controlled ring oscillator, so that the two are combined together to have the function of a voltage-controlled oscillator, and have the characteristics of high linearity and small area. The ICTRL may also be controlled directly by a tuning voltage VTUNE to form a voltage controlled oscillator in the conventional sense, the principle being similar to that described above
Referring to fig. 6, in the present embodiment, the current-controlled ring oscillator includes four differential inverters, all of which are connected in series in sequence, and the output terminal of the last differential inverter is electrically connected to the input terminal of the first differential inverter. The four differential phase inverters form a positive feedback loop and can normally start oscillation by self excitation. Meanwhile, the synchronization of differential signal edges is ensured by adopting a connection mode of complementary signal cross coupling of each level of phase inverter. According to the principle of the inverter, when the supply current of the inverter is larger, the PMOS tube can output larger driving current, and if the delay of each stage of the inverter is td, the frequency of the four-stage inverter is 1/(2 x 4 td), so that the frequency can be controlled by adjusting the ICTRL current. In practical use, two, three or more than four differential inverters can be selected according to requirements to design the current control ring oscillator.
The working principle of the utility model is as follows: the output signal of the register of the bidirectional subband counting unit 3 is used for controlling the on-off of a control switch K1 in each mirror branch 52 in the voltage-current converter, so that the subband selection of the phase-locked loop is realized, in addition, the output signal of the register of the bidirectional subband counting unit 3 is determined by the counting direction and the adjusting amplitude of an adder/subtracter, so that the counting direction of the bidirectional subband counting unit 3 is determined by the tuning voltage detection unit 2, the counting amplitude of the bidirectional subband counting unit 3 is determined and controlled by the adjusting amplitude control unit 4, the subbands of the voltage-current converter can be selected in multiple stages, and one-stage switching is not needed.
Referring to fig. 8, the subband tuning process of the voltage-to-current converter is as follows: in fig. 8, assuming S1 as the starting point, S2 is taken as the intermediate process, S3 is taken as the final target point, and Δ fs represents the distance between two sub-bands. When the amplitude control unit 4 starts to adjust and detect that the frequency of S1 is lower than S3 and the frequency deviation is larger than 2 Δ fs, 3 sub-bands are added at a time to reach the position of S2; when the tuning voltage VTUNE is found to be larger than the upper limit voltage VREF _ HIGH after S2 is reached, and the frequency deviation is larger than 1 Δ fs and smaller than two Δ fs, the position of the phase-locked loop reaching S3 is reduced by 1 subband, and the tuning voltage VTUNE reaches a designed area, which represents that the phase-locked loop is normally locked, so that the phase-locked loop can be regarded as a proper subband position, and the subband is kept unchanged. When voltage, temperature and Process Variations (PVT) occur, the tuning voltage VTUNE drifts, causing a drift out of the lock area, and the same adjustment procedure as above will occur to adjust the phase locked loop to the locked position.
In addition, in the above adjusting process, a synchronous clock provides a synchronous beat to cooperate with the implementation of the function, which may specifically refer to the following: resetting after power-on, resetting a counter of the adjusting amplitude control unit 4 to zero to start counting, simultaneously resetting the register position of the bidirectional subband counter 3 to an intermediate position, and operating a period to start a subband adjusting process; when the first synchronous clock after the resetting is finished temporarily judges the located interval of the tuning voltage VTUNE, the adjusting direction is output, and meanwhile, the adjusting amplitude control unit 4 judges the error between the current frequency and the target frequency according to the back 3T/4 counting value and outputs the adjusting amplitude; when a second clock comes, the state of the adjusting amplitude and the state of the tuning voltage VTUNE are output to a bidirectional subband counter 3, then the state of the tuning voltage VTUNE is continuously monitored, and an adjusting amplitude control unit 4 continuously counts and calculates the frequency difference; eventually, until the tuning voltage VTUNE is at the appropriate interval position, the bi-directional subband adjuster 3 will remain unchanged.
In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims. Based on the explanations herein, those skilled in the art will realize other embodiments of the present patent without any creative effort, which shall fall within the protection scope of the present patent.
Claims (7)
1. Frequency band calibration circuit based on tuning voltage and frequency offset, its characterized in that: the tuning voltage generation unit generates tuning voltage according to the phase difference between input reference frequency and output frequency of the voltage-controlled oscillator, wherein the tuning voltage generation unit comprises a phase frequency detector, a charge pump and a loop filter, the reference frequency is input into the phase frequency detector, the output frequency of the voltage-controlled oscillator is input into the phase frequency detector through a frequency divider, the phase frequency detector is electrically connected with the charge pump, the charge pump is electrically connected with the loop filter, and the loop filter outputs the tuning voltage; the tuning voltage detection unit inputs a counting direction control signal to the bidirectional subband counting unit according to the tuning voltage, the bidirectional subband counting unit adjusts the counting direction according to the counting direction control signal, the adjusting amplitude control unit is used for calculating the difference value between the output frequency of the voltage-controlled oscillator and a set target frequency and inputting an adjusting amplitude control signal to the bidirectional subband counting unit according to the difference value, the bidirectional subband counting unit responds to the counting direction control signal and the adjusting amplitude control signal and inputs a frequency adjusting signal to the voltage-controlled oscillator, and the voltage-controlled oscillator responds to the frequency adjusting signal and adjusts the output frequency.
2. The tuning voltage and frequency offset based band calibration circuit of claim 1, wherein: the tuning voltage detection unit comprises at least two paths of voltage comparison units, the tuning voltages are respectively input to each path of voltage comparison unit, and each path of voltage comparison unit inputs a counting direction control signal to the bidirectional subband counter according to the magnitude of the tuning voltages.
3. The tuning voltage and frequency offset based band calibration circuit according to claim 1 or 2, wherein: the bidirectional subband counting unit comprises an adder/subtractor and a register, wherein a counting direction input end of the adder/subtractor inputs the counting direction control signal, an adjusting amplitude input end of the adder/subtractor is electrically connected with the adjusting amplitude control unit, an output end of the adder/subtractor is electrically connected with the register, and the register is electrically connected with the voltage-controlled oscillator.
4. The tuning voltage and frequency offset based band calibration circuit of claim 3, wherein: the adjusting amplitude control unit comprises a counter, a timer and a multi-path comparator, the timer is used for timing, the counter counts output signals of the voltage-controlled oscillator within timing time, the output end of the counter is electrically connected with the input end of the multi-path comparator, and the output end of the multi-path comparator is electrically connected with the adjusting amplitude input end of the adder/subtracter.
5. The tuning voltage and frequency offset based band calibration circuit of claim 4, wherein: the voltage-controlled oscillator comprises a voltage-current converter and a current-controlled ring oscillator, the tuning voltage is input to a voltage input end of the voltage-current converter, the voltage-current converter inputs control current with corresponding magnitude to the current-controlled ring oscillator according to the output state of the register, and the current-controlled ring oscillator outputs corresponding frequency according to the magnitude of the control current.
6. The tuning voltage and frequency offset based band calibration circuit of claim 5, wherein: the voltage-current converter comprises a current mirror circuit, the current mirror circuit comprises a sampling circuit and a mirror circuit, the tuning voltage is input into the sampling circuit, the mirror circuit comprises at least two mirror branches, each mirror branch is provided with a control switch, and the output signal of the register controls the on-off of the control switch.
7. The tuning voltage and frequency offset based band calibration circuit of claim 5, wherein: the current control ring oscillator comprises at least two differential inverters, all the differential inverters are sequentially connected in series, and the output end of the last differential inverter is electrically connected with the input end of the first differential inverter.
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| CN2021210276865 | 2021-05-13 | ||
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098508A (en) * | 2021-05-13 | 2021-07-09 | 江苏集萃智能集成电路设计技术研究所有限公司 | Phase-locked loop |
| CN116436459A (en) * | 2023-06-12 | 2023-07-14 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
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2021
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098508A (en) * | 2021-05-13 | 2021-07-09 | 江苏集萃智能集成电路设计技术研究所有限公司 | Phase-locked loop |
| CN113098508B (en) * | 2021-05-13 | 2023-12-15 | 江苏集萃智能集成电路设计技术研究所有限公司 | Phase locked loop |
| CN116436459A (en) * | 2023-06-12 | 2023-07-14 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
| CN116436459B (en) * | 2023-06-12 | 2024-03-01 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
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