CN217767478U - Multi-channel high-speed low-delay control panel of quantum computer - Google Patents

Abstract

The application discloses control panel that low delay of multichannel high speed of quantum computer relates to the quantum computer field, especially relates to a control panel that low delay of multichannel high speed of quantum computer, and it includes: the system comprises an FPGA chip module, a precision clock module, an optical fiber communication module and a data communication module; the precision clock module is used for generating a high-precision clock signal of 125 MHz; the optical fiber communication module is used for performing interconversion between optical fiber signals and electric signals; the FPGA chip module is used for carrying out low-delay processing on the electric signal data; the data communication module is used for outputting and/or receiving low-voltage differential signals and communicating with each quantum computer through an external interface board card; the multi-channel low-delay high-speed data communication of 125MHz is realized, and the control can be carried out by an upper computer, so that the operation mode of the ion trap quantum computer is simplified.

Description

Multi-channel high-speed low-delay control panel of quantum computer

Technical Field

The application relates to the field of quantum computers, in particular to a multi-channel high-speed low-delay control board of a quantum computer.

Background

The physical systems of quantum computing currently and internationally explored comprise superconduction, ion traps, super-cooled atoms, semiconductor quantum dots and the like, wherein the ion trap quantum computing has the three characteristics of long coherence time and high preparation and reading efficiency of quantum bits due to high quantum bit quality.

The technical principle of the method is that the interaction force between charges and an electromagnetic field is utilized to restrain the motion of charged particle bodies, and two energy levels consisting of the ground state and the excited state of limited ions are utilized as quantum bits. On one hand, an ion trap quantum computer needs a control system to complete a series of control operations within a limited time due to the limited coherence time of a quantum bit, and on the other hand, high-precision timing control is required due to the fact that the operation of a logic gate needs high phase coherence.

When the ion trap quantum computer is operated, multi-channel data processing with high speed, parallel and low delay is needed. The existing data processing control panel is in a mode of controlling equipment by a CPU (central processing unit), has low data processing speed, cannot process data in parallel, has high delay and few channels, and cannot meet the requirements.

SUMMERY OF THE UTILITY MODEL

The utility model aims at avoiding the weak point among the prior art and providing a control mainboard that can reach the synchronous precision of control delay of sub-microsecond level and nanosecond level.

The purpose of the utility model is realized through the following technical scheme:

a multi-channel high-speed low-delay control board of a quantum computer, comprising: the system comprises an FPGA chip module, a precision clock module, an optical fiber communication module and a data communication module; the FPGA chip module is respectively and independently linked with the precision clock module, the optical fiber communication module and the data communication module; the optical fiber communication module is used for being connected with an upper computer; the precise clock module is used for generating a high-precision clock signal of 125 MHz; the optical fiber communication module is used for carrying out interconversion between optical fiber signals and electric signals; the FPGA chip module is used for carrying out low-delay processing on the electric signal data; the data communication module is used for outputting and/or inputting low-voltage differential signals and communicating with the quantum computer through an external interface board card.

Specifically, the system further comprises a configuration module; the configuration module is connected with the FPGA chip module, and the configuration module is connected with a peripheral configuration device and used for controlling each configuration pin of the FPGA.

More specifically, the device also comprises a storage module; the storage module is connected with the FPGA chip module; the storage module comprises a FLASH memory circuit and a DDR memory circuit which are respectively connected with a FLASH memory and a DDR memory.

More specifically, the DDR memory adopts a model number MT41K256M16TW-107: p memory chips.

In another embodiment, the optical fiber communication module includes an optical fiber signal circuit and a plurality of groups of optical fiber interface circuits; the precise clock module is connected with the optical fiber signal circuit; each group of optical fiber interface circuits are respectively and independently connected with the optical fiber signal circuit.

Furthermore, the precision clock module comprises a clock crystal oscillator circuit; the clock crystal oscillator circuit comprises a clock crystal oscillator chip; the clock crystal oscillator chip adopts a chip with the model number of 549CBAC000112 ABG.

Furthermore, the precision clock module also comprises a clock signal driving circuit; the clock signal driving circuit comprises a clock signal buffer driver and a plurality of radio frequency output interfaces; the clock signal buffer driver adopts a chip with the model number ADCLK948 BCPZ.

Furthermore, the data communication module comprises a plurality of groups of I2C interface circuits; and each group of I2C interface circuits are respectively and independently connected with corresponding electrostatic protection circuits.

In the above, the FPGA chip module comprises an FPGA chip with the model of XC7A100T-3FGG 484E.

Furthermore, the power supply module comprises a power supply input circuit and a power supply conversion circuit; the power input circuit comprises a common-mode inductor, a filter capacitor and a voltage stabilizing diode; each output end of the power supply conversion circuit is provided with a filter.

The utility model discloses the beneficial effect who reaches: a multi-channel high-speed low-delay control board of a quantum computer, comprising: the system comprises an FPGA chip module, a precision clock module, an optical fiber communication module and a data communication module; the precision clock module is used for generating a high-precision clock signal of 125 MHz; the optical fiber communication module is used for performing interconversion between optical fiber signals and electric signals; the FPGA chip module is used for carrying out low-delay processing on the electric signal data; the data communication module is used for outputting and/or receiving low-voltage differential signals and communicating with each quantum computer through an external interface board card; the multi-channel low-delay high-speed data communication of 125MHz is realized, and the control can be carried out by the upper computer, so that the operation mode of the ion trap quantum computer is simplified.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a block diagram of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a power input circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 3 is a schematic circuit diagram of a power conversion circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a FLASH memory circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 5 is a schematic circuit diagram of a DDR memory circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of a chip configuration circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 7 is a schematic circuit diagram of a clock oscillator circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a clock signal driving circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 9 is a schematic circuit diagram of an I2C interface circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 10 is a schematic circuit diagram of an electrostatic protection circuit of an I2C interface of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

FIG. 11 is a schematic circuit diagram of an optical fiber signal circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application;

fig. 12 is a schematic circuit diagram of an optical fiber interface circuit of a multi-channel high-speed low-delay control board of a quantum computer according to an embodiment of the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below through embodiments with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Example one

A multi-channel high-speed low-delay control board of a quantum computer, as shown in fig. 1 to 12, comprising: the device comprises an FPGA chip module, a power supply module, a storage module, a configuration module, a precision clock module, an optical fiber communication module and a data communication module.

The power supply module is respectively and independently connected with the FPGA chip module, the storage module, the configuration module, the precision clock module, the optical fiber communication module and the data communication module to supply power for each module.

Specifically, the power module includes a power input circuit and a power conversion circuit. The power input circuit comprises common mode inductors FL1 and FL2 with the voltage of 10A/50V, a filter capacitor and a voltage stabilizing diode SMBJ12A, and pulse signals or noise of other modules are prevented from entering the circuit.

The power conversion circuit adopts an ADP5052ACPZ multi-channel output power chip to convert a 12V power into voltages of 3.3V,2.5V,1.8V,1.5V,1.2V and 1.0V to supply power to electronic components of each module, and simultaneously, the power conversion circuit adopts a TLV62565DBVT high-precision linear voltage stable power chip to convert the 3.3V voltage into the 1.8V voltage. An LC filter is added at each output end of the power conversion circuit to stabilize the output voltage.

The optical fiber communication module is used for being connected with an upper computer and used for carrying out interconversion between optical fiber signals and electric signals.

Specifically, the optical fiber communication module comprises an optical fiber signal circuit and a plurality of groups of optical fiber interface circuits; each group of optical fiber interface circuits are respectively and independently connected with the optical fiber signal circuit. In an embodiment of the present application, the fiber optic signal circuit provides a 4-way gigabit data rate communication channel. The precision clock module is connected with the optical fiber signal circuit and provides 125MHz high-precision clock signals for the 4 communication channels. Each group of optical fiber interface circuits are mounted on the PCB in a crimping mode by adopting a chip model number of U77A11108000P, and the mode ensures the quality of high-speed signals.

The FPGA chip module is respectively and independently linked with the precision clock module, the storage module, the configuration module, the optical fiber communication module and the data communication module. The FPGA chip module is used for carrying out low-delay processing on the electric signal data.

Specifically, the FPGA chip module comprises an FPGA chip with the model of XC7A100T-3FGG 484E. The device has the following advantages:

1. the interior is realized by pure hardware, and input and output signals can be processed in parallel;

2. the signal processing speed is high, and microsecond-level processing delay can be realized;

3. the communication speed with the daughter board is high, the pin speed of the differential pair can reach 680Mb/s, and the 125MHz requirement of the communication speed designed by the scheme is met;

4. the internal capacity is large, and the number of logic units is up to 101440;

5. FGG484 BGA 1.0 pin pitch small volume dense pin package is used.

6. Total 484 external pins are provided, 285 available IO ports are available, and the pin resource requirement of 8 × 12=96 pairs of differential signals can be met.

The configuration module comprises a chip configuration circuit and a serial port module. The configuration module is connected with the FPGA chip module, and the configuration module is connected with a peripheral configuration device and used for controlling each configuration pin of the FPGA.

The storage module comprises a FLASH memory circuit and a DDR memory circuit which are respectively connected with a FLASH memory and a DDR memory. If a large amount of data needs to be stored when the FPGA runs, the DDR RAM memory is used for completing storage. The DDR memory adopts a model number MT41K256M16TW-107: p memory chips. The chip has the capacity of 256Mb, the rate of 1866MHz, the voltage of 1.5V and the DDR3 standard. The method has the advantages of large capacity, high speed and low power consumption, and can meet the high-speed and high-capacity data storage requirement of the scheme.

The precise clock module comprises a clock crystal oscillator circuit and a clock signal driving circuit; the clock crystal oscillator circuit comprises a programmable clock crystal oscillator chip.

Specifically, the programmable clock crystal oscillator chip adopts a chip with model 549CBAC000112ABG and is used for generating a precise 125MHz clock signal. The chip outputs clock signals by using 2.5V CMOS differential signals, and the anti-interference capability of output signals is improved. The output end of the high-frequency power amplifier is also provided with a series matching resistor of 30 ohms, so that the impedance of signal routing can be matched, and the signal integrity index can be improved. It has the following advantages:

1. the clock signal of 250MHz can be output, and the system clock frequency requirement of 125MHz can be met;

2. the ultra-low jitter output of as low as 95 femtoseconds is far superior to the commonly used jitter output index of the crystal oscillator picosecond level;

3. the temperature jitter is low and is only +/-25 ppm;

4. the power supply voltage is 2.5V, the working current is 127mA, and the power consumption is low;

5. the I2C interface can be adopted to control the output frequency, thereby providing extremely high flexibility;

and 6, the CMOS 2.5V differential output signal greatly improves the anti-interference capability of the signal compared with the common single-ended output signal.

Specifically, the 125MHz clock signal output by the clock oscillator circuit is input to the clock signal driver circuit. The clock signal driving circuit comprises a clock signal buffer driver and a plurality of radio frequency output interfaces; the clock signal buffer driver adopts a chip with the model number of ADCLK948BCPZ and is used for copying the input 125MHz clock signal into a plurality of paths for output; in this embodiment, the 125MHz clock signal output by the clock signal driving circuit serves as the working master clock of the FPGA chip module; the clock signal can be supplied to 4 paths of clock signals output from the outside, and the clock signals of the connected board cards can have the same source and the same frequency; the method adopts an MMCX standard shielding cable and outputs through 4 MMCX-J-P-H-ST-TH1 standard MMCX radio frequency output interfaces. The MMCX socket is small in size, the transmission frequency can reach 3GHz, and the frequency requirement of 125MHz is met. The shielding cable greatly reduces the interference of external signals and ensures the stability of the signals.

The clock signal buffer driver adopting ADCLK948BCPZ as 8-path output has the following advantages:

1. the highest working frequency is 4.8GHz, and the requirement of a system clock on 125MHz is met;

2. the jitter is extremely low, only 75 femtoseconds are needed, and the jitter is far superior to that of a common picosecond device;

3. up to 8 paths of output, and the clock requirement used by the system is met;

4. the signals are input in a differential mode and output in a differential mode, and compared with the common single-ended output signals, the anti-interference capacity of the signals is greatly improved.

The data communication module is used for outputting and/or inputting Low Voltage Differential Signaling (LVDS) signals and communicating with a quantum computer of the ion trap through an external interface board card. The data communication module comprises a plurality of groups of I2C interface circuits. In this embodiment, the LVDS signals output by the FPGA chip module are connected to N2530-6002RB ports with a 2.54mm pitch, which are 12 high-speed 30 pins, and then connected to the daughter boards through a 30-core high-speed cable. Differential signal wiring from the FPGA to the socket strictly meets the requirements of LVDS signals, a 100-ohm differential impedance design is used, signal quality is guaranteed, and data signals with the frequency of 125MHz can pass through the circuit in high quality. In addition, in addition to transmitting high-speed data signals, the port simultaneously outputs an I2C standard interface signal, a 12V power supply, and a 3.3V power supply to each daughter board.

Specifically, each I2C interface circuit of group is connected with corresponding electrostatic protection circuit respectively alone, and its TVS that adopts the model to be PRTR5VOU2X prevents electrostatic protection, can effectively prevent the injury of static to the chip.

The working principle is as follows:

the host computer can issue various instructions to the circuit board through the optical fiber communication module at any time, configure various working parameters, and simultaneously read various working parameters of the circuit at any time. In detail, the upper computer exchanges data with the optical fiber communication module through a gigabit Ethernet; the other end of the optical fiber communication module is connected with the FPGA chip module through an SFP standard communication interface; the optical fiber communication module performs mutual conversion on gigabit Ethernet signal SFP signals, and the FPGA chip module and the upper computer complete data exchange.

The FPGA chip module outputs and inputs LVDS high-speed serial signals through a built-in high-speed serial signal pin, and the multi-channel LVDS signals are converted into external interface board cards through the data communication module, so that the communication between the FPGA chip and the external interface board cards is realized.

The other end of the external interface board card is connected to a quantum computer of the ion trap. The interface board card can obtain various output signals of the quantum computer of the ion trap, converts the output signals into data, and transmits the data to the FPGA chip module through the data communication module. After receiving the input data, the FPGA chip module performs operation according to the set parameters, and the operation result can be output to a corresponding interface board card or an upper computer. The FPGA chip module can transmit data to each interface board card through the data communication module, and the interface board cards are converted into signals meeting the requirements of the quantum computer of the ion trap and output the signals to the quantum computer of the ion trap, so that the control of the quantum computer of the ion trap is realized.

To sum up, the multi-channel high-speed low-delay control board of the quantum computer of the present application realizes multi-channel, parallel processing of 12 slots, high-speed data communication channel of 8 × 125mhz per slot, and microsecond level low-delay control, and effectively solves the problem that the conventional method cannot meet the above requirements of the quantum computer of the ion trap; the ion trap quantum computer can be directly controlled by an upper computer, an independently controlled module is not needed, and the operation mode of the ion trap quantum computer is simplified.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims (10)

1. A multi-channel high-speed low-delay control board for a quantum computer, comprising: the system comprises an FPGA chip module, a precision clock module, an optical fiber communication module and a data communication module;

the FPGA chip module is respectively and independently linked with the precision clock module, the optical fiber communication module and the data communication module; the optical fiber communication module is used for being connected with an upper computer;

the precision clock module is used for generating a high-precision clock signal of 125 MHz;

the optical fiber communication module is used for performing interconversion between optical fiber signals and electric signals;

the FPGA chip module is used for carrying out low-delay processing on the electric signal data;

the data communication module is used for outputting and/or inputting low-voltage differential signals and communicating with the quantum computer through an external interface board card.

2. The multi-channel high-speed low-delay control board of the quantum computer as claimed in claim 1, further comprising a configuration module;

the configuration module is connected with the FPGA chip module, and the configuration module is connected with a peripheral configuration device and used for controlling each configuration pin of the FPGA.

3. The multi-channel high-speed low-delay control board of the quantum computer as claimed in claim 1 or 2, further comprising a storage module;

the storage module is connected with the FPGA chip module;

the storage module comprises a FLASH memory circuit and a DDR memory circuit which are respectively connected with a FLASH memory and a DDR memory.

4. The multi-channel high-speed low-delay control board of the quantum computer of claim 3, characterized in that:

the DDR memory adopts a model number MT41K256M16TW-107: p memory chips.

5. The multi-channel high-speed low-delay control board of the quantum computer of claim 3, characterized in that:

the optical fiber communication module comprises an optical fiber signal circuit and a plurality of groups of optical fiber interface circuits;

the precise clock module is connected with the optical fiber signal circuit;

and each group of the optical fiber interface circuits are respectively and independently connected with the optical fiber signal circuit.

6. The multi-channel high-speed low-delay control board of the quantum computer of claim 5, characterized in that:

the precise clock module comprises a clock crystal oscillator circuit;

the clock crystal oscillator circuit comprises a clock crystal oscillator chip; the clock crystal oscillator chip adopts a chip with the model number of 549CBAC000112 ABG.

7. The multi-channel high-speed low-delay control board of the quantum computer of claim 6, characterized in that:

the precision clock module also comprises a clock signal driving circuit;

the clock signal driving circuit comprises a clock signal buffer driver and a plurality of radio frequency output interfaces;

the clock signal buffer driver adopts a chip with the model number ADCLK948 BCPZ.

8. The multi-channel high-speed low-delay control board of the quantum computer of claim 7, characterized in that:

the data communication module comprises a plurality of groups of I2C interface circuits; and each group of I2C interface circuits are respectively and independently connected with corresponding electrostatic protection circuits.

9. The multi-channel high-speed low-delay control board of the quantum computer according to any one of claims 5 to 8, characterized in that:

the FPGA chip module comprises an FPGA chip with the model of XC7A100T-3FGG 484E.

10. The multi-channel high-speed low-delay control board of the quantum computer of claim 9, characterized in that: the power supply module comprises a power supply input circuit and a power supply conversion circuit;

the power input circuit comprises a common-mode inductor, a filter capacitor and a voltage stabilizing diode;

and each output end of the power supply conversion circuit is provided with a filter.

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