CN217740981U

CN217740981U - Human eye safe long wavelength VCSEL array chip for laser radar

Info

Publication number: CN217740981U
Application number: CN202222207079.8U
Authority: CN
Inventors: 鄢静舟; 薛婷; 季晓明; 柯程; 杨奕; 吴建忠
Original assignee: Fujian Huixin Laser Technology Co ltd
Current assignee: Fujian Huixin Laser Technology Co ltd
Priority date: 2022-08-22
Filing date: 2022-08-22
Publication date: 2022-11-04
Anticipated expiration: 2032-08-22

Abstract

The utility model discloses an eye safety long wavelength VCSEL array chip for laser radar, which relates to the technical field of semiconductor photoelectron, and comprises a radiating fin and a plurality of VCSELs which are arranged and bonded above the radiating fin, wherein each VCSEL comprises a dielectric layer DBR, a second N-type doped DBR, a second buried tunneling junction, a multi-junction cascade active region, a first N-type doped DBR, an InP second buffer layer and a grating layer from bottom to top in sequence; and solder for connecting the radiating fins is filled between the dielectric layer DBRs of two adjacent VCSELs. The utility model discloses utilize the combination speculum of dielectric layer DBR + first N type doping DBR and grating layer + second N type doping DBR to replace the single semiconductor DBR speculum in traditional VCSEL, reduced VCSEL's light, the electrical loss on the one hand from this, the series resistance has been reduced, VCSEL's electro-optical conversion efficiency has been improved, on the other hand has improved the heat-sinking capability and the high temperature working property of VCSEL chip, and reduced the preparation degree of difficulty of device, accord with the characteristic demand of laser radar to long wavelength VCSEL.

Description

Human eye safe long wavelength VCSEL array chip for laser radar

Technical Field

The utility model relates to a semiconductor optoelectronic technology field, in particular to human eye safety long wavelength VCSEL array chip for laser radar.

Background

At present, a multi-junction 905nm Edge Emitting Laser (EEL) and a multi-junction Vertical Cavity Surface Emitting Laser (VCSEL) are mainly adopted as a laser radar light source, and the VCSEL has the unique advantages of stable wavelength, suitability for large-scale production, lower price and better reliability compared with the EEL, no cavity surface damage, capability of being rapidly modulated, surface array light emitting, round uniform symmetrical light spots and the like, so that a high-power 905/940nm VCSEL array chip is favored by a laser radar system. However, the laser power required by the vehicle-mounted lidar is up to tens of watts or even hundreds of watts level to ensure a sufficiently long detection distance, which causes a great eye safety problem for the 905/940nm laser used for the vehicle-mounted lidar.

Human eyes have different transmittances and absorption characteristics to light radiation with different frequencies, and visible light waves with the wavelength of 400-700 nm can penetrate through irises, crystalline lenses and vitreous bodies of eyeballs to damage retina; the near infrared band with the wavelength of 750nm-1400nm can cause cataract and retina damage; however, laser light with wavelengths below 400nm and above 1400nm has a high damage threshold to the human eye and is almost absorbed by the crystalline lens, and therefore, generally does not cause damage to the inside of the eyeball. Lasers in the 1500-1800nm and 2000-2400nm bands are therefore generally referred to as eye-safe lasers. There is data showing that 1550nm laser of equal power possesses more than 10 ten thousand times eye safety compared to 905nm laser! Meanwhile, in consideration of the transmission factor of light waves in the atmosphere, 1500nm laser is just positioned in an 'atmospheric window', and has excellent performances such as strong smoke penetration capacity and high target reflectivity, so 1550nm is generally accepted as the optimal wavelength of a laser radar light source at present.

At present, almost all laser radar manufacturers adopting 1550nm schemes adopt 1550nm fiber lasers, mainly because 1550nm laser sources which can provide enough power, have good beam quality and small divergence angles are available in the market, but the fiber lasers are extremely expensive and heavy, which greatly limits the application and popularization of 1550nm laser radars safe to human eyes. Similar to multi-junction 905/940nm VCSEL array chip, the 1550nm multi-junction VCSEL array chip can replace 1550nm fiber laser to become the most mainstream laser light source of the laser radar with the advantages of high performance, low cost, small size, suitability for mass production and the like, and is a necessary technical path for the laser radar and the automatic driving practicability.

However, the difficulty in the prior art is that 1550nm VCSEL are based on InP substrate, there is no suitable lattice constant matching compound semiconductor material with large refractive index difference to design DBR mirrors necessary for VCSEL, and there is no material similar to AlAs which is used in GaAs substrate system to form an oxide aperture to improve optical and electrical properties of VCSEL, so 1550nm VCSEL has not become mainstream in the industry, and there is no mature product for optical communication, and even no 1550nm VCSEL array chip is used in lidar.

The conventional VCSEL structure usually adopts a "sandwich" design, and the DBR mirrors at the top and bottom and the active region form a resonant cavity of the laser. The DBR reflector of the VCSEL with the long wavelength of 1550nm grown on the basis of the InP substrate generally adopts InP/InAlGaAs interactive periodic stacking, and if the reflectivity is to reach 99%, the thickness of the DBR reflector needs to reach 8 mu m. However, the larger the thickness of the DBR mirror is, the larger the light absorption is, which easily causes the problems of high threshold current and large insertion loss, and also causes a chip to have a very large series resistance, and the heat dissipation of the chip is poor. And the larger the thickness of the DBR reflector is, the more the number of the film layers of InP/InAlGaAs is, which causes the difficulty in manufacturing the device to be high and the production to be difficult.

In addition, the price of 3-inch InP substrates on the market today is $ 600 and $ 800-900 for 4-inch InP substrates, which is seen to be very expensive, further limiting the development and popularity of long wavelength VCSELs.

In summary, the long wavelength VCSEL with the traditional structure cannot meet the high power requirement of the laser radar application end on the VCSEL chip, and has the problems of high manufacturing difficulty, high production cost and the like.

Disclosure of Invention

The utility model provides a safe long wavelength VCSEL array chip of people's eye for laser radar, the problem that its main aim at solved prior art existence.

The utility model adopts the following technical scheme:

an eye-safe long-wavelength VCSEL array chip for a laser radar comprises a radiating fin and a plurality of VCSELs which are arranged and bonded above the radiating fin, wherein each VCSEL sequentially comprises a dielectric layer DBR, a second N-type doped DBR, a second buried tunneling junction, a multi-junction cascade active region, a first N-type doped DBR, an InP second buffer layer and a grating layer from bottom to top; and solder for connecting the radiating fins is filled between the medium layer DBRs of two adjacent VCSELs.

Further, the dielectric layer DBR is made of SiO ₂ /Si ₃ N ₄ The period of the reflector is 4-8, and the thickness is 1800-3750nm.

Furthermore, the high refractive index material of the grating layer is SiO ₂ Or Si ₃ N ₄ The low refractive index material is air or an oxide.

Furthermore, the grating period of the grating layer is 550nm < lambda < 800nm, the filling coefficient is 350nm < eta < 500nm, and the grating depth is 350nm < tg < 500nm.

Further, the first N-type doped DBR and the second N-type doped DBR are mirrors formed by InAlGaAs/InP or InGaAsP/InP periodic stacking; the number of the periods of the first N-type doped DBR and the second N-type doped DBR is 5-20, and the thickness is 1000-5000nm.

Furthermore, the heat radiating fin is a silicon wafer, and the thickness of the heat radiating fin is 300-700 mu m.

Further, the multi-junction cascade active region comprises n active regions, and the active regions are cascaded through a first tunneling junction; each active region comprises a limiting layer, a waveguide layer, a quantum well layer, a symmetrical waveguide layer and a symmetrical limiting layer from bottom to top.

Further, the well layer/barrier layer of the quantum well layer is In _x Ga _1-x As _y P _1-y /In _x Ga _1-x As _y P _1-y Or AlInGaAs of different Ga/Al ratios.

Furthermore, contact electrodes are arranged above the second N-type doped DBR and the InP second buffer layer.

Further, the lasing wavelength range of each VCSEL is 1200-1800nm.

Compared with the prior art, the utility model discloses the beneficial effect who produces lies in:

1. the utility model discloses a design concept of combination speculum, the combination speculum that utilizes dielectric layer DBR + first N type to dope DBR and grating layer + second N type to dope the DBR replaces among the traditional VCSEL rete figure many, inP/InAlGaAs's that thickness is big single DBR speculum, effectively reduced VCSEL's light from this aspect, the electrical loss, the series resistance has been reduced, VCSEL's electricity has been improved, the light conversion efficiency, on the other hand improves VCSEL chip's heat-sinking capability greatly, improve chip high temperature working property, and the preparation degree of difficulty of device has been reduced, accord with laser radar to long wavelength VCSEL's characteristic demand.

2. The utility model discloses an active area in piling up the cavity increases the gain volume, improves VCSEL's output from this for VCSEL array chip accords with 1550nm laser radar's high power demand.

3. The utility model discloses a substrate strip technique peels off the required InP substrate of long wavelength VCSEL to adopt the silicon chip that the heat conductivility is good or other good material of thermal diffusivity/substrate to replace the InP substrate as the fin, thereby play heat dissipation and physics supporting role, set up the combination speculum and provide necessary technical support for both ends about the VCSEL. The stripped expensive InP substrate can be reused many times, maximizing the reduction in the production cost of long wavelength VCSELs.

Drawings

Fig. 1 is a schematic structural diagram of a VCSEL array chip in the present invention.

Fig. 2 is a schematic structural diagram of a single VCSEL in the present invention.

Fig. 3 is a schematic diagram of the layered structure of the multi-junction cascaded active region of the present invention.

Fig. 4 is a schematic diagram of the layer structure of the nth active region of the multi-junction cascaded active region of the present invention.

Fig. 5 is a schematic structural diagram of the grating layer in the present invention.

Fig. 6 is a schematic view of the epitaxial structure of the VCSEL before the substrate is peeled off in the present invention.

Fig. 7 is a schematic diagram illustrating a first process for manufacturing a VCSEL array chip according to the present invention.

Fig. 8 is a schematic diagram of a second process for manufacturing the VCSEL array chip of the present invention.

Fig. 9 is a third schematic view of the process for manufacturing the VCSEL array chip of the present invention.

In the figure:

10. an InP substrate; 11. An InP first buffer layer;

12. a superlattice sacrificial layer; 13. An InP second buffer layer;

14. a first N-type doped DBR; 15. A multi-junction cascaded active region;

16. a second N-type doped DBR; 17. A medium layer DBR;

18. a second buried tunnel junction; 19. A grating layer;

110/111, contact electrode; 112. Welding flux;

113. a heat sink; 21. A first active region;

22. a first tunneling junction; 23. A second active region;

24. an nth active region; 241. A confinement layer;

244. a symmetric waveguide layer; 245. A symmetric confinement layer.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

As shown in fig. 1 and fig. 2, the embodiment provides a 1550nm VCSEL array chip for lidar, which includes a heat sink 113 and a plurality of VCSELs arranged and bonded above the heat sink 113, wherein each VCSEL sequentially includes, from bottom to top, a first combined mirror, a second N-type doped DBR16, a second buried tunneling junction 18, a multi-junction cascaded active region 15, a first N-type doped DBR14, an InP second buffer layer 13, and a second combined mirror. The first combined reflecting mirror and the second combined reflecting mirror can be any one of a dielectric layer DBR and a grating layer. The first combined mirror in this embodiment is preferably a dielectric layer DBR17 and the second combined mirror is preferably a grating layer 19. And the solder 112 for connecting the radiating fins is filled between the dielectric layer DBRs 17 of the two adjacent VCSELs. A contact electrode 111 is disposed above the second N-type doped DBR16, and a contact electrode 110 is also disposed above the inp second buffer layer 13.

As shown in fig. 1, fig. 2 and fig. 5, the epitaxial structure parameters of each VCSEL in the present embodiment are as follows:

the heat sink 113 is made of silicon wafer with good thermal conductivity or other materials or substrates with good heat dissipation properties, and has a thickness of 300-700 μm. The heat sink 113 not only facilitates heat dissipation of the chip, but also provides physical support.

The DBR17 is made of SiO ₂ /Si ₃ N ₄ Periodic stackThe number of cycles of the stacked reflector is 4-8, and the thickness of the stacked reflector is 1800-3750nm.

The first N-type doped DBR14 and the second N-type doped DBR16 are mirrors comprised of inalgas/InP or InGaAsP/InP periodic stacks. The first N-doped DBR14 and the second N-doped DBR16 of this embodiment provide sufficient physical support and provide partial reflectivity to ensure a reliable and stable mirror assembly of the epitaxial layers. The first N-type doped DBR14 and the second N-type doped DBR16 have the cycle number of 5-20 and the thickness of 1000-5000nm. When the reflectivity of the traditional 1550nm VCSEL InP/InAlGaAs DBR reflector is 99%, the thickness of a semiconductor DBR reaches 8 mu m; the first N-type semiconductor doping DBR (5-10 cycles) and the dielectric layer DBR reflecting unit are adopted to achieve the same reflectivity, and the thickness of the semiconductor DBR is only 1-2.5 mu m; the same reflectivity is achieved by doping the DBR (5-20 cycles) + HCG reflective element with a second N-type semiconductor, the thickness of the semiconductor DBR being only 1-5 μm. Therefore, the thickness of the DBR reflector can be effectively reduced by adopting the combined reflector of the dielectric layer DBR17+ the first N-type doped DBR14 and the grating layer 19+ the second N-type doped DBR16, so that the problems in the prior art are effectively solved.

The thickness of the InP second buffer layer 13 is 500-1000nm, the doping atom is Si, and the doping concentration is more than 10 ¹⁸ cm ^-3 . Since the VCSEL array chip provided in this embodiment needs to be manufactured by a substrate lift-off process, the InP second buffer layer 13 may be disposed to ensure the crystal quality.

The grating layer 19 is preferably a high index contrast subwavelength grating of the type formed by subwavelength stripes of a high index material surrounded by a low index medium, wherein the high index material is SiO ₂ Or Si ₃ N ₄ The low refractive index material can be air or oxide, and the grating period is 550nm<∧<800nm, fill factor 350nm<η<500nm, grating depth 350nm<tg<500nm。

The relevant design parameters of the epitaxial structure of each VCSEL are referenced in table 1.

TABLE 1VCSEL epitaxial Structure parameter Table

As shown in fig. 3 and 4, the multi-junction cascaded active region 15 adopts a mode of alternately cascading n active regions and a first tunneling junction 22, and includes, from bottom to top, a first active region 21, a first tunneling junction 22, a second active region 23, a first tunneling junction 22 \8230: \ 8230and an nth active region 24. For each active region, from bottom to top, there are a confinement layer 241, a waveguide layer 242, a quantum well layer 243, a symmetric waveguide layer 244, and a symmetric confinement layer 245. A quantum well layer in the Nth active region 24 is located at a standing wave antinode in a resonant cavity, and the first tunneling junction 22 is located at a standing wave trough in the resonant cavity. The well layer/barrier layer of the quantum well layer 243 is In _x Ga _1-x As _y P _1-y /In _x Ga _1-x AsyP _1-y Or AlInGaAs of different Ga/Al ratios.

The first tunnel junction 22 and the second buried tunnel junction 18 include a P-type heavily doped layer and an N-type heavily doped layer from bottom to top. The P-type heavily doped layer material can be, but is not limited to, inGaAsP, inGaAlAs, alInAs, inP, and the N-type heavily doped layer material can be, but is not limited to, gaInAs, inP, inGaAsP, inGaAlAs, alInAs; the thickness range of the P-type heavily doped layer is 8-50nm, and the thickness range of the N-type heavily doped layer is 10-50nm; the doping atoms of the P-type heavily doped layer can Be but not limited to C, mg, zn and Be, and the doping atoms of the N-type heavily doped layer can Be but not limited to Te, se, si and S; the doping concentration of the P-type heavily doped layer and the N-type heavily doped layer is 10 ¹⁹ -10 ²⁰ cm ^-3 An order of magnitude; the second buried tunnel junction 18 has an aperture in the range of 4-50 μm.

The design parameters of the multijunction cascaded active region 15 are referenced in table 2.

TABLE 2 parameter table for multijunction cascaded active regions

In this embodiment, the long wavelength VCSEL array chip for lidar is fabricated by a substrate lift-off technique, and in order to illustrate the fabrication method more clearly, the VCSEL epitaxial structure before lift-off is described in detail below:

as shown in fig. 6, the epitaxial structure of the VCSEL before lift-off includes, from bottom to top, an InP substrate 10, an InP first buffer layer 11, a superlattice sacrificial layer 12, an InP second buffer layer 13, a first N-doped DBR14, a multi-junction cascaded active region 15, a second buried tunnel junction 18, a second N-doped DBR16, and a dielectric layer DBR 17.

The thickness of the InP substrate 10 is 300-700 μm, and the thickness of the epitaxial structure above the InP substrate 10 is 6-20 μm. By the aid of the substrate stripping process, cyclic utilization of the InP substrate 10 can be achieved, manufacturing cost of enterprises is greatly reduced, and necessary technical support is provided for preparation of VCSELs with combined reflectors at two ends.

The superlattice sacrificial layer 12 is of an AlAs/InAlAs/AlAs/InAlAs/AlAs superlattice structure, wherein the thickness of AlAs is 1.5-2.1nm, and the thickness of InAlAs is 1nm. The choice and thickness of the sacrificial layer composition is critical in the ELO process, with thicker layers leading to slower etch rates, and too thin layers (typically less than 5 nm) leading to a sudden etch stop, and studies have shown that reasonable thickness of the sacrificial layer should be controlled in the range of 5-10 nm. In the prior art, the ELO process based on the InP substrate usually uses AlAs as the sacrificial layer, but the lattice mismatch between AlAs material and InP material is as high as 3.6%. In the InP substrate peeling test using AlAs as a sacrificial layer, which has been carried out, the use of AlAs having a thickness exceeding 5nm causes the sacrificial layer to relax, causing crystal defects, thereby affecting the device performance. In order to overcome the thickness limitation of the AlAs layer, the present embodiment uses AlAs/InAlAs/AlAs superlattice instead of AlAs as the sacrificial layer, although there is a high degree of lattice mismatch between AlAs and InP, the AlAs/InAlAs/AlAs/InAlAs superlattice structure can be regarded as a single layer, exhibiting an effective average composition constituting the superlattice, and a thicker sacrificial layer can be deposited, and maintaining good material crystal quality. Therefore, the adoption of the AlAs/InAlAs/AlAs/InAlAs/AlAs superlattice structure can realize the stripping and recycling of the InP substrate while ensuring the quality of the thin film of the device, thereby reducing the production cost of enterprises.

The following description is directed to a method for manufacturing the long wavelength VCSEL array chip for lidar, which includes the steps of:

(1) An epitaxial layer is grown on an InP substrate 10, the epitaxial layer comprises an InP first buffer layer 11, a superlattice sacrificial layer 12, an InP second buffer layer 13, a first N-type doped DBR14, a multi-junction cascade active region 15, a tunneling junction layer and a second N-type doped DBR16, and the tunneling junction layer is etched with a plurality of second buried tunneling junctions 18 which are arranged at intervals. Specifically, firstly, depositing an InP first buffer layer 11, a superlattice sacrificial layer 12, an InP second buffer layer 13, a first N-type doped DBR14, a multi-junction cascaded active region 15, and a tunnel junction layer on an InP substrate 10 in sequence by using an MOCVD process; the aperture of the VCSEL is then defined by masking and etching to form the mesa of the tunnel junction, then the tunnel junction 18 is second buried by second epitaxy and a second N-doped DBR16 is grown, as shown in fig. 6 and 7 (a).

(2) A plurality of first mirrors corresponding to the second buried tunnel junctions 18 are formed on the surface of the epitaxial layer. The first reflector is preferably a dielectric layer DBR17, and the manufacturing method comprises the following steps: depositing a dielectric layer DBR17 on the surface of the second N-type doped DBR16 by adopting a PECVD process, as shown in FIG. 7 (b); the dielectric layer DBR17 is etched using photolithography, chemical solution etching, to be aligned with the second buried tunnel junction 18, as shown in fig. 7 (c).

(3) A one-piece heat spreader 113 is bonded over the epitaxial layers. Specifically, solder is filled in the gap between two adjacent dielectric layers DBR17, and a one-piece heat sink 113 is bonded above the dielectric layers DBR17, as shown in fig. 7 (d). In practical applications, a one-piece heat sink may be mounted on the epitaxial layer by direct bonding or adhesive bonding.

(4) Etching the superlattice sacrificial layer 12 by using an HF solution, thereby peeling the InP substrate 10 from the bottom of the epitaxial layer; specifically, the HF solution selectively etches the epitaxial layer to separate the superlattice sacrificial layer from the InP substrate 10, thereby peeling the entire epitaxial layer off the InP substrate 10, as shown in fig. 8 (e) and (f).

(5) Inverting the epitaxial layer, which is now structured as shown in FIG. 8 (g), a second mirror is fabricated on the surface of InP second buffer layer 13, and mesa etching and contact electrode fabrication are performed on the epitaxial stack to form a stripA VCSEL chip having a grid array pattern. In this embodiment, the second reflecting mirror is preferably a grating layer, and the manufacturing method thereof is: firstly, a PECVD process is adopted to deposit a plurality of SiO arranged at intervals on the surface of the InP second buffer layer 13 ₂ Layer or Si ₃ N ₄ Layer of SiO ₂ Layer or Si ₃ N ₄ The gap of the layer corresponds to the gap between two adjacent second buried tunnel junctions 18, as shown in fig. 9 (h); then, mesa etching and contact electrode manufacturing are carried out on the epitaxial layer, so that a VCSEL chip with a grid array pattern is formed, as shown in FIG. 9 (i); finally, the grating layer 19 is formed by photolithography and etching with a chemical solution or local oxidation, as shown in fig. 9 (j).

The above description is only for the specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. All utilize the utility model discloses a design concept is right the utility model discloses carry out immaterial change, all should belong to the infringement the utility model discloses the action of scope.

Claims

1. An eye-safe long wavelength VCSEL array chip for a lidar, characterized by: the LED light source comprises a radiating fin and a plurality of VCSELs which are arranged and bonded above the radiating fin, wherein each VCSEL sequentially comprises a dielectric layer DBR, a second N-type doped DBR, a second buried tunneling junction, a multi-junction cascade active region, a first N-type doped DBR, an InP second buffer layer and a grating layer from bottom to top; and solder for connecting the radiating fins is filled between the medium layer DBRs of two adjacent VCSELs.

2. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the DBR of the medium layer is made of SiO ₂ /Si ₃ N ₄ The periodic stack is composed of mirrors with period number of 4-8 and thickness of 1800-3750nm.

3. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the high-refractive-index material of the grating layer is SiO ₂ Or Si ₃ N ₄ The low refractive index material is air or an oxide.

4. An eye-safe long wavelength VCSEL array chip for lidar according to claim 2, wherein: the grating period 550nm of the grating layer is less than ^ 800nm, the filling coefficient 350nm is less than eta and less than 500nm, and the grating depth 350nm is less than tg and less than 500nm.

5. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the first N-type doping DBR and the second N-type doping DBR are both mirrors formed by InAlGaAs/InP or InGaAsP/InP periodic stacking; the number of the periods of the first N-type doped DBR and the second N-type doped DBR is 5-20, and the thickness is 1000-5000nm.

6. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the radiating fin is a silicon wafer, and the thickness of the radiating fin is 300-700 mu m.

7. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the multi-junction cascade active region comprises n active regions, and cascade connection is carried out between the active regions through a first tunneling junction; each active region comprises a limiting layer, a waveguide layer, a quantum well layer, a symmetrical waveguide layer and a symmetrical limiting layer from bottom to top.

8. An eye-safe long wavelength VCSEL array chip for lidar according to claim 7, wherein: the well layer/barrier layer of the quantum well layer is In _x Ga _1-x As _y P _1-y /In _x Ga _1-x As _y P _1-y Or AlInGaAs of different Ga/Al ratios.

9. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: and contact electrodes are arranged above the second N-type doped DBR and the InP second buffer layer.

10. An eye-safe long wavelength VCSEL array chip for lidar according to claim 1, wherein: the lasing wavelength range of each VCSEL is 1200-1800nm.