CN217590847U

CN217590847U - Intelligent protocol converter

Info

Publication number: CN217590847U
Application number: CN202221806662.4U
Authority: CN
Inventors: 张毅; 靳文佳; 杨杰
Original assignee: Chengdu Qianxin Technology Co ltd
Current assignee: Chengdu Qianxin Technology Co ltd
Priority date: 2022-07-13
Filing date: 2022-07-13
Publication date: 2022-10-14
Anticipated expiration: 2032-07-13

Abstract

The utility model discloses an intelligent protocol converter, which belongs to the technical field of communication of the Internet of things and comprises a processor module, a 1533B bus interface module, a CAN bus interface module, an Ethernet port module and an RS232 interface module; processor module is connected with 1533B bus interface module, CAN bus interface module, ethernet net gape module and RS232 interface module respectively, the utility model provides a be difficult to realize efficient multiprotocol conversion and the interconnected problem of many networks, reduced the complexity and the cost that the network realized, and improved protocol conversion's real-time.

Description

Intelligent protocol converter

Technical Field

The utility model belongs to the technical field of the thing communication network, especially, relate to an intelligent protocol converter.

Background

Most of the existing protocol conversion devices are mainly used for one-to-one protocol conversion, wherein an ARM (advanced RISC machine), a DSP (digital signal processor) and a Pentium series processor are adopted as control processors for protocol conversion. The protocol processor receives information of a certain type of bus through a hardware interface, extracts a data segment through unpacking processing, packs the data segment according to a protocol format of a target bus and sends the data segment out, but the conversion mode is very complicated to realize and has higher cost in a protocol conversion environment related to various buses;

the existing multi-protocol conversion system converts all protocol formats into an Ethernet protocol, constructs a local area network through the Ethernet, and realizes the interconnection of all buses by utilizing Ethernet routing addressing, the scheme is simple, but each subsystem needs to convert the protocol format into the Ethernet, a large amount of protocol conversion equipment is needed, the cost is overhigh, and the Ethernet as an interconnection medium influences the real-time performance on the transmission between a CAN bus and a 1553B bus; therefore, an efficient intelligent protocol converter capable of implementing multi-bus protocol conversion is necessary.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned not enough among the prior art, the utility model provides a pair of intelligent protocol converter has solved the problem that is difficult to realize efficient multiprotocol conversion and many networks interconnection.

In order to achieve the purpose of the invention, the utility model adopts the technical scheme that:

the utility model provides an intelligent protocol converter, which comprises a processor module, a 1533B bus interface module, a CAN bus interface module, an Ethernet port module and an RS232 interface module;

the processor module is respectively connected with the 1533B bus interface module, the CAN bus interface module, the Ethernet port module and the RS232 interface module.

The beneficial effects of the utility model are that: the utility model provides a pair of intelligence protocol converter, respectively through 1533B bus interface module, CAN bus interface module, ethernet net gape module and RS232 interface module provide 15533B bus interface, CAN bus interface, ethernet net gape and RS232 interface, and according to 1533B bus interface's realization interface logic circuit, and realize the transmission of control 1533B information through processor module, CAN realize 1533B and CAN bus through protocol conversion chip U1 and processor module, ethernet and RS 232's bus communication and protocol conversion.

Further, the processor module adopts a processor chip U1 with the model number of AT91SAM 9261;

pins A0 to A11, pins D0 to D15, pins PC0, pins CS0, pins A13, pins PC14 and pins PC15 of the processor chip U1 are all connected with a 1522B bus module; the CANTX pin and the CANRX pin of the processor chip U1 are both connected with the CAN bus interface module; an MDIO pin, an MDC pin, an ENTTX0 pin, an ENTRX0 pin, an ENTTX1 pin, an ENTRX1 pin, an ENTTXEN pin, an ENTRER pin, a CRS pin and an ENTTXCLK pin of the processor chip U1 are all connected with the Ethernet port module; and the 232TX pin and the 232RX pin of the processor chip U2 are both connected with the RS232 interface module.

The beneficial effect of adopting the further scheme is as follows: the CAN bus, the Ethernet and the RS232 bus are communicated and accessed through the processor module, and the access information transmission and the 1553B bus are controlled to realize the co-conversion.

Further, the 1533B BUS interface module includes a protocol chip U2 of a BUS-61560 type, a capacitor C1, a resistor R1, a triode Q1, and a triode Q2;

pins A0 to A11 of the processor chip U1 are connected with pins A0 to A11 of the protocol chip U2 in a one-to-one correspondence manner; the pins D0 to D15 of the processor chip U1 are correspondingly connected with the pins D0 to D15 of the protocol chip U2 one by one; the PC0 pin of the processor chip U1 is respectively connected with the DIR pin and the RD/WR pin of the protocol chip U2; a CS0 pin of the processor chip U1 is respectively connected with a SELECT pin and a STRBD pin of the protocol chip U2; the A13 pin of the processor chip U1 is connected with the MEM/REG pin of the protocol chip U2; the INT pin of the protocol chip U2 is respectively connected with the emitting electrode of the triode Q1 of the PC14 pin of the processor chip U1; the collector of the triode Q1 is connected with the collector of the triode Q2 and is grounded; the base electrode of the triode Q1 is connected with the base electrode of the triode Q2 and is externally connected with a +3.3V power supply; the READY pin of the protocol chip U2 is respectively connected with the PC15 pin of the processor chip U1 and the emitting electrode of the triode Q2; the MSTCLR pin of the protocol chip U2 is respectively connected with one end of the resistor R1 and one end of the capacitor C1; the other end of the resistor R1 is externally connected with a +5V power supply; the other end of the capacitor C1 is grounded; the TRANSPARENT pin, the TAG _ CLK pin, the POLARITY _ SEL pin, the 16/8 pin, the SSFLAG pin, the ADDR _ LAT pin and the ZERO _ WAIT pin of the protocol chip U2 are all grounded.

The beneficial effect of adopting the further scheme is as follows: the protocol chip U2 is provided, two transceiver components, a protocol logic component, a memory management component, an interrupt control component, a processor interface logic component and an RAM are integrated in the protocol chip U2, and the protocol chip U2 is compatible with the processor chip U1, can realize communication of a transmission layer, a data link layer and a physical layer, simplifies the complexity of an interface circuit and improves the real-time property.

Further, the CAN bus interface module includes an isolation chip U3 with a model of admum 1201, a CAN level conversion chip U4 with a model of AMIS42675, a capacitor C2, an inductor L1, a diode D2, a resistor R2, a ground resistor R3, a resistor R4, a resistor R5, a resistor R6, and a CAN transceiver J1;

the 1 st pin of the isolation chip U3 is externally connected with a +3.3V power supply; the No. 2 pin and the No. 3 pin of the isolation chip U3 are respectively connected with the CANTX pin and the CANRX pin of the processor chip U1 in a one-to-one correspondence manner; the 4 th pin and the 5 th pin of the isolation chip U3 are grounded; the 6 th pin of the isolation chip U3 is connected with the 4 th pin of the CAN level conversion chip U4; the 7 th pin of the isolation chip U3 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with one end of the resistor R2; the other end of the resistor R2 is externally connected with a +5V power supply; the 8 th pin of the isolation chip U3 is connected with the 1 st pin of the CAN level conversion chip U4 and is externally connected with a +5V power supply; a No. 2 pin of the CAN level conversion chip U4 is connected with one end of the capacitor C2 and is grounded; the No. 3 pin of the CAN level conversion chip U4 is connected with the other end of the capacitor C2 and is grounded; a 6 th pin and a 7 th pin of the CAN level conversion chip U4 are both connected with one end of the inductor L2; the other end of the inductor L2 is connected with one end of the resistor R4 and one end of the resistor R5 respectively; the other end of the resistor R4 is connected with one end of the diode D2 and one end of the resistor R6 respectively; the other end of the resistor R5 is connected with the other end of the diode D2 and a No. 2 pin and a No. 3 pin of the CAN transceiver respectively; the other end of the resistor R6 is connected with a No. 1 pin of the CAN transceiver; and the 8 th pin of the CAN level conversion chip U4 is connected with the grounding resistor R3.

The beneficial effect of adopting the above further scheme is that: the CAN bus interface module is provided, message frames which CAN be transmitted by the CAN bus comprise data frames, remote frames, error frames and overload frames, the CAN bus interface module has extremely strong information transmission capability, and protocol conversion and information transmission between the CAN bus interface and the 1553B bus CAN be realized through the processor module.

Further, the ethernet port module includes an ethernet transceiving chip U5 of the type LAN8720A, an RJ45 chip U6 of the type HR11105A, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C3, a capacitor C8, a capacitor C9, and a capacitor C10;

a 12 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R8 and an MDIO pin of the processor chip U1; a13 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R7 and an MDC pin of the processor chip U1; the other end of the resistor R7 is connected with the other end of the resistor R8 and is externally connected with a +3.3V power supply; a 17 th pin and an8 th pin of the Ethernet transceiver chip U5 are respectively connected with an ENTTX0 pin and an ENTRX0 pin of the processor chip U1 in a one-to-one correspondence manner; the 18 th pin and the 7 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTX1 pin and the ENTRX1 pin of the processor chip U1 in a one-to-one correspondence manner; the 16 th pin and the 10 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTXEN pin and the ENTRXER pin of the processor chip U1 in a one-to-one correspondence manner; the 11 th pin of the Ethernet transceiver chip U5 is connected with a CRS pin of the processor chip U1; a 14 th pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R10; a 15 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R9 and one end of the capacitor C3; the other end of the resistor R9 is connected with the other end of the resistor R10 and is externally connected with a +3.3V power supply; the other end of the capacitor C3 is grounded; a 14 th pin of the Ethernet transceiving chip U5 is connected with one end of a resistor R15; the other end of the resistor R15 is grounded; a 21 st pin of the Ethernet transceiving chip U5 is respectively connected with one end of the resistor R11 and a1 st pin of the RJ45 chip U6; a 20 th pin of the Ethernet transceiving chip U5 is respectively connected with one end of the resistor R12 and a 2 nd pin of the RJ45 chip U6; a 23 rd pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R13 and a 3 rd pin of the RJ45 chip U6; a 22 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R14 and a 6 th pin of the RJ45 chip U6; the other end of the resistor R11 is respectively connected with the other end of the resistor R12, the other end of the resistor R13 and the other end of the resistor R14, and is externally connected with a positive 3.3V power supply; a 3 rd pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R16; a 2 nd pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R17; a 19 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C10 and is externally connected with a +3.3V power supply; the No. 1 pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C9 and is externally connected with a +3.3V power supply; a 9 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C8 and is externally connected with a +3.3V power supply; a 6 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of a capacitor C6 and one end of a capacitor C7; a 25 th pin of the ethernet transceiving chip U5 is connected to the other end of the capacitor C10, the other end of the capacitor C11, the other end of the capacitor C12, the other end of the capacitor C13, and the other end of the capacitor C14, respectively, and is grounded; the 5 th pin of the Ethernet transceiving chip U5 is connected with the ENTTXCLK pin of the processor chip U1; a 4 th pin of the RJ45 chip U6 is connected with one end of a capacitor C4; a 5 th pin of the RJ45 chip U6 is connected with one end of a capacitor C5; the other end of the capacitor C4 is connected with the other end of the capacitor C5 and is grounded; the 9 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; the 10 th pin of the RJ45 chip U6 is connected with the other end of the resistor R16; the 11 th pin of the RJ45 chip U6 is connected with the other end of the resistor R17; a 12 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; and the 10 th pin of the RJ45 chip U6 is respectively connected with the 14 th pin and the 8 th pin and is grounded.

The beneficial effect of adopting the further scheme is as follows: the Ethernet communication can be realized through the Ethernet port, and the protocol conversion and information transmission between the Ethernet port and the 1553B bus can be realized by utilizing the processor module.

Further, the RS232 interface module includes a 232 communication chip U7 with model number SP3232, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, and a 232 interface COM1;

the 1 st pin of the 232 communication chip U7 is connected with the 3 rd pin of the capacitor C10; the No. 3 pin of the 232 communication chip U7 is connected with the other end of the capacitor C10; the 2 nd pin of the 232 communication chip U7 is connected with one end of a capacitor C12; the 6 th pin of the 232 communication chip U7 is connected with one end of a capacitor C13; the other end of the capacitor C12 is connected with the other end of the capacitor C13 and is grounded; the 4 th pin of the 232 communication chip U7 is connected with one end of a capacitor C11; the 5 th pin of the 232 communication chip U7 is connected with the other end of the capacitor C11; the 11 th pin and the 12 th pin of the 232 communication chip U7 are respectively connected with the 232TX pin and the 232RX pin of the processor chip U1 in a one-to-one correspondence manner; the 13 th pin of the 232 communication chip U7 is connected with the 3 rd pin of the 232 interface COM1; the 14 th pin of the 232 communication chip U7 is connected with the 3 rd pin of the 232 interface COM1; the 15 th pin of the 232 communication chip U7 is grounded; a 16 th pin of the 232 communication chip U7 is externally connected with a +3.3V power supply; the 5 th pin of the 232 interface COM1 is grounded.

The beneficial effect of adopting the above further scheme is that: the RS232 module can realize serial port communication, and the processor module can realize protocol conversion and information transmission between a serial port and a 1553B bus.

Drawings

Fig. 1 is a block diagram of an intelligent protocol converter according to an embodiment of the present invention.

Fig. 2 is a schematic circuit diagram of a processor module and a 1533B bus interface module according to an embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of the CAN bus interface module according to the embodiment of the present invention.

Fig. 4 is a schematic circuit diagram of an ethernet port module according to an embodiment of the present invention.

Fig. 5 is a schematic circuit diagram of an RS232 interface module according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided to enable those skilled in the art to understand the invention, and it is to be understood that the invention is not limited to the details of the embodiments, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined and defined by the appended claims.

As shown in fig. 1, in an embodiment of the present invention, the present invention provides an intelligent protocol converter, which includes a processor module, a 1533B bus interface module, a CAN bus interface module, an ethernet port module, and an RS232 interface module;

the processor module is respectively connected with the 1533B bus interface module, the CAN bus interface module, the Ethernet port module and the RS232 interface module;

as shown in fig. 2, the processor module adopts a processor chip U1 with model number AT91SAM 9261;

pins A0 to A11, pins D0 to D15, pins PC0, pins CS0, pins A13, pins PC14 and pins PC15 of the processor chip U1 are all connected with a 1522B bus module; the CANTX pin and the CANRX pin of the processor chip U1 are both connected with the CAN bus interface module; an MDIO pin, an MDC pin, an ENTTX0 pin, an ENTRX0 pin, an ENTTX1 pin, an ENTRX1 pin, an ENTTXEN pin, an ENTRER pin, a CRS pin and an ENTTXCLK pin of the processor chip U1 are all connected with the Ethernet port module; the 232TX pin and the 232RX pin of the processor chip U2 are both connected with the RS232 interface module;

the 1533B BUS interface module comprises a protocol chip U2 with the model of BUS-61560, a capacitor C1, a resistor R1, a triode Q1 and a triode Q2;

pins A0 to A11 of the processor chip U1 are connected with pins A0 to A11 of the protocol chip U2 in a one-to-one correspondence manner; the pins D0 to D15 of the processor chip U1 are correspondingly connected with the pins D0 to D15 of the protocol chip U2 one by one; the PC0 pin of the processor chip U1 is respectively connected with the DIR pin and the RD/WR pin of the protocol chip U2; a CS0 pin of the processor chip U1 is respectively connected with a SELECT pin and a STRBD pin of the protocol chip U2; the A13 pin of the processor chip U1 is connected with the MEM/REG pin of the protocol chip U2; the INT pin of the protocol chip U2 is respectively connected with the emitter of the triode Q1 of the PC14 pin of the processor chip U1; the collector of the triode Q1 is connected with the collector of the triode Q2 and is grounded; the base electrode of the triode Q1 is connected with the base electrode of the triode Q2 and is externally connected with a +3.3V power supply; the READY pin of the protocol chip U2 is respectively connected with the PC15 pin of the processor chip U1 and the emitting electrode of the triode Q2; the MSTCLR pin of the protocol chip U2 is respectively connected with one end of the resistor R1 and one end of the capacitor C1; the other end of the resistor R1 is externally connected with a +5V power supply; the other end of the capacitor C1 is grounded; the TRANSPARENT pin, the TAG _ CLK pin, the POLARITY _ SEL pin, the 16/8 pin, the SSFLAG pin, the ADDR _ LAT pin and the ZERO _ WAIT pin of the protocol chip U2 are all grounded;

as shown in fig. 3, the CAN bus interface module includes an isolation chip U3 with a model of ADUM1201, a CAN level conversion chip U4 with a model of AMIS42675, a capacitor C2, an inductor L1, a diode D2, a resistor R2, a ground resistor R3, a resistor R4, a resistor R5, a resistor R6, and a CAN transceiver J1;

the No. 1 pin of the isolation chip U3 is externally connected with a +3.3V power supply; the No. 2 pin and the No. 3 pin of the isolation chip U3 are respectively connected with the CANTX pin and the CANRX pin of the processor chip U1 in a one-to-one correspondence manner; the 4 th pin and the 5 th pin of the isolation chip U3 are both grounded; the 6 th pin of the isolation chip U3 is connected with the 4 th pin of the CAN level conversion chip U4; the 7 th pin of the isolation chip U3 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with one end of the resistor R2; the other end of the resistor R2 is externally connected with a +5V power supply; the 8 th pin of the isolation chip U3 is connected with the 1 st pin of the CAN level conversion chip U4 and is externally connected with a +5V power supply; a No. 2 pin of the CAN level conversion chip U4 is connected with one end of the capacitor C2 and is grounded; a No. 3 pin of the CAN level conversion chip U4 is connected with the other end of the capacitor C2 and is grounded; a 6 th pin and a 7 th pin of the CAN level conversion chip U4 are both connected with one end of the inductor L2; the other end of the inductor L2 is connected with one end of the resistor R4 and one end of the resistor R5 respectively; the other end of the resistor R4 is connected with one end of the diode D2 and one end of the resistor R6 respectively; the other end of the resistor R5 is connected with the other end of the diode D2 and a No. 2 pin and a No. 3 pin of the CAN transceiver respectively; the other end of the resistor R6 is connected with a No. 1 pin of the CAN transceiver; the 8 th pin of the CAN level conversion chip U4 is connected with a grounding resistor R3;

as shown in fig. 4, the ethernet port module includes an ethernet transceiver chip U5 of model number LAN8720A, an RJ45 chip U6 of model number HR11105A, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C3, a capacitor C8, a capacitor C9, and a capacitor C10;

a 12 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R8 and an MDIO pin of the processor chip U1; a13 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R7 and an MDC pin of the processor chip U1; the other end of the resistor R7 is connected with the other end of the resistor R8 and is externally connected with a +3.3V power supply; a 17 th pin and an8 th pin of the Ethernet transceiver chip U5 are respectively connected with an ENTTX0 pin and an ENTRX0 pin of the processor chip U1 in a one-to-one correspondence manner; the 18 th pin and the 7 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTX1 pin and the ENTRX1 pin of the processor chip U1 in a one-to-one correspondence manner; the 16 th pin and the 10 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTXEN pin and the ENTRXER pin of the processor chip U1 in a one-to-one correspondence manner; the 11 th pin of the Ethernet transceiver chip U5 is connected with a CRS pin of the processor chip U1; a 14 th pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R10; a 15 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R9 and one end of the capacitor C3; the other end of the resistor R9 is connected with the other end of the resistor R10 and is externally connected with a +3.3V power supply; the other end of the capacitor C3 is grounded; a 14 th pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R15; the other end of the resistor R15 is grounded; a 21 st pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R11 and a1 st pin of the RJ45 chip U6; a 20 th pin of the Ethernet transceiving chip U5 is respectively connected with one end of the resistor R12 and a 2 nd pin of the RJ45 chip U6; a 23 rd pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R13 and a 3 rd pin of the RJ45 chip U6; a 22 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R14 and a 6 th pin of the RJ45 chip U6; the other end of the resistor R11 is respectively connected with the other end of the resistor R12, the other end of the resistor R13 and the other end of the resistor R14, and is externally connected with a positive 3.3V power supply; a 3 rd pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R16; a 2 nd pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R17; a 19 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C10 and is externally connected with a +3.3V power supply; the No. 1 pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C9 and is externally connected with a +3.3V power supply; a 9 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C8 and is externally connected with a +3.3V power supply; a 6 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of a capacitor C6 and one end of a capacitor C7; a 25 th pin of the ethernet transceiving chip U5 is connected to the other end of the capacitor C10, the other end of the capacitor C11, the other end of the capacitor C12, the other end of the capacitor C13, and the other end of the capacitor C14, respectively, and is grounded; the 5 th pin of the Ethernet transceiving chip U5 is connected with the ENTTXCLK pin of the processor chip U1; a 4 th pin of the RJ45 chip U6 is connected with one end of a capacitor C4; a 5 th pin of the RJ45 chip U6 is connected with one end of a capacitor C5; the other end of the capacitor C4 is connected with the other end of the capacitor C5 and is grounded; a 9 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; the 10 th pin of the RJ45 chip U6 is connected with the other end of the resistor R16; the 11 th pin of the RJ45 chip U6 is connected with the other end of the resistor R17; a 12 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; the 10 th pin of the RJ45 chip U6 is respectively connected with the 14 th pin and the 8 th pin and is grounded;

as shown in fig. 5, the RS232 interface module includes a 232 communication chip U7 with model number SP3232, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, and a 232 interface COM1;

The utility model has the advantages that: the utility model provides a pair of intelligent protocol converter, respectively through 1533B bus interface module, CAN bus interface module, ethernet net gape module and RS232 interface module provide 15533B bus interface, CAN bus interface, ethernet net gape and RS232 interface, and according to 1533B bus interface realized interface logic circuit, and realize the transmission of control 1533B information through processor module, CAN realize 1533B and CAN bus through protocol conversion chip U1 and processor module, ethernet and RS 232's bus communication and protocol conversion.

The utility model discloses a theory of operation does:

the utility model provides an intelligent protocol converter, which realizes CAN bus communication of the intelligent protocol converter by connecting the No. 2 pin and the No. 3 pin of an isolation chip U3 with the CANTX pin and the CANRX pin of a processor chip U1 in a one-to-one correspondence manner; the 12 th pin of the Ethernet transceiving chip U5 is respectively connected with one end of the resistor R8 and the MDIO pin of the processor chip U1, so that management data input and output are realized; the 17 th pin and the 8 th pin of the Ethernet transceiving chip U5 are respectively and correspondingly connected with the ENTTX0 pin and the ENTRX0 pin of the processor chip U1, and the 18 th pin and the 7 th pin of the Ethernet transceiving chip U5 are respectively and correspondingly connected with the ENTTX1 pin and the ENTRX1 pin of the processor chip U1, so that Ethernet data transmission is realized; the 16 th pin and the 10 th pin of the Ethernet transceiving chip U5 are respectively connected with the ENTTXEN pin and the ENTRXER pin of the processor chip U1 in a one-to-one correspondence manner, so that the control of an Ethernet communication switch is realized; the 11 th pin of the Ethernet transceiver chip U5 is connected with the CRS pin of the processor chip U1 to transmit positioning information; the No. 5 pin of the Ethernet transceiving chip U5 is connected with the ENTTXCLK pin of the processor chip U1 to control the Ethernet data transmission clock signal; the 21 st pin of the Ethernet transceiving chip U5 is respectively connected with one end of a resistor R11 and the 1 st pin of an RJ45 chip U6, the 20 th pin of the Ethernet transceiving chip U5 is respectively connected with one end of a resistor R12 and the 2 nd pin of the RJ45 chip U6, the 23 rd pin of the Ethernet transceiving chip U5 is respectively connected with one end of a resistor R13 and the 3 rd pin of the RJ45 chip U6, and the 22 nd pin of the Ethernet transceiving chip U5 is respectively connected with one end of a resistor R14 and the 6 th pin of the RJ45 chip U6, so that the Ethernet communication of the intelligent protocol conversion equipment is completed through an RJ45 interface; the pins A0 and A11 of the processor chip U1 are correspondingly connected with the pins A0 and A11 of the protocol chip U2 one by one, so that the 1533B bus data communication between the processor module and the 1533B bus interface module is realized; the pins D0 to D15 of the processor chip U1 are correspondingly connected with the pins D0 to D15 of the protocol chip U2 one by one, so that 16-bit cache between the processor chip U1 and the protocol chip U2 is realized; the PC0 pin of the processor chip U1 is respectively connected with the DIR pin and the RD/WR pin of the protocol chip U2, and a 1553B bus communication read-write direction control signal is transmitted; the CS0 pin of the processor chip U1 is respectively connected with the SELECT pin and the STRBD pin of the protocol chip U2, so that the protocol chip U2 is selected through the CS0 chip selection signal and data gating is realized; the method comprises the steps that a pin A13 of a processor chip U1 is connected with a MEM/REG pin of a protocol chip U2, and the REG or RAM selection signal of the protocol chip U2 is controlled through high and low levels; the INT pin of the protocol chip U2 is respectively connected with the emitting electrode of the triode Q1 of the PC14 pin of the processor chip U1, and the READY pin of the protocol chip U2 is respectively connected with the PC15 pin of the processor chip U1 and the emitting electrode of the triode Q2, so that the data receiving and sending are completed by interrupt control; the MSTCLR pin of the protocol chip U2 is connected with a high level to realize power-on reset; the buffer/TRANSPARENT mode selection of protocol conversion is realized through a TRANSPARENT pin of a protocol chip U2; read-write signal enabling selection of the protocol conversion microprocessor is realized through a POLARITY _ SEL pin of a protocol chip U2; the data transmission mode selection with the processor module is realized through a 16/8 pin of the protocol chip U2; confirming that the protocol conversion works in a buffering mode through an ADDR _ LAT pin of a protocol chip U2; the ZERO _ WAIT pin of the protocol chip U2 is used for realizing the 0 waiting selection of protocol conversion, and when the logic of the ZERO _ WAIT pin is 0, the communication process between the processor module and the 1533B bus interface module can be realized without handshaking signals.

Claims

1. An intelligent protocol converter is characterized by comprising a processor module, a 1533B bus interface module, a CAN bus interface module, an Ethernet port module and an RS232 interface module;

2. The intelligent protocol converter of claim 1, wherein the processor module employs a processor chip U1 of model AT91SAM 9261;

3. The intelligent protocol converter according to claim 2, wherein the 1533B BUS interface module comprises a protocol chip U2 of type BUS-61560, a capacitor C1, a resistor R1, a transistor Q1, and a transistor Q2;

the pins A0 to A11 of the processor chip U1 are correspondingly connected with the pins A0 to A11 of the protocol chip U2 one by one; the pins D0 to D15 of the processor chip U1 are correspondingly connected with the pins D0 to D15 of the protocol chip U2 one by one; the PC0 pin of the processor chip U1 is respectively connected with the DIR pin and the RD/WR pin of the protocol chip U2; a CS0 pin of the processor chip U1 is respectively connected with a SELECT pin and a STRBD pin of the protocol chip U2; the A13 pin of the processor chip U1 is connected with the MEM/REG pin of the protocol chip U2; the INT pin of the protocol chip U2 is respectively connected with the emitting electrode of the triode Q1 of the PC14 pin of the processor chip U1; the collector of the triode Q1 is connected with the collector of the triode Q2 and is grounded; the base electrode of the triode Q1 is connected with the base electrode of the triode Q2 and is externally connected with a +3.3V power supply; the READY pin of the protocol chip U2 is respectively connected with the PC15 pin of the processor chip U1 and the emitting electrode of the triode Q2; the MSTCLR pin of the protocol chip U2 is respectively connected with one end of the resistor R1 and one end of the capacitor C1; the other end of the resistor R1 is externally connected with a +5V power supply; the other end of the capacitor C1 is grounded; the TRANSPARENT pin, the TAG _ CLK pin, the POLARITY _ SEL pin, the 16/8 pin, the SSFLAG pin, the ADDR _ LAT pin and the ZERO _ WAIT pin of the protocol chip U2 are all grounded.

4. The intelligent protocol converter of claim 3, wherein the CAN bus interface module comprises an isolation chip U3 with a model number ADUM1201, a CAN level conversion chip U4 with a model number AMIS42675, a capacitor C2, an inductor L1, a diode D2, a resistor R2, a ground resistor R3, a resistor R4, a resistor R5, a resistor R6 and a CAN transceiver J1;

the 1 st pin of the isolation chip U3 is externally connected with a +3.3V power supply; the No. 2 pin and the No. 3 pin of the isolation chip U3 are respectively connected with the CANTX pin and the CANRX pin of the processor chip U1 in a one-to-one correspondence manner; the 4 th pin and the 5 th pin of the isolation chip U3 are both grounded; the 6 th pin of the isolation chip U3 is connected with the 4 th pin of the CAN level conversion chip U4; the 7 th pin of the isolation chip U3 is connected with the cathode of the diode D1; the anode of the diode D1 is connected with one end of the resistor R2; the other end of the resistor R2 is externally connected with a +5V power supply; the 8 th pin of the isolation chip U3 is connected with the 1 st pin of the CAN level conversion chip U4 and is externally connected with a +5V power supply; a No. 2 pin of the CAN level conversion chip U4 is connected with one end of the capacitor C2 and is grounded; a No. 3 pin of the CAN level conversion chip U4 is connected with the other end of the capacitor C2 and is grounded; a 6 th pin and a 7 th pin of the CAN level conversion chip U4 are both connected with one end of the inductor L2; the other end of the inductor L2 is connected with one end of the resistor R4 and one end of the resistor R5 respectively; the other end of the resistor R4 is connected with one end of the diode D2 and one end of the resistor R6 respectively; the other end of the resistor R5 is connected with the other end of the diode D2 and a No. 2 pin and a No. 3 pin of the CAN transceiver respectively; the other end of the resistor R6 is connected with a No. 1 pin of the CAN transceiver; and the 8 th pin of the CAN level conversion chip U4 is connected with the grounding resistor R3.

5. The intelligent protocol converter of claim 4, wherein the ethernet port module comprises an ethernet transceiver chip U5 of model number LAN8720A, an RJ45 chip U6 of model number HR11105A, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C3, a capacitor C8, a capacitor C9, and a capacitor C10;

a 12 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R8 and an MDIO pin of the processor chip U1; a13 th pin of the Ethernet transceiving chip U5 is respectively connected with one end of the resistor R7 and an MDC pin of the processor chip U1; the other end of the resistor R7 is connected with the other end of the resistor R8 and is externally connected with a +3.3V power supply; a 17 th pin and an8 th pin of the Ethernet transceiver chip U5 are respectively connected with an ENTTX0 pin and an ENTRX0 pin of the processor chip U1 in a one-to-one correspondence manner; the 18 th pin and the 7 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTX1 pin and the ENTRX1 pin of the processor chip U1 in a one-to-one correspondence manner; the 16 th pin and the 10 th pin of the Ethernet transceiver chip U5 are respectively connected with the ENTTXEN pin and the ENTRXER pin of the processor chip U1 in a one-to-one correspondence manner; the 11 th pin of the Ethernet transceiver chip U5 is connected with a CRS pin of the processor chip U1; a 14 th pin of the Ethernet transceiving chip U5 is connected with one end of the resistor R10; a 15 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R9 and one end of the capacitor C3; the other end of the resistor R9 is connected with the other end of the resistor R10 and is externally connected with a +3.3V power supply; the other end of the capacitor C3 is grounded; a 14 th pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R15; the other end of the resistor R15 is grounded; a 21 st pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R11 and a1 st pin of the RJ45 chip U6; a 20 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of a resistor R12 and a 2 nd pin of an RJ45 chip U6; a 23 rd pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R13 and a 3 rd pin of the RJ45 chip U6; a 22 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of the resistor R14 and a 6 th pin of the RJ45 chip U6; the other end of the resistor R11 is respectively connected with the other end of the resistor R12, the other end of the resistor R13 and the other end of the resistor R14, and is externally connected with a positive 3.3V power supply; a 3 rd pin of the Ethernet transceiver chip U5 is connected with one end of a resistor R16; a 2 nd pin of the Ethernet transceiving chip U5 is connected with one end of a resistor R17; a 19 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C10 and is externally connected with a +3.3V power supply; the No. 1 pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C9 and is externally connected with a +3.3V power supply; a 9 th pin of the Ethernet transceiver chip U5 is connected with one end of a capacitor C8 and is externally connected with a +3.3V power supply; a 6 th pin of the Ethernet transceiver chip U5 is respectively connected with one end of a capacitor C6 and one end of a capacitor C7; a 25 th pin of the ethernet transceiving chip U5 is connected to the other end of the capacitor C10, the other end of the capacitor C11, the other end of the capacitor C12, the other end of the capacitor C13, and the other end of the capacitor C14, respectively, and is grounded; the 5 th pin of the Ethernet transceiving chip U5 is connected with the ENTTXCLK pin of the processor chip U1; a 4 th pin of the RJ45 chip U6 is connected with one end of a capacitor C4; a 5 th pin of the RJ45 chip U6 is connected with one end of a capacitor C5; the other end of the capacitor C4 is connected with the other end of the capacitor C5 and is grounded; the 9 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; the 10 th pin of the RJ45 chip U6 is connected with the other end of the resistor R16; the 11 th pin of the RJ45 chip U6 is connected with the other end of the resistor R17; the 12 th pin of the RJ45 chip U6 is externally connected with a +3.3V power supply; and the 10 th pin of the RJ45 chip U6 is respectively connected with the 14 th pin and the 8 th pin and is grounded.

6. The intelligent protocol converter according to claim 5, wherein the RS232 interface module comprises a 232 communication chip U7 with model number SP3232, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13 and a 232 interface COM1;