CN217522826U - Sampling circuit based on multichannel high-speed SAR ADC - Google Patents

Sampling circuit based on multichannel high-speed SAR ADC Download PDF

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CN217522826U
CN217522826U CN202221064825.6U CN202221064825U CN217522826U CN 217522826 U CN217522826 U CN 217522826U CN 202221064825 U CN202221064825 U CN 202221064825U CN 217522826 U CN217522826 U CN 217522826U
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coupled
sampling
switch
circuit
sampling switch
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乐超
程知群
周鑫
周涛
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Hangzhou University Of Electronic Science And Technology Fuyang Institute Of Electronic Information Co ltd
Suzhou Youliang Smart Technology Co ltd
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Hangzhou University Of Electronic Science And Technology Fuyang Institute Of Electronic Information Co ltd
Suzhou Youliang Smart Technology Co ltd
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Abstract

The utility model discloses a sampling circuit based on multichannel high-speed SAR ADC, the first sampling switch comprises a grid voltage bootstrap circuit and a grid voltage transmission control switch, can finish selecting one path from multiple paths and sampling the input signal of the path; the second sampling switch is composed of an NMOS tube, and can realize synchronous sampling of the path of signals with the first sampling switch, and the result is transmitted to the high-speed ADC for conversion and output. The utility model discloses an improve traditional grid voltage bootstrapping sampling circuit, utilize multiplexing design theory, adopt grid voltage transmission control switch, realized that a plurality of passageways share an ADC, improved the uniformity of each passageway conversion precision, introduce the second sampling switch simultaneously, eliminated on the one hand because MOS pipe leakage current exists the nonlinearity that leads to sampling voltage; on the other hand, the multichannel output node is isolated from the Top end of the ADC capacitor array, so that the problem of capacitor array capacitor mismatch caused by large parasitic capacitance of the multichannel output node is solved, and the precision of the whole ADC system is greatly improved.

Description

Sampling circuit based on multichannel high-speed SAR ADC
Technical Field
The utility model belongs to the technical field of the analog signal chain, in particular to sampling circuit based on high-speed SAR ADC of multichannel.
Background
With the rapid development of the internet of things, in the fields of the internet of things such as environment monitoring, mobile sharing equipment and fire alarm, a plurality of electronic systems need to acquire and process a plurality of paths of analog input signals during working, and the acquisition and processing can be realized by using a plurality of ADCs in the system, but the scheme can greatly increase the power consumption and the chip area of the system. In order to solve the problem, a high-speed SAR ADC with multi-channel sampling needs to be designed, so that the characteristics of high speed, low power consumption, high integration level and the like are realized while the application requirements are met. The multichannel sampling circuit is positioned at the front end of the multichannel high-speed SAR ADC, discretizes an input continuous analog signal, is the first step of analog-to-digital conversion of the ADC, and plays an important role in improving the speed and precision of the whole ADC system.
For a multi-channel high-speed SAR ADC, as the number of channels increases, the conventional method of directly connecting a plurality of sampling circuits in parallel will have many problems: firstly, when the number of channels reaches dozens, the number of transistors of the sampling circuit is increased sharply, and the power consumption and the chip area of a system are greatly increased; secondly, in the multi-channel SAR ADC sampling circuit, when one channel is opened and the other channels are all closed, the channel is not completely closed due to the existence of MOS tube leakage current, so that the leakage of the charge of the grid electrode of the opened channel sampling tube is caused, the output voltage is nonlinear, and the nonlinearity can cause the reduction of the system precision along with the increase of the number of the channels; thirdly, as the number of channels increases, the parasitic capacitance of the output node of the multi-channel sampling circuit becomes very large, and when the node is directly connected with the Top end of the capacitor array, the capacitor of the capacitor array is mismatched, so that the output nonlinear error is caused, and the precision of the whole ADC system is greatly reduced.
SUMMERY OF THE UTILITY MODEL
In order to overcome the problem that exists in the above-mentioned technique, the utility model provides a sampling circuit based on high-speed SAR ADC of multichannel. By applying a multiplexing design concept and adopting a grid voltage transfer control switch, a plurality of channels share one ADC (analog to digital converter), the identity of conversion precision of each channel is improved, and meanwhile, a second sampling switch is introduced, so that the nonlinearity of sampling voltage caused by the leakage current of an MOS (metal oxide semiconductor) tube is eliminated; on the other hand, the multichannel output node is isolated from the Top end of the ADC capacitor array, so that the problem of capacitor array capacitor mismatch caused by large parasitic capacitance of the multichannel output node is solved, and the precision of the whole ADC system is greatly improved.
In order to achieve the above object, the present invention provides a sampling circuit based on a multi-channel high-speed SAR ADC, comprising a first sampling switch and a second sampling switch, wherein,
the first sampling switch is used for selecting one path from multiple paths and sampling the input signal, and the input end of the first sampling switch is coupled with the external N paths of input signals V i N, the output end of the second sampling switch is coupled with the input end of the second sampling switch to provide an input signal V for the second sampling switch i ＜n＞；
The second sampling switch is used for realizing the synchronous signal V with the first sampling switch i And (n) sampling, transmitting the result Vout to a subsequent high-speed ADC for conversion output, wherein the input end of the Vout is coupled with the output end of the first sampling switch, and the output end of the Vout is coupled with the Top end of a subsequent high-speed ADC capacitor array.
Preferably, the first sampling switch includes a gate voltage bootstrap circuit and an N-way gate voltage transfer control switch S < 1: N >, wherein a fo _ vi end of the gate voltage bootstrap circuit is coupled to a fo _ vi end of the gate voltage transfer control switch, and a Vg end of the gate voltage bootstrap circuit is coupled to a Vg end of the gate voltage transfer control switch and a Vg end of the second sampling switch, respectively.
Preferably, the gate voltage bootstrapping circuit comprises two control signals clk _ s and clk _ s _ n with opposite polarities, 6 NMOS transistors: m 202 、M 203 、M 206 、M 207 、M 208 And M 210 4 PMOS transistors: m 201 、M 204 、M 205 And M 209 A capacitor C 0 Wherein:
the control signals clk _ s are coupled to M 201 、M 202 、M 209 And M 210 When the grid is at high level, the circuit enters a sampling state; the control signals clk _ s _ n are coupled to M 203 、M 208 And M 209 、 M 210 When the drain of the circuit is at a high level, the circuit enters a hold state;
M 204 the drain electrode of the transistor is coupled with a power supply AVDD, the grid electrode of the transistor is coupled with a Vg end, and the source electrodes of the transistor are respectively coupled with a capacitor C 0 Upper electrode plate, M 205 A source of such a connection that the capacitor C is connected 0 The voltage of the upper polar plate reaches a required large value without being clamped;
the fo _ vi terminals are respectively connected with M 202 Source electrode, M 203 Drain electrode of (1), M 206 Source electrode and capacitor C 0 The lower polar plate of the circuit is coupled, when the circuit is in a sampling state, the voltage of the end changes along with the voltage of the input signal selected by the grid voltage transmission control switch;
vg terminal is respectively connected to M 204 、M 206 And M 205 、M 207 The drain electrodes of the two electrodes are coupled;
M 201 、M 209 source and M 207 The grids of the grid-connected transistors are coupled with a power supply AVDD; m 203 、M 208 、 M 210 The sources of (a) are all coupled to ground AGND; m 201 、M 202 、M 206 Drain electrode of (1) and 205 the grid of the grid is coupled; m 207 Source and M of 208 Are coupled.
Preferably, the grid voltage transmission control switch S < 1: N > is formed by connecting N grid voltage transmission control switches in parallel.
Preferably, the gate voltage transfer control switch includes an enable signal OE1, two enable signals OE2 and OE2 — N with opposite polarities, and 7 NMOS transistors: m 303 、M 304 、M 305 、M 306 、M 307 、 M 308 And M 310 3 PMOS transistors: m is a group of 301 、M 302 And M 309 Wherein:
the enable signals OE1 are coupled to M 301 、M 302 The enable signals OE2 are respectively coupled to M 303 、 M 304 The two gates control the transfer of a Vg port signal together;
the enable signals OE2 are respectively coupled to M 309 、M 310 And through a gate of M 309 、M 310 The inverter is configured to generate an enable signal OE2_ N, and OE2_ N is coupled to M 309 、M 310 A drain electrode of (1); the enable signal OE2_ N is coupled to M 305 Of the grid, control M 305 Is turned on and off, when it is at a high level, M 305 Conducting;
vg terminals are coupled to M respectively 301 Source electrode, M 303 Drain of, input V i Terminals are respectively coupled to M 307 Drain electrode of (1), M 308 Source of, output V o End coupling M 308 A drain electrode of (1);
fo _ vi terminal is coupled to M 307 When M is a source of 307 When the gate of (c) is high, the voltage at the fo _ vi terminal will follow the input signal V i A change in voltage;
M 306 grid electrode of, M 309 The sources of the transistors are coupled with a power supply AVDD; m 305 、M 310 The sources of (a) are all coupled to ground AGND; m 301 Is coupled with the drain electrode of M 302 Source electrode of, M 303 Is coupled with M 304 Drain electrode of (D), M 305 Is coupled with the drain electrode of M 306 A source electrode of (a);
M 307 、M 308 respectively with M 302 、M 306 Drain electrode of (1) and M 304 Are coupled.
Preference is given toGround, the second sampling switch only adopts 1 NMOS transistor M 401 The realization is that, among others,
M 401 the grid electrode of the first sampling switch is coupled with the Vg end of the second sampling switch, and the source electrode of the first sampling switch is coupled with the output V of the grid voltage transmission control switch o And the drain of the terminal is coupled with the Vout terminal of the second sampling switch and outputs a final sampling signal.
The beneficial effects of the utility model include at least: compared with the prior art, the utility model discloses the application is multiplexing to design the theory, adopts grid voltage transmission control switch, has realized that a plurality of passageways share an ADC, has improved the identity of each passageway conversion precision, has also reduced the area that multichannel sampling circuit account for the chip, introduces the second sampling switch simultaneously, has eliminated on the one hand because MOS pipe leakage current exists and has led to the nonlinearity of sampling voltage; on the other hand, the multichannel output node is isolated from the Top end of the ADC capacitor array, so that the problem of capacitor array capacitor mismatch caused by large parasitic capacitance of the multichannel output node is solved, and the precision of the whole ADC system is greatly improved.
Drawings
In order to make the purpose, technical scheme and beneficial effect of the utility model clearer, the utility model provides a following figure explains:
fig. 1 is a block diagram of a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;
fig. 2 is a specific structure block diagram of the sampling circuit based on the multi-channel high-speed SAR ADC according to the embodiment of the present invention;
fig. 3 is a schematic diagram of a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a gate voltage transfer control switch in a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;
fig. 5 is a simulation test chart of the sampling circuit based on the multi-channel high-speed SAR ADC according to the embodiment of the present invention;
fig. 6 is a time domain simulation diagram of Vout and clk _ s of a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention;
fig. 7 shows Vout and V of the sampling circuit based on the multi-channel high-speed SAR ADC according to the embodiment of the present invention i <1>Time domain simulation graphs of (1);
fig. 8 is a diagram of FFT simulation result of sampling circuit based on multi-channel high-speed SAR ADC according to an embodiment of the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention will be made with reference to the accompanying drawings.
Referring to fig. 1-4, a block diagram and a schematic circuit diagram of a sampling circuit based on a multi-channel high-speed SAR ADC according to an embodiment of the present invention are shown, including a first sampling switch 100 and a second sampling switch 400, wherein,
the first sampling switch 100 is used for selecting one input signal from the plurality of input signals and sampling the selected input signal, and has an input terminal coupled to the external N input signals V i < 1: N >, the output terminal of which is coupled to the input terminal of the second sampling switch 400 to provide an input signal V to the second sampling switch 400 i ＜n＞；
The second sampling switch 400 is used to implement the synchronous pair signal V with the first sampling switch 100 i And n is larger than n, sampling is carried out, the result Vout is transmitted to a rear-connected high-speed ADC for conversion and output, the input end of the result Vout is coupled with the output end of the first sampling switch 100, and the output end Vout is coupled with the Top end of a rear-level high-speed ADC capacitor array.
The first sampling switch 100 includes a gate voltage bootstrap circuit 200 and an N-way gate voltage transfer control switch 300S < 1: N >, wherein a fo _ vi end of the gate voltage bootstrap circuit 200 is coupled to a fo _ vi end of the gate voltage transfer control switch 300, and a Vg end of the gate voltage bootstrap circuit 200 is coupled to a Vg end of the gate voltage transfer control switch 300 and a Vg end of the second sampling switch 400, respectively.
The gate voltage bootstrapping circuit 200 includes two control signals clk _ s and clk _ s _ n of opposite polarities, 6 NMOS transistors: m is a group of 202 、M 203 、M 206 、M 207 、M 208 And M 210 4 PMOS transistors: m 201 、M 204 、M 205 And M 209 A capacitor C 0 Wherein:
the control signals clk _ s are coupled to M 201 、M 202 、M 209 And M 210 When the grid is at high level, the circuit enters a sampling state; the control signals clk _ s _ n are coupled to M 203 、M 208 And M 209 、 M 210 When the drain of the circuit is at a high level, the circuit enters a hold state;
M 204 the drain electrode of the transistor is coupled with a power supply AVDD, the grid electrode of the transistor is coupled with a Vg end, and the source electrodes of the transistor are respectively coupled with a capacitor C 0 Upper electrode plate, M 205 A source of such a connection that the capacitor C is connected 0 The voltage of the upper polar plate reaches a required large value without being clamped;
the fo _ vi terminals are respectively connected with M 202 Source electrode, M 203 Drain electrode of (1), M 206 Source electrode and capacitor C 0 The lower plate of the gate voltage transfer control switch 300 is coupled, and when the circuit is in a sampling state, the voltage of the end changes along with the voltage of the input signal selected by the gate voltage transfer control switch;
vg terminal is respectively connected with M 204 、M 206 And M 205 、M 207 The drain electrodes of the two electrodes are coupled;
M 201 、M 209 source and M 207 The grids of the grid-connected transistors are coupled with a power supply AVDD; m is a group of 203 、M 208 、 M 210 The sources of (a) are all coupled to ground AGND; m is a group of 201 、M 202 、M 206 Drain electrode of (1) and M 205 The grid of the grid is coupled; m 207 Source and M of 208 Are coupled.
The grid voltage transmission control switch 300S is less than 1: N is formed by connecting N grid voltage transmission control switches 300 in parallel.
The gate voltage transfer control switch 300 includes an enable signal OE1, two enable signals OE2 and OE2 — N with opposite polarities, 7 NMOS transistors: m 303 、M 304 、M 305 、M 306 、M 307 、M 308 And M 310 3 PMOS transistors: m is a group of 301 、M 302 And M 309 Wherein:
the enable signals OE1 are respectively coupled to M 301 、M 302 The enable signals OE2 are respectively coupled to M 303 、 M 304 The two gates control the transfer of Vg port signals together;
the enable signals OE2 are coupled to M 309 、M 310 And through a gate of M 309 、M 310 The inverter is configured to generate an enable signal OE2_ N, and OE2_ N is coupled to M 309 、M 310 A drain electrode of (1); the enable signal OE2_ N is coupled to M 305 Gate of (C), control M 305 When it is high, M 305 Conducting;
vg terminals are coupled to M respectively 301 Source electrode, M 303 Drain of, input V i Terminals are respectively coupled to M 307 Drain electrode of (1), M 308 Source of, output V o End coupling M 308 A drain electrode of (1);
fo _ vi terminal is coupled to M 307 Source of (2) when M 307 When the gate of (c) is high, the voltage at the fo _ vi terminal will follow the input signal V i A change in voltage;
M 306 grid electrode of, M 309 The sources of the transistors are coupled with a power supply AVDD; m 305 、M 310 The sources of (a) are all coupled to ground AGND; m 301 Is coupled with the drain electrode of M 302 Source electrode of, M 303 Is coupled with M 304 Drain electrode of, M 305 Is coupled with the drain electrode of M 306 A source electrode of (a);
M 307 、M 308 respectively with M 302 、M 306 Drain electrode of (1) and M 304 Are coupled.
The second sampling switch 400 only employs 1 NMOS transistor M 401 The realization is that, among others,
M 401 a gate of the second sampling switch 400 is coupled to the Vg terminal, and a source thereof is coupled to the output V of the gate voltage transfer control switch 300 o And a terminal, the drain of which is coupled to the terminal Vout of the second sampling switch 400, outputting the final sampling signal.
The following is a specific embodiment of the 200-channel 10-bit high-speed SAR ADC sampling circuit designed based on 28nm CMOS process, and the technical solution of the present invention is further described with reference to the accompanying drawings, but the present invention is not limited to these embodiments.
As shown in fig. 1 to 4, the utility model provides a pair of based on high-speed SAR ADC sampling circuit of multichannel, including first sampling switch 100 and second sampling switch 400, wherein first sampling switch 100 contains grid voltage bootstrap circuit 200 again and 200 way grid voltage transfer control switch 300, refer to fig. 2, grid voltage bootstrap circuit 200 provides required voltage Vg for 200 way grid voltage transfer control switch 300 and second sampling switch 400, its fo _ vi end is coupled 200 way grid voltage transfer control switch 300's fo _ vi end, its Vg end is coupled 200 way grid voltage transfer control switch 300's Vg end, the Vg end of second sampling switch 400 respectively; 200-path input signal V of grid voltage transmission control switch i Selecting one path from < 1:200 > and sampling it to generate V i < n >, as an input signal of the second sampling switch 400, the output terminal thereof is coupled to the input terminal of the second sampling switch 400; the second sampling switch 400 is synchronized with the gate voltage transfer control switch to the signal V i And n is greater than the threshold value, sampling is carried out, and the result Vout is transmitted to a high-speed ADC at the later stage for conversion and output.
The gate voltage bootstrapping circuit 200 includes two control signals clk _ s and clk _ s _ n of opposite polarities, 6 NMOS transistors: m 202 、M 203 、M 206 、M 207 、M 208 And M 210 4 PMOS transistors: m 201 、M 204 、M 205 And M 209 And a capacitor C 0 . As shown in FIG. 3, the control signal clk _ s passes through M 201 And M 202 Conversion of constituent inverter structures to new voltage signal control M 205 Is turned on. When the control signal clk _ s is low, the tube M in the circuit 203 、M 204 、M 207 And M 208 Conducting to make the capacitor C 0 The upper electrode plate is connected with a power supply voltage AVDD, the lower electrode plate is connected with an earth AGND, and a capacitor C 0 Charging to a power supply voltage, and Vg is 0; when the control signal clk _ s is high, M 205 On, the voltage at port fo _ vi is equal to V i N, then Vg is V i ＜n＞+AVDD。M 204 The drain is coupled to a power supply AVDD, the gate is coupled to a Vg terminal, and the source is coupled to a groundCoupling capacitor C 0 The connection method of the upper polar plate is different from that of the traditional PMOS tube, so that the capacitor C can be formed 0 The voltage of the upper polar plate reaches a required large value without being clamped, and the following conditions can be ensured: vg ═ V i < n > + AVDD holds true throughout.
The 200-channel gate voltage transfer control switch 300 is composed of 200 gate voltage transfer control switches connected in parallel, and the circuit of each gate voltage transfer control switch is shown in fig. 4, and includes an enable signal OE1, two enable signals OE2 and OE2 — N with opposite polarities, and 7 NMOS transistors: m 303 、M 304 、M 305 、M 306 、 M 307 、M 308 And M 310 3 PMOS transistors: m 301 、M 302 And M 309 . The enable signals OE1 and OE2 jointly control the input signal V from 200 channels i And selecting one signal from the signals with the ratio of < 1:200 for sampling and outputting. When OE1<1>At low level, OE2<1>Is high and OE1<2:200>At high level, OE2<2:200>When the input signal is in a low level, the first path of input signal is gated, and the other paths of input signals are switched off. When the first path of input signal is gated, M of the path 301 、M 302 、M 303 And M 304 In the on state, M 307 And M 308 The gate voltage of Vg is V i < 1 > + AVDD, M 308 The gate-source voltage difference of (1) is always kept as the power supply voltage and M can be reduced regardless of the input signal 308 Thereby reducing the attenuation of the sampling process to the input signal and increasing M 308 The sampling precision of (2); when Vg is 0, M 307 And M 308 In the off state, the circuit enters a hold phase. M of the other paths when the input signals of the other paths are turned off 301 、M 302 、M 303 And M 304 Are all turned off, and M 305 And M 306 Is turned on, M 307 And M 308 The gate voltages of (1) are all at off-state, 0.
The second sampling switch 400 is composed of only 1 NMOS transistor M 401 Composition, as shown in fig. 3. When Vg is V i < 1 > + AVDD, M 401 The grid-source voltage difference is always kept as the power supplyVoltage independent of input signal, synchronous with the first gate voltage transfer control switch i <1>Sampling is carried out, and the final sampling precision is improved; when Vg is 0, M 401 Is switched off and enters a holding phase. At the same time, M 401 On one hand, the nonlinearity of sampling voltage caused by the existence of MOS tube leakage current is eliminated; on the other hand, the output nodes of the 200-path gate voltage transfer control switch 300 are isolated from the Top end of the ADC capacitor array, so that the problem of capacitor array capacitor mismatch caused by large parasitic capacitance of the 200-path output nodes is solved.
All the design modules are combined and connected, and simulation is carried out in Cadence software.
Fig. 5 is a simulation test chart based on a 200-channel high-speed SAR ADC sampling circuit, and fig. 6, 7 and 8 at the back are graphs of results obtained according to the simulation setup of fig. 5.
Referring to fig. 6 and 7, the final sampling result Vout (dashed vo line in fig. 6) accurately follows and holds the input signal V under the action of the control signal clk _ s (solid line in fig. 6) i <1>(solid line in fig. 7).
Referring to fig. 8, the Effective Number (ENOB) of the final sampling result Vout can reach 10.5bits, and SNR is 64.9dB, SFDR is 65.7dBc, which meets the requirements of 200-channel 10-bit high-speed SAR ADC for the sampling circuit.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims (6)

1. A sampling circuit based on a multi-channel high-speed SAR ADC is characterized by comprising a first sampling switch and a second sampling switch, wherein,
the first sampling switch is used for selecting one path from multiple paths and sampling the input signal, and the input end of the first sampling switch is coupled with the external N paths of input signals V i N, the output end of the second sampling switch is coupled with the input end of the second sampling switch to provide an input signal V for the second sampling switch i ＜n＞；
The second sampling switch is used for realizing synchronous signal V with the first sampling switch i And (n) sampling, transmitting the result Vout to a rear-connected high-speed ADC for conversion output, wherein the input end of the Vout is coupled with the output end of the first sampling switch, and the output end of the Vout is coupled with the Top end of a rear-level high-speed ADC capacitor array.
2. The sampling circuit based on the multi-channel high-speed SAR ADC of claim 1, wherein the first sampling switch comprises a gate voltage bootstrap circuit and an N-channel gate voltage transfer control switch S < 1: N >, wherein a fo _ vi end of the gate voltage bootstrap circuit is coupled to a fo _ vi end of the gate voltage transfer control switch, and a Vg end of the gate voltage bootstrap circuit is coupled to a Vg end of the gate voltage transfer control switch and a Vg end of the second sampling switch respectively.
3. The multi-channel high speed SAR ADC-based sampling circuit of claim 2, wherein the gate voltage bootstrapping circuit comprises two control signals clk _ s and clk _ s _ n of opposite polarity, 6 NMOS transistors: m 202 、M 203 、M 206 、M 207 、M 208 And M 210 4 PMOS transistors: m 201 、M 204 、M 205 And M 209 A capacitor C 0 Wherein:
the control signals clk _ s are coupled to M 201 、M 202 、M 209 And M 210 When the grid is at high level, the circuit enters a sampling state; the control signals clk _ s _ n are coupled to M 203 、M 208 And M 209 、M 210 When the drain of the circuit is at a high level, the circuit enters a hold state;
M 204 the drain electrode of the transistor is coupled with a power supply AVDD, the grid electrode of the transistor is coupled with a Vg end, and the source electrodes of the transistor are respectively coupled with a capacitor C 0 Upper electrode plate, M 205 A source of (2), the connection being such that the capacitor C is 0 The voltage of the upper plate reaches a required valueWithout being clamped;
the fo _ vi terminals are respectively connected with M 202 Source electrode, M 203 Drain electrode of (1), M 206 Source electrode and capacitor C 0 The lower polar plate of the circuit is coupled, when the circuit is in a sampling state, the voltage of the end changes along with the voltage of the input signal selected by the grid voltage transmission control switch;
vg terminal is respectively connected with M 204 、M 206 And M 205 、M 207 The drain electrodes of the two electrodes are coupled;
M 201 、M 209 source and M 207 The gates of the transistors are coupled with a power supply AVDD; m 203 、M 208 、M 210 The sources of (a) are all coupled to ground AGND; m 201 、M 202 、M 206 Drain electrode of (1) and 205 the grid of the grid is coupled; m 207 Source and M of 208 Are coupled.
4. The sampling circuit based on the multi-channel high-speed SAR ADC of claim 2, wherein the grid voltage transfer control switch S < 1: N > is formed by connecting N grid voltage transfer control switches in parallel.
5. The sampling circuit based on the multi-channel high-speed SAR ADC of claim 4, wherein the gate voltage transfer control switch comprises an enable signal OE1, two enable signals OE2 and OE2_ N with opposite polarities, and 7 NMOS transistors: m 303 、M 304 、M 305 、M 306 、M 307 、M 308 And M 310 3 PMOS transistors: m 301 、M 302 And M 309 Wherein:
the enable signals OE1 are coupled to M 301 、M 302 The enable signals OE2 are respectively coupled to M 303 、M 304 The two gates control the transfer of Vg port signals together;
the enable signals OE2 are coupled to M 309 、M 310 And through a gate of M 309 、M 310 The inverter is configured to generate an enable signalOE2_ N, and OE2_ N are coupled to M 309 、M 310 A drain electrode of (1); the enable signal OE2_ N is coupled to M 305 Of the grid, control M 305 Is turned on and off, when it is at a high level, M 305 Conducting;
vg terminals are coupled to M respectively 301 Source electrode, M 303 Drain of (2), input V i Terminals are respectively coupled to M 307 Drain electrode of (1), M 308 Source of, output V o End coupling M 308 A drain electrode of (1);
fo _ vi terminal is coupled to M 307 When M is a source of 307 When the gate of (c) is high, the voltage at the fo _ vi terminal will follow the input signal V i A change in voltage;
M 306 gate electrode of (1), M 309 The sources of the first and second transistors are coupled to a power supply AVDD; m 305 、M 310 The sources of (a) are all coupled to ground AGND; m 301 Is coupled with the drain electrode of M 302 Source electrode of, M 303 Is coupled with M 304 Drain electrode of, M 305 Is coupled with the drain electrode of M 306 A source electrode of (a);
M 307 、M 308 respectively with M 302 、M 306 Drain electrode of (1) and M 304 Are coupled.
6. The multi-channel high-speed SAR ADC-based sampling circuit of claim 5, wherein the second sampling switch only employs 1 NMOS transistor M 401 The realization is that, among others,
M 401 the grid electrode of the first sampling switch is coupled with the Vg end of the second sampling switch, and the source electrode of the first sampling switch is coupled with the output V of the grid voltage transmission control switch o And the drain of the terminal is coupled with the Vout terminal of the second sampling switch to output a final sampling signal.
CN202221064825.6U 2022-05-06 2022-05-06 Sampling circuit based on multichannel high-speed SAR ADC Active CN217522826U (en)

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