CN217507337U - Display panel and display module - Google Patents

Abstract

The application provides a display panel and display module assembly, through marking off the interval section in the test line of connecting second thin film transistor and test terminal, set up the via hole that is located the interval section top on the insulating layer, be convenient for keep the disconnection of test line in the interval section position in array substrate manufacture process, avoid static to lead into on the second thin film transistor through the test terminal, metal level and insulating layer in the array substrate are makeed the back, can make the interval section at via hole department and make the test line switch on, realize the intercommunication between second thin film transistor and the test terminal, the effectual test of static to second thin film transistor electrical property of having avoided.

Description

Display panel and display module

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display module.

Background

In the panel display industry, a pixel circuit includes a plurality of Thin Film Transistors (TFTs), and the quality of each TFT determines the quality of a product. However, in the process of manufacturing the array substrate, because the test terminal is exposed, Static electricity is introduced into the TFT through the test terminal due to electrostatic Discharge (ESD) in the subsequent process, which causes a change in electrical characteristics of the TFT, and the measured electrical characteristics of the TFT cannot truly reflect the electrical characteristics of the TFT in the pixel circuit, which is not favorable for detecting and improving the abnormality of the TFT in the pixel circuit in time.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a display panel and a display module to solve the technical problem that data distortion occurs when a TFT used for measurement is influenced by ESD.

The embodiment of the application provides a display panel, which comprises a display area and a non-display area adjacent to the display area, wherein the display panel comprises an array substrate, the array substrate comprises a plurality of first thin film transistors positioned in the display area, at least one second thin film transistor positioned in the non-display area, a plurality of test terminals and a plurality of test wires, and one test terminal is connected with the second thin film transistor through one test wire;

the array substrate further comprises a substrate layer, a metal layer arranged on the substrate layer and an insulating layer arranged in a stacking mode with the metal layer, the metal layer comprises the test terminal and the test wiring, and the insulating layer comprises a plurality of through holes located in the non-display area;

the test wiring comprises a spacing section, the through hole is correspondingly arranged above the spacing section, and the projection of the spacing section on the substrate layer is located in the range of the through hole.

In the display panel provided in the embodiment of the present application, the plurality of test traces include a first test trace, a second test trace, and a third test trace, and the plurality of test terminals include a first test terminal, a second test terminal, and a third test terminal;

one end of the first testing wire is connected with the first testing terminal, the other end of the first testing wire is connected with the testing grid electrode of the second thin film transistor, one end of the second testing wire is connected with the second testing terminal, the other end of the second testing wire is connected with the testing source electrode of the second thin film transistor, one end of the third testing wire is connected with the third testing terminal, and the other end of the third testing wire is connected with the testing drain electrode of the second thin film transistor;

the metal layer comprises a first metal layer and a second metal layer which is positioned on one side of the first metal layer far away from the substrate layer, the first metal layer comprises the test grid and the first test wire, and the second metal layer comprises the test source electrode, the test drain electrode, the second test wire and the third test wire;

the first test wire comprises a first spacing section, the second test wire comprises a second spacing section, the third test wire comprises a third spacing section, and the plurality of via holes comprise a first via hole positioned above the first spacing section, a second via hole positioned above the second spacing section, and a third via hole positioned above the third spacing section.

In the display panel provided by the embodiment of the application, the insulating layer includes a first insulating sublayer located on a side of the second metal layer away from the substrate layer, the second via hole passes through the first insulating sublayer, and the third via hole passes through the first insulating sublayer.

In the display panel provided in the embodiment of the present application, the insulating layer further includes a second insulating sub-layer located between the second metal layer and the first metal layer, and the first via hole passes through the first insulating sub-layer and the second insulating sub-layer.

In the display panel provided by the embodiment of the application, the first test wire further comprises a first section and a second section, one end of the spacer is connected with the first section, the other end of the spacer is connected with the second section, and the spacer covers a part of the first section and a part of the second section.

In the display panel that this application embodiment provided, follow in the direction that the test was walked the line and is extended, the interval with first section overlap portion's length is 3um ~ 8um, the interval with second section overlap portion's length is 3um ~ 8 um.

In the display panel provided in the embodiment of the present application, the material of the first segment is the same as the material of the second segment, and the material of the first segment is different from the material of the spacer.

In the display panel provided in the embodiment of the present application, the display panel further includes a third metal layer, the third metal layer includes a plurality of electrodes, and a material of the electrodes is the same as a material of the spacer.

In the display panel provided in the embodiment of the present application, the first metal layer further includes a metal gate of the first thin film transistor, and the second metal layer further includes a metal source and a metal drain of the first thin film transistor.

The embodiment of the application provides a display module, including the display panel in above arbitrary embodiment.

The beneficial effect of this application does: the application provides a display panel and display module assembly, walk the line through the test of connecting second thin film transistor and test terminal and mark off the interval section, set up the via hole that is located the interval section top on the insulating layer, be convenient for keep the test in array substrate manufacture in-process and walk the disconnection of line at the interval section position, avoid static to pass through the leading-in second thin film transistor of test terminal on, metal level and insulating layer in array substrate make the back of accomplishing, can make the interval section at via hole department and make the test walk the line and switch on, realize the intercommunication between second thin film transistor and the test terminal, the effectual test of static to second thin film transistor electrical property of having avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure;

FIG. 3 is an enlarged view of a portion A of FIG. 1;

FIG. 4 is a schematic cross-sectional view taken along line A-A of FIG. 3;

FIG. 5 is a schematic view of a portion of the enlarged structure at B in FIG. 4;

FIG. 6 is a schematic cross-sectional view of the first spacer of FIG. 4 prior to fabrication;

FIG. 7 is a schematic cross-sectional view taken along line B-B of FIG. 3;

FIG. 8 is an enlarged partial view of the structure at C in FIG. 7;

FIG. 9 is an enlarged partial view of FIG. 7 at D;

fig. 10 is a schematic diagram of the structure of fig. 7 before the second spacer and the third spacer are formed.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only one component embodiments of the present application, and not all groups of embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The embodiment of the application provides a display panel and a display module. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.

Referring to fig. 1 to 3, an embodiment of the present application provides a display panel, including a display area AA and a non-display area AZ adjacent to the display area AA, where the display panel includes an array substrate, where the array substrate includes a plurality of first thin film transistors 20 located in the display area AA, and at least one second thin film transistor 10 located in the non-display area AZ, a plurality of test terminals 30 and a plurality of test traces, and one of the test terminals 30 is connected to the second thin film transistor 10 through one of the test traces; the array substrate further comprises a substrate layer 1, a metal layer 2 arranged on the substrate layer 1, and an insulating layer 3 stacked with the metal layer 2, wherein the metal layer 2 comprises the test terminal 30 and the test trace, and the insulating layer 3 comprises a plurality of via holes 40 located in the non-display area AZ; one of the test traces includes a spacer 502, one of the vias 40 is correspondingly disposed above one of the spacers 502, and a projection of the spacer 502 on the substrate layer 1 is located within a range of the via 40.

It is understood that in the panel display industry, a pixel circuit includes a plurality of Thin Film Transistors (TFTs), the quality of each TFT determines the quality of a product, and at present, the electrical performance of the TFTs in the pixel circuit or the driving circuit is observed mainly by designing the TFTs in the non-display region, which are the same as the pixel circuit, and measuring the electrical curve of the TFTs in the non-display region by using an electrical measuring device. However, in the preparation process of the array substrate, because the test terminal is exposed, Static electricity may be introduced into the TFT through the test terminal due to electrostatic Discharge (ESD) in the subsequent process, which causes a change in electrical characteristics of the TFT, and the measured electrical performance of the TFT may not truly reflect the electrical performance of the TFT in the pixel circuit, which is not beneficial to detecting and improving the abnormal TFT in the pixel circuit, in the embodiment of the present application, by dividing the spacing section 502 in the test trace connecting the second thin film transistor 10 and the test terminal 30, the via hole 40 located above the spacing section 502 is provided on the insulating layer 3, which is convenient to keep the test trace disconnected at the position of the spacing section 502 during the manufacturing process of the array substrate, and prevent Static electricity from being introduced to the second thin film transistor 10 through the test terminal 30, after the metal layer 2 and the insulating layer 3 in the array substrate are manufactured, the spacer 502 can be manufactured at the via hole 40 to conduct the test trace, so that the second thin film transistor 10 is communicated with the test terminal 30, and the test of the electrical property of the second thin film transistor 10 by static electricity is effectively avoided.

It should be noted that, referring to fig. 4 to 10, when the array substrate is manufactured to the metal layer 2 and the insulating layer 3, the test trace is always kept disconnected at the position of the spacer 502, that is, when the test trace is manufactured, the spacer 502 is not manufactured, so that the second thin film transistor 10 and the test terminal 30 are disconnected, and after the array substrate is manufactured to the metal layer 2 and the insulating layer 3, the spacer 502 is manufactured at the via hole 40 to turn on the test trace, so as to achieve communication between the second thin film transistor 10 and the test terminal 30; the via hole 40 is located above the spacer 502, and the projection of the spacer 502 on the substrate layer 1 is located within the range of the via hole 40, which is equivalent to that the via hole 40 can completely expose the spacer 502, so that after the fabrication of the metal layer 2 and the insulating layer 3 of the array substrate is completed, the spacer 502 is fabricated at the via hole 40 to conduct the test trace, and the disconnection of the test trace at the spacer 502 due to the too small via hole 40 can be avoided.

It should be noted that the insulating layer 3 further includes a through hole 60 located above the test terminal 30, and the through hole 60 exposes the test terminal 30 to facilitate the probe of the electrical measurement device to contact with the test terminal 30 for electrical signal testing.

In some embodiments, referring to fig. 2-3, the plurality of test traces includes a first test trace 51, a second test trace 52, and a third test trace 53, and the plurality of test terminals 30 includes a first test terminal 301, a second test terminal 302, and a third test terminal 303; one end of the first test trace 51 is connected to the first test terminal 301, the other end of the first test trace is connected to the test gate 101 of the second thin film transistor 10, one end of the second test trace 52 is connected to the second test terminal 302, the other end of the second test trace is connected to the test source 102 of the second thin film transistor 10, one end of the third test trace 53 is connected to the third test terminal 303, and the other end of the third test trace is connected to the test drain 103 of the second thin film transistor 10; the metal layer 2 includes a first metal layer 21 and a second metal layer 22 located on a side of the first metal layer 21 away from the substrate layer 1, where the first metal layer 21 includes the test gate 101 and the first test trace 51, and the second metal layer 22 includes the test source 102, the test drain 103, the second test trace 52 and the third test trace 53; wherein the first test trace 51 includes a first spacer 512, the second test trace 52 includes a second spacer 522, the third test trace 53 includes a third spacer 532, and the plurality of vias 40 includes a first via 41 located above the first spacer 512, a second via 42 located above the second spacer 522, and a third via 43 located above the third spacer 532.

It can be understood that, the first metal layer 21 and the second metal layer 22 are sequentially stacked on the substrate layer 1, the insulating layer 3 and the metal layer 2 are sequentially stacked, the first metal layer 21 includes the test gate 101 and the first test trace 51, the second metal layer 22 includes the test source 102, the test drain 103, the second test trace 52 and the third test trace 53, one end of the first test trace 51 is connected to the first test terminal 301, the other end of the first test trace is connected to the test gate 101, one end of the second test trace 52 is connected to the second test terminal 302, the other end of the second test trace is connected to the test source 102, one end of the third test trace 53 is connected to the third test terminal 301, the other end of the third test trace is connected to the test drain 103, the insulating layer 3 includes the first via 41, the second via 41, and the third via 512 located above the first spacing section 512, After the metal layer 2 and the insulating layer 3 are manufactured, the first spacer 512 is manufactured at the first via hole 41 to achieve conduction of the first test trace 51, the second spacer 522 is manufactured at the second via hole 42 to achieve conduction of the second test trace 52, and the third spacer 532 is manufactured at the third via hole 43 to achieve conduction of the third test trace 53, so that communication between the test gate 101 and the first test terminal 301, communication between the test source 102 and the second test terminal 302, and communication between the test drain 103 and the third test terminal 303 are achieved.

Optionally, the first metal layer 21 includes the first test terminal 301, and the second metal layer 22 includes the second test terminal 302 and the third test terminal 303, that is, the test gate 101, the first test terminal 301 and the first test trace 51 are disposed in the same layer, and the test source 102, the test drain 103, the second test terminal 302, the third test terminal 303, the second test trace 52 and the third test trace 53 are disposed in the same layer.

It should be noted that a projection of the second metal layer 22 on the substrate layer 1 is completely misaligned with a projection of the first test terminal 301 on the substrate layer 1, so that an opening does not need to be designed on the second metal layer 22 to expose the first test terminal 301.

In some embodiments, with continued reference to fig. 2, the insulating layer 3 includes a first insulating sublayer on the side of the second metal layer 22 remote from the substrate layer 1, the second via 42 passes through the first insulating sublayer, and the third via 43 passes through the first insulating sublayer.

It can be understood that the first metal layer 21, the second metal layer 22 and the first insulating sub-layer are sequentially disposed on the substrate layer 1, the second via 42 passes through the first insulating sub-layer, after the metal layer 2 and the insulating layer 3 are fabricated, the second spacer 522 is fabricated at the second via 42 to achieve conduction of the second test trace 52, so as to achieve communication between the test source 102 and the second test terminal 302, the third via 43 passes through the first insulating sub-layer, and after the metal layer 2 and the insulating layer 3 are fabricated, the third spacer 532 is fabricated at the third via 43 to achieve conduction of the third test trace 53, so as to achieve communication between the test drain 103 and the third test terminal 303.

Optionally, the first insulating sublayer includes a passivation layer 32 and a planarization layer 33.

Note that the first via 41 also passes through the first insulating sublayer.

In some embodiments, with continued reference to fig. 2, the insulating layer 3 further includes a second insulating sublayer 31 located between the second metal layer 22 and the first metal layer 21, and the first via 41 passes through the first insulating sublayer and the second insulating sublayer 31.

It can be understood that the first metal layer 21, the second insulating sublayer 31, the second metal layer 22 and the first insulating sublayer are sequentially disposed on the substrate layer 1, the first metal layer 21 includes the test gate 101 and the first test trace 51, the second metal layer 22 includes the test source 102, the test drain 103, the second test trace 52 and the third test trace 53, the first via 41 passes through the first insulating sublayer and the second insulating sublayer 31, the second via 42 passes through the first insulating sublayer, the third via 43 passes through the first insulating sublayer, after the metal layer 2 and the insulating layer 3 are fabricated, the first spacer 512 is fabricated at the first via 41 to achieve conduction of the first test 51, and the second spacer 522 is fabricated at the second via 42 to achieve conduction of the second test 52, the third spacing section 532 is formed at the third via hole 43 to realize the conduction of the third test trace 53, so as to realize the communication between the test gate 101 and the first test terminal 301, the communication between the test source 102 and the second test terminal 302, and the communication between the test drain 103 and the third test terminal 303.

Optionally, the array substrate further includes an active layer. The active layer may be located on a side of the first metal layer 21 away from the substrate layer 1, that is, the active layer is located between the first metal layer 21 and the second metal layer 22, and the second thin film transistor 10 is a bottom gate structure; the active layer may be located on a side of the first metal layer 21 close to the substrate layer 1, that is, the active layer is located between the first metal layer 21 and the substrate layer 1, and the second thin film transistor 10 has a top gate structure.

In some embodiments, referring to fig. 4 and 7, a test trace further includes a first section and a second section, the spacer 502 is connected to the first section at one end and to the second section at the other end, and the spacer 502 covers a portion of the first section and a portion of the second section.

It can be understood that, the first segment is connected to the second tft 10 at one end and the other end is connected to the spacer segment 502, the second segment is connected to the test terminal 30, and the other end is connected to one end of the spacer segment 502 away from the first segment, or the first segment is connected to the test terminal 30 at one end and the other end is connected to the spacer segment 502 at one end, the second segment is connected to the second tft 10 at the other end is connected to one end of the spacer segment 502 away from the first segment, so as to achieve communication between the test terminal 30 and the second tft 10, and the spacer segment 502 covers a part of the first segment and a part of the second segment, which can avoid the wire break of the test trace at the position of the spacer segment 502.

Specifically, the plurality of test traces include a first test trace 51, a second test trace 52 and a third test trace 53, the plurality of test terminals 30 include a first test terminal 301, a second test terminal 302 and a third test terminal 303, one end of the first test trace 51 is connected to the first test terminal 301, the other end of the first test trace is connected to the test gate 101 of the second thin film transistor 10, one end of the second test trace 52 is connected to the second test terminal 302, the other end of the second test trace is connected to the test source 102 of the second thin film transistor 10, one end of the third test trace 53 is connected to the third test terminal 303, and the other end of the third test trace 53 is connected to the test drain 103 of the second thin film transistor 10; the first test wire 51 includes a first terminal connection segment 511, a first spacing segment 512, and a first TFT connection segment 513, the first spacing segment 512 covers a part of the first terminal connection segment 511 and a part of the first TFT connection segment 513, the second test wire 52 includes a second terminal connection segment 521, a second spacing segment 522, and a second TFT connection segment 523, the second spacing segment 522 covers a part of the second terminal connection segment 521 and a part of the second TFT connection segment 523, the third test wire 53 includes a third terminal connection segment 531, a third spacing segment 532, and a third TFT connection segment 533, and the third spacing segment 532 covers a part of the third terminal connection segment 531 and a part of the third TFT connection segment 533.

In some embodiments, referring to fig. 5, 8 and 9, along the extending direction of the test trace, the length of the overlapping portion of the spacer 502 and the first segment is 3um to 8um, and the length of the overlapping portion of the spacer 502 and the second segment is 3um to 8 um.

It can be understood that the projection of the spacing segment 502 on the substrate layer 1 coincides with the projection of the first segment on the substrate layer 1, the projection of the spacing segment 502 on the substrate layer 1 coincides with the projection of the second segment on the substrate layer 1, and follows in the direction that the test routing extends, the spacing segment 502 with the length of the first segment overlapping part is 3um ~ 8um, the spacing segment 502 with the length of the second segment overlapping part is 3um ~ 8um, can realize the spacing segment 502 with the effective overlap joint of the first segment and the spacing segment 502 with the effective overlap joint of the second segment. When the length of the overlapping portion of the spacer 502 and the first segment is less than 3um or the length of the overlapping portion of the spacer 502 and the second segment is less than 3um, the conduction of the test trace is affected by the problem that the spacer 502 and the first segment may have poor overlapping or even disconnection due to errors of the manufacturing process or the problem that the spacer 502 and the second segment may have poor overlapping or even disconnection due to errors of the manufacturing process; when the length of the overlapped portion of the spacer 502 and the first segment is greater than 8um or the length of the overlapped portion of the spacer 502 and the second segment is greater than 8um, because the projection of the spacer 502 on the substrate layer 1 is located in the range of the via hole 40, the longer the length of the overlapped portion of the spacer 502 and the first segment is or the longer the length of the overlapped portion of the spacer 502 and the second segment is, the larger the open area of the via hole 40 is, the impact strength of the display panel is reduced, and the quality of the display panel is affected. Therefore, along in the direction that the test was walked the line and is extended, interval 502 with first section overlap's length is 3um ~ 8um, interval 502 with second section overlap's length is 3um ~ 8 um.

Specifically, referring to fig. 5, 8 and 9, along the extending direction of the test trace, the length of the overlapping portion of the first spacing segment 512 and the first TFT connecting segment 513 is L1, the length of the overlapping portion of the first spacing segment 512 and the first terminal connecting segment 511 is L2, the length of the overlapping portion of the second spacing segment 522 and the second TFT connecting segment 521 is L3, the length of the overlapping portion of the second spacing segment 522 and the second terminal connecting segment 523 is L4, the length of the overlapping portion of the third spacing segment 532 and the third terminal connecting segment 531 is L5, and the length of the overlapping portion of the third spacing segment 532 and the third TFT connecting segment 533 is L6, that is, L1 is equal to or less than 8um 3um, L2 is equal to or less than 8um 3um is equal to or less than 5, L4 um 3um is equal to or less than 35 um 3um 6 is equal to or less than 8um 3um 4838 um 3um is equal to or less than 8um 6 um 3 um.

In some embodiments, referring to fig. 5, 8 and 9, the material of the first segment is the same as the material of the second segment and the material of the first segment is different from the material of the spacer segment 502.

It can be understood that, in the manufacturing process of the array substrate, the test trace is not manufactured with the spacer 502 at the position of the spacer 502, only the first section and the second section of the test trace are manufactured, after the metal layer 2 and the insulating layer 3 are manufactured, the spacer 502 is manufactured at the via hole 40 to conduct the test trace, so as to achieve the communication between the second thin film transistor 10 and the test terminal 30, and the first section and the spacer 502 are manufactured through two processes, which use different materials, so that the material of the first section is different from the material of the spacer 502.

It should be noted that, in the manufacturing process of the array substrate, the first section and the second section of the test trace are manufactured simultaneously with the test terminal 30, the first section and the test terminal 30 may be made of the same material, and the material of the first section includes one or more of Al, Mo, and Cu.

In some embodiments, referring to fig. 2 and 4, the display panel further includes a third metal layer, the third metal layer includes a plurality of electrodes 701, and the material of the electrodes 701 is the same as the material of the spacers 502.

It can be understood that the display panel further includes the third metal layer, the third metal layer is located on the array substrate, the third metal layer includes a plurality of electrodes 701, and the electrodes 701 and the spacers 502 can be manufactured through the same process, so that the spacers 502 can be manufactured by arranging a plurality of vias 40 on the insulating layer 3 and changing a process of manufacturing the electrodes 701 on the basis of an existing panel manufacturing process in the embodiment of the present application, and the manufacturing process of the spacers 502 is simple and does not increase additional design cost.

Optionally, the materials of the electrode 701 and the spacer 502 both include silver.

In some embodiments, referring to fig. 2, the first metal layer 21 further includes a metal gate 201 of the first thin film transistor 20, and the second metal layer 22 further includes a metal source 202 and a metal drain 203 of the first thin film transistor 20.

It is understood that the first metal layer 21 and the second metal layer 22 are sequentially disposed on the substrate layer 1, the first metal layer 21 includes the metal gate 201 located in the display area AA and the test gate 101 located in the non-display area AZ, the second metal layer 22 includes the metal source 202 and the metal drain 203 located in the display area AA and the test source 102 and the test drain 103 located in the non-real area, the first thin film transistor 20 and the second thin film transistor 10 are simultaneously fabricated, and the metal gate 201 of the first thin film transistor 20 and the test gate 101 of the second thin film transistor 10 are fabricated, the metal source 202 and the metal drain 203 of the first thin film transistor, and the test source 102 and the test drain 103 of the second thin film transistor 10 are fabricated in the same layer, equivalent to the first thin film transistor 20 and the second thin film transistor 10, the electrical performance parameter of the first thin film transistor 20 can be obtained by measuring the electrical performance parameter of the second thin film transistor 10.

In some embodiments, referring to fig. 2-10, the method for manufacturing the display panel includes the following steps:

providing the substrate layer 1, wherein the display panel comprises the display area AA and the non-display area AZ;

forming the metal layer 2 and the insulating layer 3 on the substrate layer 1, where the metal layer 2 includes the plurality of test terminals 30, a plurality of test traces, and at least one second thin film transistor 10 located in the non-display area AZ, and the insulating layer 3 includes a plurality of via holes 40 located in the non-display area AZ, where one of the test traces includes an opening, one of the via holes 40 is located above one of the openings, and the opening is within a range of the via hole 40.

Specifically, referring to fig. 2 to fig. 3, the metal layer 2 and the insulating layer 3 are formed on the substrate layer 1, where the metal layer 2 includes the plurality of test terminals 30 located in the non-display area AZ, a plurality of test traces, and at least one second thin film transistor 10, one of the test terminals 30 is connected to the second thin film transistor 10 through one of the test traces, and one of the test traces includes one of the openings, that is, the test trace is disconnected at the opening, which is equivalent to that there is no communication between the second thin film transistor 10 and the test terminal 30; the insulating layer 3 comprises a plurality of the vias 40, one of the vias 40 is located above one of the openings, and the opening is within the range of the via 40.

The spacer 502 is formed within the via 40, and the spacer 502 covers the opening.

Specifically, referring to fig. 4 to fig. 10, the spacer 502 is formed in the via hole 40, and the spacer 502 covers the opening, which is equivalent to that the spacer 502 is prepared in the via hole 40 to achieve conduction of the test trace, that is, to complete communication between the second thin film transistor 10 and the test terminal 30.

The embodiment of the application provides a display module, and the display module comprises the display panel of any one of the above embodiments.

It can be understood that the display module includes the display panel of any of the above embodiments, and the display panel further includes a supporting layer, a buffer layer, a polarizing layer, and the like, and the supporting layer, the buffer layer, and the polarizing layer can refer to the prior art and are not described herein again.

In the embodiment of the application, the interval section is marked off in the test wiring connecting the second thin film transistor and the test terminal, the via hole positioned above the interval section is formed in the insulating layer, the test wiring is conveniently kept to be disconnected at the interval section position in the manufacturing process of the array substrate, static electricity is prevented from being led into the second thin film transistor through the test terminal, after the metal layer and the insulating layer in the array substrate are manufactured, the interval section can be manufactured at the via hole to enable the test wiring to be conducted, communication between the second thin film transistor and the test terminal is realized, and the test of the static electricity on the electrical property of the second thin film transistor is effectively avoided.

The foregoing embodiments have been described in detail, and specific examples are used herein to explain the principles and implementations of the present application, where the above description of the embodiments is only intended to help understand the method and its core ideas of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A display panel is characterized by comprising a display area and a non-display area adjacent to the display area, wherein the display panel comprises an array substrate, the array substrate comprises a plurality of first thin film transistors positioned in the display area, at least one second thin film transistor positioned in the non-display area, a plurality of test terminals and a plurality of test wires, and one test terminal is connected with the second thin film transistor through one test wire;

the array substrate further comprises a substrate layer, a metal layer arranged on the substrate layer and an insulating layer arranged in a stacking mode with the metal layer, the metal layer comprises the test terminal and the test wiring, and the insulating layer comprises a plurality of through holes located in the non-display area;

the test wiring comprises a spacing section, the through hole is correspondingly arranged above the spacing section, and the projection of the spacing section on the substrate layer is located in the range of the through hole.

2. The display panel of claim 1, wherein the plurality of test traces includes a first test trace, a second test trace, and a third test trace, and the plurality of test terminals includes a first test terminal, a second test terminal, and a third test terminal;

one end of the first testing wire is connected with the first testing terminal, the other end of the first testing wire is connected with the testing grid electrode of the second thin film transistor, one end of the second testing wire is connected with the second testing terminal, the other end of the second testing wire is connected with the testing source electrode of the second thin film transistor, one end of the third testing wire is connected with the third testing terminal, and the other end of the third testing wire is connected with the testing drain electrode of the second thin film transistor;

the metal layer comprises a first metal layer and a second metal layer which is positioned on one side of the first metal layer far away from the substrate layer, the first metal layer comprises the test grid and the first test wire, and the second metal layer comprises the test source, the test drain, the second test wire and the third test wire;

the first test routing comprises a first spacing segment, the second test routing comprises a second spacing segment, the third test routing comprises a third spacing segment, and the plurality of via holes comprise a first via hole positioned above the first spacing segment, a second via hole positioned above the second spacing segment, and a third via hole positioned above the third spacing segment.

3. The display panel of claim 2, wherein the insulating layer comprises a first insulating sublayer on a side of the second metal layer remote from the substrate layer, wherein the second via passes through the first insulating sublayer, and wherein the third via passes through the first insulating sublayer.

4. The display panel according to claim 3, wherein the insulating layer 3 further comprises a second insulating sublayer located between the second metal layer and the first metal layer, and the first via passes through the first insulating sublayer and the second insulating sublayer.

5. The display panel of claim 1 wherein a test trace further includes a first segment and a second segment, the spacer has one end connected to the first segment and the other end connected to the second segment, and the spacer covers a portion of the first segment and a portion of the second segment.

6. The display panel of claim 5, wherein along the direction in which the test trace extends, the length of the overlapping portion of the spacer and the first segment is 3um to 8um, and the length of the overlapping portion of the spacer and the second segment is 3um to 8 um.

7. The display panel of claim 5, wherein the material of the first segment is the same as the material of the second segment, and the material of the first segment is different from the material of the spacer segment.

8. The display panel of claim 1, further comprising a third metal layer comprising a plurality of electrodes of the same material as the spacer.

9. The display panel according to claim 2, wherein the first metal layer further comprises a metal gate of the first thin film transistor, and wherein the second metal layer further comprises a metal source and a metal drain of the first thin film transistor.

10. A display module comprising the display panel according to any one of claims 1 to 9.

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