CN113421908A - Display panel, preparation method thereof and display device - Google Patents

Abstract

The embodiment of the invention provides a display panel, a preparation method thereof and a display device. The display panel comprises a display area and an array detection area located on one side of the display area, wherein the array detection area comprises a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on one side, far away from the substrate, of the at least one detection pin and a covering layer arranged on one side, far away from the substrate, of the inorganic layer, and the orthographic projection of the inorganic layer on the substrate and the orthographic projection of the at least one detection pin on the substrate are at least partially overlapped.

Description

Display panel, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.

Background

An Organic Light Emitting Diode (OLED) display is one of the hot spots in the research field of displays. Compared with a Liquid Crystal Display (LCD for short), the OLED Display has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like.

Currently, the OLED display panel can be manufactured by using an Oxide (Oxide) Thin Film Transistor (TFT) process technology. Generally, in an OLED display panel manufactured by using an oxide thin film transistor process technology, a type of a thin film transistor in a pixel driving circuit chip of the OLED display panel may be a P-type or an N-type, but no matter whether the P-type or the N-type thin film transistor is selected to realize the pixel driving circuit chip, a current of an organic light emitting diode changes along with a threshold voltage offset of the driving transistor, so that the OLED display panel generates a Mura phenomenon of non-uniform display brightness, and further, the brightness uniformity and the brightness constancy of the OLED display panel are affected.

In an Array process of an OLED display panel, AT (Array Tester) detects a formed Driving Thin Film Transistor (DTFT) and pixels in an AA Area (active Area) and feeds back information such as defect type, number, and position to a production line, thereby monitoring and improving the process of the Array process, and achieving the purpose of improving yield.

Disclosure of Invention

The embodiment of the invention provides a display panel, a preparation method thereof and a display device, which are used for avoiding the display problems of poor mosaic lines and the like of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including a display area and an array detection area located on one side of the display area, where the array detection area includes a substrate, at least one detection pin disposed on one side of the substrate, an inorganic layer disposed on one side of the at least one detection pin away from the substrate, and a cover layer disposed on one side of the inorganic layer away from the substrate, and an orthographic projection of the inorganic layer on the substrate at least partially overlaps with an orthographic projection of the at least one detection pin on the substrate.

In an exemplary embodiment, the at least one detection pin is arranged on the substrate to form at least one detection pin row, and an orthogonal projection of the at least one detection pin row on the substrate is located in an orthogonal projection of the inorganic layer on the substrate.

In an exemplary embodiment, the display device further includes a first binding region, the first binding region is located between the array detection region and the display region, the first binding region includes at least one binding pin, and the at least one binding pin is connected to the at least one detection pin.

In an exemplary embodiment, the detection pin row at least includes a first end, the first end is located at an end of the detection pin row near the first bonding region, the inorganic layer at least includes a first edge, the first edge is located at a side of the inorganic layer near the first bonding region, and an orthogonal projection of the first edge on the substrate is located at a side of the first end of the detection pin row near the first bonding region in an orthogonal projection of the substrate.

In an exemplary embodiment, a distance between an orthographic projection of the first edge on the substrate and an orthographic projection of the first end of the row of detection pins on the substrate is not less than 30 um.

In an exemplary embodiment, an orthogonal projection of the inorganic layer on the substrate does not overlap an orthogonal projection of the first binding region on the substrate, and a distance between a first edge of the inorganic layer on the orthogonal projection of the substrate and an edge of the first binding region on a side close to the first edge on the orthogonal projection of the substrate is not less than 5 um.

In an exemplary embodiment, the display device further comprises a second binding region located at a side of the array detection region away from the display region.

In an exemplary embodiment, the detection pin row at least includes a second end, the second end is located at one end of the detection pin row near the second bonding region, the inorganic layer at least includes a second edge, the second edge is located at one side of the inorganic layer near the second bonding region, and an orthogonal projection of the second edge on the substrate is located at one side of the second end of the detection pin row near the second bonding region.

In an exemplary embodiment, a distance between the orthographic projection of the second edge on the substrate and the orthographic projection of the second end of the row of detection pins on the substrate is 22um to 27 um.

In an exemplary embodiment, an orthogonal projection of the inorganic layer on the substrate does not overlap an orthogonal projection of the second binding region on the substrate, and a distance between an orthogonal projection of the second edge of the inorganic layer on the substrate and an orthogonal projection of an edge of the second binding region near the second edge on the substrate is not less than 5 um.

In an exemplary embodiment, the display device further includes a driving circuit chip, the driving circuit chip includes at least an output end and an input end, the output end of the driving circuit chip is bound to the first binding region, and the input end of the driving circuit chip is bound to the second binding region.

In an exemplary embodiment, an orthogonal projection of the driving circuit chip on the substrate and an orthogonal projection of the at least one detection pin row on the substrate at least partially overlap.

In an exemplary embodiment, the at least one detection pin row includes at least a first side and a second side that are oppositely disposed, the inorganic layer includes a third edge and a fourth edge that are oppositely disposed, the third edge is located at a side of the inorganic layer close to the first side, the fourth edge is located at a side of the inorganic layer close to the second side, an orthographic projection of the third edge of the inorganic layer on the substrate is located at a side of the first side that is orthographic projection of the substrate away from the at least one detection pin row; and/or the orthographic projection of the fourth edge of the inorganic layer on the substrate is positioned on one side of the orthographic projection of the second side on the substrate, which is far away from the at least one detection pin row.

In an exemplary embodiment, a distance between an orthographic projection of the third edge of the inorganic layer on the substrate and an orthographic projection of the first side on the substrate is not less than 100 um; and/or the distance between the orthographic projection of the fourth edge of the inorganic layer on the substrate and the orthographic projection of the second side on the substrate is not less than 100 um.

In an exemplary embodiment, a surface of the inorganic layer on a side away from the substrate is not higher than a surface of the driving circuit chip on a side close to the substrate.

In a second aspect, an embodiment of the present invention provides a display device, including the foregoing display panel.

In a third aspect, an embodiment of the present invention provides a method for manufacturing a display panel, including:

forming at least one detection pin on a substrate;

performing array detection through the at least one detection pin;

an inorganic layer formed on the side of the at least one detection pin away from the substrate; the orthographic projection of the inorganic layer on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin on the substrate;

and forming a covering layer on the side of the inorganic layer far away from the substrate.

The invention provides a display panel, a preparation method thereof and a display device.

Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the embodiments of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.

FIG. 1 is a first top view of a display panel according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of an array detection area in a display panel according to an embodiment of the present invention;

FIG. 3 is an enlarged view of an array detection area in a display panel according to an embodiment of the present invention;

fig. 4 is a second top view of the display panel according to the embodiment of the invention.

Detailed Description

The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The detection of the display Panel (Panel) mainly includes array detection (AT) and box-to-box process detection (ET). For COP (Chip on PI) products, array detection may be used to detect whether an array substrate of a display panel has defects. In the detection, a voltage is applied to the pixels by using the array detection area, electron signals are generated by emitting electron beams to the pixels, and the defects of the array substrate can be judged by detecting the electron signals.

With the increasing of the pixel density of the display panel, the data routing density in the display panel is increasing, and the routing density of the array detection is also increasing, because the array detection is used as the electrical test of the array process section, the bad abnormal monitoring and the bad improvement evaluation of the process section are ensured, which means that the higher the frequency of the array detection for the data routing test is, the higher the monitoring accuracy for the performance of the display panel is. But the trace density of the array detection increases, further exacerbating the MDL process risk.

The research of the inventor of the application discovers that the detection pins in the array detection area are covered by the flat layer, and the thickness of the flat layer on the detection pins is thin due to the process of preparing the flat layer, so that the conductive gold balls can pierce the flat layer covered on the detection pins in the process of carrying out the MDL Bonding process, the conductive gold balls are in contact with the detection pins, the adjacent detection pins are in short circuit, and the display area is poor in mosaic lines. Meanwhile, due to the influence of the MDL Bonding process, protection cannot be performed by increasing the thickness of the flat layer, otherwise the binding of the driving circuit is influenced.

The embodiment of the invention provides a display panel, which comprises a display area and an array detection area positioned on one side of the display area, wherein the array detection area comprises a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on one side, far away from the substrate, of the at least one detection pin, and a covering layer arranged on one side, far away from the substrate, of the inorganic layer, and the orthographic projection of the inorganic layer on the substrate and the orthographic projection of the at least one detection pin on the substrate are at least partially overlapped.

FIG. 1 is a first top view of a display panel according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of an array detection area in a display panel according to an embodiment of the invention. Take fig. 2 as an example of a cross-sectional view along a-a' in fig. 1. As shown in fig. 1 and 2, the display panel according to the embodiment of the invention includes a display area 10 and an array detection area 200 located at one side of the display area 100 in a direction parallel to the display panel. In a direction perpendicular to the display panel, the array detection region 200 includes a substrate 1, a structural film 6 disposed on one side of the substrate 1, at least one detection pin 2 disposed on one side of the structural film 6 away from the substrate 1, an inorganic layer 3 disposed on one side of the at least one detection pin 2 away from the substrate 1, and a cover layer 4 disposed on one side of the inorganic layer 3 away from the substrate 1, wherein an orthographic projection of the inorganic layer 3 on the substrate 1 and an orthographic projection of the at least one detection pin 2 on the substrate 1 at least partially overlap.

In an exemplary embodiment, the array test area 200 is used to test whether a defect exists in an array substrate of a display panel. In the detection, the array detection area 200 is used for applying voltage to the sub-pixels, the sub-pixels emit electron beams to generate electron signals, and the defects of the array substrate are judged by detecting the electron signals. The array test area 200 is electrically connected to signal leads in the display panel, and specifically, the signal lead of each row of pixels is connected to one test pin 2 in the array test area 200. The signal leads in the display panel may be data leads in the display area 100.

According to the display panel provided by the embodiment of the invention, the inorganic layer 3 is formed on the detection pin 2, so that the inorganic layer 3 can block the conductive metal ball 7 in the binding process of the driving circuit chip, and the display problems that the detection pin 2 is short-circuited to cause poor mosaic lines and the like in the display area 100 due to the contact between the conductive metal ball 7 and the detection pin 2 are avoided.

In an exemplary embodiment, the detection pin 2 may be disposed on the same layer as the data lead in the display region, and may be made of the same material through the same manufacturing process. The detection pin 2 may be made of a metal material, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, or the like, and may have a single-layer structure or a multi-layer composite structure.

In an exemplary embodiment, the inorganic layer 3 may be disposed in the same layer as the passivation layer in the display region 100, and may be formed by the same manufacturing process using the same material. The inorganic layer 3 may employ any one or more of SiOx, SiNx, and SiON, and may be a single layer, a multilayer, or a composite layer.

In an exemplary embodiment, the cover layer 4 may be disposed in the same layer as the flat layer in the display area 100, and may be formed by the same manufacturing process using the same material. The cover layer 4 may be made of an organic material such as resin.

In exemplary embodiments, the structural film layer 6 may adopt a single-layer structure or a multi-layer structure. For example, the structural film layer 6 may include at least one of an interlayer dielectric layer, a first gate insulating layer, and a second gate insulating layer. The interlayer dielectric layer in the structural film layer 6 and the interlayer dielectric layer in the display area 100 can be arranged on the same layer and are prepared by the same material and the same preparation method; the first gate insulating layer in the structural film layer 6 may be disposed on the same layer as the first gate insulating layer in the display area 100, and is prepared from the same material by the same preparation method; the second gate insulating layer in the structural film layer 6 may be disposed on the same layer as the second gate insulating layer in the display area 100, and may be prepared from the same material by the same preparation method.

FIG. 3 is an enlarged view of an array detection area in a display panel according to an embodiment of the present invention. Take fig. 3 as an example of an enlarged view of the detection area of the array of fig. 1. In an exemplary embodiment, as shown in fig. 3, the material of the detection pin 2 may be a conductor, for example, a metal. The detection pin 2 extends along a first direction and is formed into a long strip shape; at least one of the sensing pins 2 is arranged in the array sensing region 200 along the second direction to form at least one sensing pin row 5, and the sensing pins 2 in one sensing pin row 5 are insulated from each other. Wherein the first direction intersects the second direction, e.g., the first direction is perpendicular to the second direction.

In an exemplary embodiment, as shown in fig. 1, the orthographic projection of at least one detection pin row 5 on the substrate 1 is located in the orthographic projection of the inorganic layer 3 on the substrate 1, i.e. the inorganic layer 3 covers all the detection pins 2, so that the conductive metal ball can be blocked from contacting any one detection pin 2 to avoid short circuit of the detection pin 2.

In some exemplary embodiments, an orthographic projection of the inorganic layer 3 on the substrate 1 may overlap with an orthographic projection of a portion of the detection pin row 5 on the substrate 1, so that the conductive metal ball can be blocked from contacting a portion of the detection pin 2 to prevent the portion of the detection pin 2 from being shorted.

Fig. 4 is a second top view of the display panel according to the embodiment of the invention. In an exemplary embodiment, as shown in fig. 1 and 4, in a direction parallel to the display panel, the display panel according to an embodiment of the present invention further includes a first bonding region 300, a second bonding region 400, and a driving circuit chip 500, where the driving circuit chip 500 includes at least an output terminal and an input terminal, the output terminal of the driving circuit chip 500 is bonded to the first bonding region 300, and the input terminal of the driving circuit chip 500 is bonded to the second bonding region 400.

In an exemplary embodiment, as shown in fig. 1, in a direction parallel to the display panel, the display panel according to an embodiment of the present invention further includes a flexible circuit board binding region 600, where the flexible circuit board binding region 600 is located on a side of the second binding region 400 away from the display region 100, the flexible circuit board binding region 600 is connected to the second binding region 400, and the flexible circuit board binding region 600 is used for binding with a flexible circuit board, so that an electrical signal output by the flexible circuit board is input to the second binding region 400 through the flexible circuit board binding region 600.

In an exemplary embodiment, as shown in FIG. 1, the first and second binding regions 300 and 400 are located on opposite sides of the array detection zone 200. Specifically, the first bonding area 300 is located between the array detection area 200 and the display area 100, the second bonding area 400 is located on a side of the array detection area 200 away from the display area 100, and an orthogonal projection of the driving circuit chip 500 on the substrate 1 at least partially overlaps an orthogonal projection of the at least one detection pin row 5 on the substrate 1. For example, the orthographic projection of the driving circuit chip 500 on the substrate 1 overlaps the orthographic projection of all the detection pin rows 5 on the substrate 1, so that the driving circuit chip 500 covers the detection pin rows 5, thereby hiding the detection pin rows 5 under the driving circuit chip 500.

In an exemplary embodiment, as shown in fig. 2, when the driving circuit chip 500 is bonded to the first bonding area 300 and the second bonding area 400, the conductive metal ball 7 is easily generated, the conductive metal ball 7 may enter the upper portion of the array detection area 200, and the inorganic layer 3 in the array detection area 200 may block the conductive metal ball 7, so as to avoid the conductive metal ball 7 contacting the detection pin 2, which may cause the detection pin 2 to be short-circuited, which may cause the display area 100 to have display problems such as poor mosaic lines.

In an exemplary embodiment, as shown in fig. 1, the first bonding area 300 includes at least one bonding pin, an output terminal of the at least one bonding pin is connected to a signal lead in the display area, and an input terminal of the at least one bonding pin is connected to the at least one detection pin 2 in a one-to-one correspondence, so that the at least one detection pin 2 can be connected to the signal lead in the display area through the bonding pin of the first bonding area 300. When a circuit test is required, according to the actual circuit test, the corresponding level signal is input from the detection pin 2, and the level signal is input to the corresponding signal lead in the display area through the binding pin in the first binding area 300, so that the detection of the corresponding pixel in the display area is realized.

In an exemplary embodiment, as shown in fig. 3, the detection pin row 5 includes at least a first end 501, the first end 501 is located at an end of the detection pin row 5 close to the first bonding region 300, the inorganic layer 3 includes at least a first edge 301, the first edge 301 is located at a side of the inorganic layer 3 close to the first bonding region 300, an orthogonal projection of the first edge 301 on the substrate 1 is located at a side of the first end 501 of the detection pin row 5 on the orthogonal projection of the substrate 1 close to the first bonding region 300, so that the inorganic layer 3 completely covers the first end 501 of the detection pin row 5.

In an exemplary embodiment, the distance between the front projection of the first edge 301 on the substrate 1 and the front projection of the first end 501 of the detection pin row 5 on the substrate 1 is not less than 30um, so that the conductive metal ball 7 can be blocked more effectively.

In an exemplary embodiment, the orthographic projection of the inorganic layer 3 on the substrate 1 does not overlap with the orthographic projection of the first binding region 300 on the substrate 1, and the distance between the orthographic projection of the first edge 301 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the edge of the first binding region 300 close to the first edge 301 on the substrate 1 is not less than 5um, so that a certain distance is formed between the inorganic layer 3 and the first binding region 300, and the inorganic layer 3 is prevented from obstructing the binding of the driving circuit chip and the first binding region 300.

In an exemplary embodiment, as shown in fig. 3, the detection pin row 5 includes at least a second end 502, and the second end 502 is located at an end of the detection pin row 5 near the second binding area 400. Wherein the second end 502 and the first end 501 are respectively located at two opposite ends of the detection pin row 5. The inorganic layer 3 at least includes a second edge 302, the second edge 302 is located on a side of the inorganic layer 3 close to the second bonding area 400, an orthogonal projection of the second edge 302 on the substrate 1 is located at a second end 502 of the detection pin row 5 on a side of the orthogonal projection of the substrate 1 close to the second bonding area 400, so that the inorganic layer 3 completely covers the second end 502 of the detection pin row 5.

In an exemplary embodiment, the distance between the front projection of the second edge 302 on the substrate 1 and the front projection of the second end 502 of the detection pin row 5 on the substrate 1 is 22um to 27um, so that the conductive metal balls 7 can be blocked more effectively.

In an exemplary embodiment, the orthographic projection of the inorganic layer 3 on the substrate 1 does not overlap with the orthographic projection of the second binding region 400 on the substrate 1, and the distance between the orthographic projection of the second edge 302 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the edge of the second binding region 400 close to the second edge 302 on the substrate 1 is not less than 5um, so that a certain distance is formed between the inorganic layer 3 and the second binding region 400, and the inorganic layer 3 is prevented from obstructing the binding of the driving circuit chip and the second binding region 400.

In an exemplary embodiment, as shown in fig. 3, the detection pin row 5 includes at least a first side 503 and a second side 504 that are oppositely disposed, and the first side 503 and the second side 504 are respectively located at two sides of the detection pin row 5 along the second direction. The inorganic layer 3 comprises a third edge 303 and a fourth edge 304 which are oppositely arranged, the third edge 303 is positioned on the side of the inorganic layer 3 close to the first side 503, the fourth edge 304 is positioned on the side of the inorganic layer 3 close to the second side 504, the orthographic projection of the third edge 303 of the inorganic layer 3 on the substrate 1 is positioned on the side of the orthographic projection of the first side 503 on the substrate 1 away from the detection pin row 5; and/or the fourth edge 304 of the inorganic layer 3 is located on the second side 504 on the side of the substrate 1 that is far away from the detection pin row 5 in the orthographic projection of the substrate 1, so that the inorganic layer 3 covers the first side 503 and/or the second side 504 of the detection pin row 5, thereby ensuring that the inorganic layer 3 can effectively block the electro-metal balls 7.

In an exemplary embodiment, the distance between the orthographic projection of the third edge 303 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the first side 503 on the substrate 1 is not less than 100 um; and/or the distance between the orthographic projection of the fourth edge 304 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the second side 504 on the substrate 1 is not less than 100um, so as to ensure that the inorganic layer 3 can effectively block the electric metal balls 7.

In an exemplary embodiment, a surface of the inorganic layer 3 on a side away from the substrate 1 is not higher than a surface of the driving circuit chip 500 on a side close to the substrate 1, so as to avoid the inorganic layer 3 from blocking the binding of the driving circuit chip 500. For example, the thickness of the inorganic layer 3 is 2000A to 4000A.

In an exemplary embodiment, the inorganic layer 3 may take various shapes, for example, regular or irregular shapes such as a rectangle, a circle, a diamond, a triangle, and a polygon, as long as the orthographic projection of the inorganic layer 3 on the substrate 1 at least partially overlaps with the orthographic projection of the at least one detection pin 2 on the substrate 1. Specifically, taking the inorganic layer 3 as a rectangle as an example, the length of the inorganic layer 3 is 25905 um; the width of the inorganic layer 3 is 400 um.

In an exemplary embodiment, as shown in fig. 1, the display panel of the embodiment of the invention further includes a box test area 700(CT, CellTest) in a direction parallel to the display panel, the box test area 700 is located at a side of the first binding area 300 close to the display area 100, and the box test area 700 is connected to a signal lead in the display area 100 for box testing the display area 100.

The embodiment of the invention also provides a preparation method of the display panel, the display panel comprises a display area and an array detection area positioned on one side of the display area, and the preparation method of the display panel comprises the following steps:

forming at least one detection pin on a substrate;

performing array detection through the at least one detection pin;

an inorganic layer formed on the side of the at least one detection pin away from the substrate; the orthographic projection of the inorganic layer on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin on the substrate;

and forming a covering layer on the side of the inorganic layer far away from the substrate.

In an exemplary embodiment, the sensing pin may be prepared by the same manufacturing process using the same material as the data wire in the display region. The detection pin can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium and the like, and can be of a single-layer structure or a multi-layer composite structure.

In an exemplary embodiment, the inorganic layer may be prepared through the same preparation process using the same material as the passivation layer in the display region. The inorganic layer may adopt any one or more of SiOx, SiNx and SiON, and may be a single layer, a multilayer or a composite layer.

In an exemplary embodiment, the capping layer may be prepared by the same preparation process using the same material as the planarization layer in the display region. The cover layer 4 may be made of an organic material such as resin.

The embodiment of the invention also provides a display device which comprises the display panel. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc.

In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (17)

1. A display panel is characterized by comprising a display area and an array detection area positioned on one side of the display area, wherein the array detection area comprises a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on one side, far away from the substrate, of the at least one detection pin and a covering layer arranged on one side, far away from the substrate, of the inorganic layer, and the orthographic projection of the inorganic layer on the substrate and the orthographic projection of the at least one detection pin on the substrate are at least partially overlapped.

2. The display panel according to claim 1, wherein the at least one detection pin is arranged on the substrate to form at least one detection pin row, and an orthogonal projection of the at least one detection pin row on the substrate is located in an orthogonal projection of the inorganic layer on the substrate.

3. The display panel of claim 2, further comprising a first binding region between the array detection region and the display region, the first binding region comprising at least one binding pin, the at least one binding pin being connected to the at least one detection pin.

4. The display panel according to claim 3, wherein the detection pin row comprises at least a first end, the first end is located at an end of the detection pin row near the first bonding region, the inorganic layer comprises at least a first edge, the first edge is located at a side of the inorganic layer near the first bonding region, and an orthographic projection of the first edge on the substrate is located at a side of the first end of the detection pin row near the first bonding region.

5. The display panel according to claim 4, wherein a distance between a forward projection of the first edge on the substrate and a forward projection of the first end of the detection pin row on the substrate is not less than 30 um.

6. The display panel according to claim 4, wherein the orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the first binding region on the substrate, and a distance between the orthographic projection of the first edge of the inorganic layer on the substrate and the orthographic projection of the first binding region on the side close to the first edge is not less than 5 um.

7. The display panel of claim 3, further comprising a second binding region on a side of the array detection region away from the display region.

8. The display panel of claim 7, wherein the row of detection pins comprises at least a second end, the second end is located at an end of the row of detection pins near the second bonding region, the inorganic layer comprises at least a second edge, the second edge is located at a side of the inorganic layer near the second bonding region, and an orthographic projection of the second edge on the substrate is located at a side of the second end of the row of detection pins near the second bonding region.

9. The display panel of claim 8, wherein the second edge has a distance of 22um to 27um between the orthographic projection of the substrate and the orthographic projection of the second end of the row of detection pins.

10. The display panel of claim 8, wherein the orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the second binding region on the substrate, and a distance between the orthographic projection of the second edge of the inorganic layer on the substrate and the orthographic projection of the second binding region on the substrate near one side edge of the second edge is not less than 5 um.

11. The display panel according to claim 7, further comprising a driving circuit chip, wherein the driving circuit chip comprises at least an output terminal and an input terminal, the output terminal of the driving circuit chip is bonded to the first bonding region, and the input terminal of the driving circuit chip is bonded to the second bonding region.

12. The display panel of claim 11, wherein an orthographic projection of the driving circuit chip on the substrate at least partially overlaps with an orthographic projection of the at least one detection pin row on the substrate.

13. The display panel according to claim 2, wherein the at least one row of detection pins comprises at least a first side and a second side which are oppositely disposed, the inorganic layer comprises a third edge and a fourth edge which are oppositely disposed, the third edge is located on a side of the inorganic layer close to the first side, the fourth edge is located on a side of the inorganic layer close to the second side, and an orthogonal projection of the third edge of the inorganic layer on the substrate is located on a side of the first side where the orthogonal projection of the substrate is far away from the at least one row of detection pins; and/or the orthographic projection of the fourth edge of the inorganic layer on the substrate is positioned on one side of the orthographic projection of the second side on the substrate, which is far away from the at least one detection pin row.

14. The display panel according to claim 13, wherein a distance between an orthographic projection of the third edge of the inorganic layer on the substrate and an orthographic projection of the first side on the substrate is not less than 100 um; and/or the distance between the orthographic projection of the fourth edge of the inorganic layer on the substrate and the orthographic projection of the second side on the substrate is not less than 100 um.

15. The display panel according to claim 11, wherein a surface of the inorganic layer on a side away from the substrate is not higher than a surface of the driving circuit chip on a side close to the substrate.

16. A display device comprising the display panel according to any one of claims 1 to 15.

17. A method for manufacturing a display panel, comprising:

forming at least one detection pin on a substrate;

performing array detection through the at least one detection pin;

an inorganic layer formed on the side of the at least one detection pin away from the substrate; the orthographic projection of the inorganic layer on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin on the substrate;

and forming a covering layer on the side of the inorganic layer far away from the substrate.

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