CN217484785U

CN217484785U - High-precision voltage-stabilized power supply circuit

Info

Publication number: CN217484785U
Application number: CN202221280481.2U
Authority: CN
Inventors: 杨光瑶
Original assignee: Wuxi Chixiang Innovation Technology Co ltd
Current assignee: Wuxi Chixiang Innovation Technology Co ltd
Priority date: 2022-05-25
Filing date: 2022-05-25
Publication date: 2022-09-23
Anticipated expiration: 2032-05-25

Abstract

The utility model belongs to the technical field of integrated chip, specifically provide a high accuracy constant voltage power supply circuit, including high voltage power supply module, power output module, POR start module, elementary voltage division module, one-level reference voltage drive module, voltage reference module and second grade reference voltage drive module, high voltage power supply module, POR start module, elementary voltage division module, one-level reference voltage drive module and second grade reference voltage drive module all connect chip outside high pressure VDD input port, high voltage power supply module passes through power output module and POR start module to be connected, elementary voltage division module, one-level reference voltage drive module, voltage reference module, second grade reference voltage drive module and power output module connect gradually, power output module still connects chip low pressure MOS circuit; the utility model provides a high accuracy constant voltage power supply circuit can guarantee voltage reference's high accuracy nature and stability simultaneously.

Description

High-precision voltage-stabilized power supply circuit

Technical Field

The utility model relates to an integrated chip technical field, more specifically relates to a high accuracy constant voltage power supply circuit.

Background

When designing a chip, because the input voltage is higher, a lower stable voltage source needs to be generated in the chip, and the requirement of the chip is simultaneously satisfied with the power supply of most low-voltage circuits of the chip. However, the conventional voltage-stabilized power supply circuit cannot simultaneously guarantee the high precision and stability of the voltage reference.

Disclosure of Invention

An object of the utility model is to provide a high accuracy constant voltage power supply circuit to the current constant voltage power supply circuit that exists can't guarantee the high accuracy nature and the problem of stability of voltage reference simultaneously among the solution background art.

As a first aspect of the utility model, a high accuracy constant voltage power supply circuit is provided, including high voltage power supply module, power output module, POR start module, elementary partial pressure module, reference voltage drive module and voltage reference module, wherein, reference voltage drive module includes one-level reference voltage drive module and second grade reference voltage drive module, chip outside high pressure VDD input port is all connected to high voltage power supply module, POR start module, elementary partial pressure module, one-level reference voltage drive module and second grade reference voltage drive module, high voltage power supply module still passes through power output module with POR start module connects, elementary partial pressure module, one-level reference voltage drive module, voltage reference module, second grade reference voltage drive module and power output module connect gradually, elementary partial pressure module, POR start module, The POR starting module is connected with the power output module, the first-level reference voltage driving module, the voltage reference module and the second-level reference voltage driving module are connected with the POR starting module, and the power output module is further connected with a chip low-voltage MOS circuit.

Further, the high-voltage power supply module comprises a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a load resistor R0, a first capacitor C1 and a first Zener diode D1, wherein, the grid of the first PMOS pipe PM1 is connected with the grid of the third PMOS pipe PM3, the gate of the first PMOS transistor PM2 is connected to the gate of the third PMOS transistor PM4, the drain electrode of the first PMOS pipe PM1 and the drain electrode of the third PMOS pipe PM3 are both connected with the chip external high-voltage VDD input port, the source of the first PMOS transistor PM1 is connected to the drain of the second PMOS transistor PM2, the source of the second PMOS transistor PM2 is connected to one end of the load resistor R0, the other end of the load resistor R0 is connected to one end of the first capacitor C1 and the anode of the first zener diode D1 respectively, the source of the third PMOS transistor PM3 is connected to the drain of the fourth PMOS transistor PM4, the source electrode of the fourth PMOS transistor PM4 is respectively connected to the other end of the first capacitor C1 and the cathode of the first zener diode D1; the high-voltage power supply module is used for converting a high-voltage power supply VDD input from an external high-voltage VDD input port of the chip into a weak driving voltage source.

Further, the power output module includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a second capacitor C2, and an inverter I1, a source of the fifth PMOS transistor PM5 and a source of the sixth PMOS transistor PM6 are both connected to the weak driving voltage source, a gate of the fifth PMOS transistor PM5 is connected to a POR start signal and an input end of the inverter I1, respectively, the POR start signal includes the VDD start signal and a sleep signal, a drain of the fifth PMOS transistor PM5 is connected to a source of the sixth PMOS transistor PM6 and the second capacitor C2, a gate of the sixth PMOS transistor PM6 is connected to an output end of the inverter I1, and a drain of the sixth PMOS transistor PM6 is connected to the stable voltage source.

Further, the primary voltage dividing module includes a first NMOS 1, a second NMOS 2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a second zener diode D2, one end of the first resistor R1 is connected to the chip external high voltage VDD input port, the other end of the first resistor R1 is connected to one end of the second resistor R2, the drain of the first NMOS NM1, one end of the third capacitor C3, and the negative electrode of the second zener diode D2, the other end of the second resistor R2 is connected to one end of the third resistor R3 and the gate of the first NMOS 1, the other end of the third resistor R3 is connected to one end of a fourth resistor R4, the other end of the fourth resistor R4 is connected to the source of the second NMOS 2, the other end of the third capacitor C3, and the positive electrode of the second zener diode D2, and the source of the second NMOS 1, the gate of the second NMOS transistor NM2 is connected to the sleep signal.

Further, the primary reference voltage driving module and the secondary reference voltage driving module have the same structure, the primary reference voltage driving module or the secondary reference voltage driving module includes a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a fifth resistor R5, a sixth resistor R6, a fourth capacitor C4, and a third zener diode D3, gates of the third and fifth NMOS tubes NM3 and NM5 are both connected to an externally input voltage signal, the voltage signal includes a low voltage reference signal and a reference voltage signal, gates of the third and fifth NMOS tubes NM3 and NM5 of the primary reference voltage driving module are both connected to the low voltage reference signal input by the primary reference voltage module, gates of the third and fifth NMOS tubes NM3 and NM 3638 of the secondary reference voltage driving module are both connected to the reference voltage input module, the drain of the third NMOS transistor NM3 is connected to the source of the seventh PMOS transistor PM7 and the gate of the ninth PMOS transistor PM9, the source of the third NMOS transistor NM3 is connected to the drain of the fifth NMOS transistor NM5 and the source of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5 is connected to the drain of the sixth NMOS transistor NM6 and one end of the sixth resistor R6, the gate of the sixth NMOS transistor NM6 is connected to the sleep signal, the source of the sixth NMOS transistor NM6 is connected to the ground, the drain of the seventh PMOS transistor PM7, the drain of the eighth PMOS transistor PM8 and the drain of the ninth PMOS transistor PM9 are all connected to the chip external VDD high voltage input port, the source of the eighth PMOS transistor PM8 is connected to the gate of the seventh PMOS transistor PM7, the gate of the eighth PMOS transistor PM5 and the drain of the fourth NMOS transistor NM4, the drain of the fourth NMOS transistor NM4 is connected to the fifth end of the fifth PMOS transistor NM4 and the other end of the sixth resistor R5, the ninth resistor R599 and the other end of the ninth resistor R599, the seventh PMOS transistor PM 599, the drain of the seventh PMOS transistor NM 6384 and the drain of the eighth PMOS transistor NM 6342, respectively, and the drain of the eighth PMOS transistor NM9, and the drain of the eighth PMOS transistor NM9, the sixth resistor R9, and the fourth PMOS transistor NM9, and the drain of the fourth PMOS transistor NM9, the sixth resistor R9, the fourth PMOS transistor NM5 are connected to the drain of the fourth resistor R9, The cathode of the third zener diode D3 and one end of the fourth capacitor C4, the anode of the third zener diode D3 is connected to the other end of the fourth capacitor C4;

the primary reference voltage driving module outputs 3-6V voltage to the voltage reference module, the voltage reference module outputs 1.2V reference voltage signals to the secondary reference voltage driving module, and the secondary reference voltage driving module outputs the stable voltage source to the power output module.

Further, the voltage reference module adopts a band gap reference voltage source structure.

Further, the POR startup module includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a seventh NMOS NM7, an eighth NMOS NM8, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a tenth PMOS PM10, an eleventh PMOS PM11, a twelfth PMOS PM12, and a thirteenth PMOS PM13, a gate of the seventh NMOS NM 13 is connected to a power-on completion signal of a high voltage power VDD, a drain of the seventh NMOS NM 13 is connected to one end of the eighth resistor R13 and one end of the ninth resistor R13, another end of the eighth resistor R13 is connected to one end of the seventh resistor R13, one end of the NM 72 of the fifth capacitor C13, and another end of the eighth NMOS 72 of the gate of the eighth NMOS 13, the other end of the seventh resistor R13 is connected to the source of the ninth NMOS 13, and the other end of the seventh NMOS 13 of the gate of the seventh NMOS 13, the seventh NMOS 13 is connected to the external resistor R13 and the ninth NMOS 13, the drain of the tenth PMOS transistor PM10, the drain of the eleventh PMOS transistor PM11, the drain of the twelfth PMOS transistor PM12, and the drain of the thirteenth PMOS transistor PM13 are all connected to a weak driving voltage source or a stable voltage source input by the power output module, the source of the tenth PMOS transistor PM10 is connected to the drain of the tenth NMOS transistor NM10, the gate of the tenth NMOS transistor NM10, the gate of the eleventh NMOS transistor NM11, the gate of the twelfth NMOS transistor NM12, one end of the sixth capacitor C6, and the gate of the ninth NMOS transistor NM9, the source of the tenth NMOS transistor NM10 is connected to the other end of the sixth capacitor C6, the source of the eleventh NMOS transistor NM11, and the source of the twelfth NMOS transistor NM12, the gate of the eleventh PMOS transistor PM11 is connected to the gate of the twelfth PMOS transistor PM12, the source of the eleventh PMOS transistor PM11 is connected to the drain of the eighth NMOS transistor NM8, the source of the twelfth PMOS transistor PM 24 is connected to the drain of the ninth NMOS 9, the ninth capacitor NM 599, the ninth transistor PM 599, and the ninth NMOS 369, the source of the eighth NMOS transistor NM8, the source of the ninth NMOS transistor NM9, and the drain of the eleventh NMOS transistor NM11 are connected, and the source of the thirteenth PMOS transistor PM13 is connected to the other end of the seventh capacitor C7 and the drain of the twelfth NMOS transistor NM12, respectively.

The utility model provides a high accuracy constant voltage power supply circuit has following advantage:

(1) the output voltage of the voltage-stabilized internal power supply can use external high-voltage VDD as input, so that the design problem of a high-precision low-voltage-stabilized source required by the interior of a chip when the chip uses a high-voltage input power supply is solved;

(2) the circuit can be used as an independent pow high-voltage source and used for a chip low-voltage MOS circuit; on the other hand, the stability of the output power supply VDD1 is good, the temperature characteristic and the power supply rejection ratio of the voltage signal of the output power supply VDD1 both meet the requirements of most circuits for reference, and the output power supply VDD1 can be used as a voltage reference signal after the chip low-voltage MOS circuit is electrified;

(3) the voltage of the output stable voltage source VDD1 is adjustable, and the output stable voltage source can be flexibly adjusted according to the resistance setting of the secondary reference voltage driving module so as to adapt to different process requirements of 1.8V, 3V, 5V, 6V and the like; in addition, the circuit can be further improved, and the value is modified by adding a resistance string circuit (resistors R5 and R6 of a secondary reference voltage driving module) controlled by logic so as to meet the requirement of higher precision;

(4) the sleep mode can be entered by using sleep signals, the overall static power consumption is lower than 5uW, and the sleep mode has the characteristics of low power consumption, environmental protection and energy saving.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a schematic block diagram of a high-precision voltage-stabilized power supply circuit provided by the present invention.

Fig. 2 is a circuit diagram of the high voltage power supply module provided by the present invention.

Fig. 3 is a circuit diagram of a power output module provided by the present invention.

Fig. 4 is a circuit diagram of the primary voltage dividing module provided by the present invention.

Fig. 5 is a circuit diagram of the reference voltage driving module provided by the present invention.

Fig. 6 is a circuit diagram of a POR start module provided by the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention for achieving the objects of the present invention, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of the present invention for the specific embodiments, structures, features and effects of the high precision voltage-stabilized power supply circuit according to the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances for purposes of describing the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In the explanation of the present invention, it should be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly unless otherwise specified. For example, the connection may be a fixed connection, a connection through a special interface, or an indirect connection via an intermediate medium. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In this embodiment, a high-precision voltage-stabilized power supply circuit is provided, as shown in fig. 1, the high-precision voltage-stabilized power supply circuit includes a high-voltage power module, a power output module, a POR start module, a primary voltage-dividing module, a reference voltage driving module and a voltage reference module, wherein the reference voltage driving module includes a primary reference voltage driving module and a secondary reference voltage driving module, the high-voltage power module, the POR start module, the primary voltage-dividing module, the primary reference voltage driving module and the secondary reference voltage driving module are all connected to an external high-voltage VDD input port of a chip, the high-voltage power module is further connected to the POR start module through the power output module, the primary voltage-dividing module, the primary reference voltage driving module, the voltage reference module, the secondary reference voltage driving module and the power output module are sequentially connected, the primary voltage division module, the primary reference voltage driving module, the voltage reference module and the secondary reference voltage driving module are all connected with the POR starting module, and the power output module is also connected with a chip low-voltage MOS circuit;

the POR starting module comprises three modes, namely a starting mode, a working mode and a sleeping mode;

starting a mode: the POR starting module detects a high-voltage power supply VDD input from an external high-voltage VDD input port of the chip, when the high-voltage power supply VDD is detected to be powered on and started from 0V, a power-on signal of the POR starting module is generated, and the POR starting module starts to start; then the POR starting module continues to detect the high-voltage power supply VDD, after the high-voltage power supply VDD reaches a rated value (designed 20V, adjustable through a resistor), the POR starting module is powered on and is finished, and the POR starting module enters a stable state;

the working mode is as follows: when the high-voltage power supply VDD is in a normal range, the POR starting module starts a working mode after entering a stable state, and outputs a VDD starting signal to the power output module; after receiving the VDD starting signal, the power output module acquires a stable voltage source from the secondary reference voltage driving module, and outputs the stable voltage source to the POR starting module and the chip low-voltage MOS circuit, respectively, where the POR starting module outputs a stable voltage (designed 4V, adjustable by a resistor);

a sleep mode: the POR starting module outputs a sleep signal to the power output module, the primary voltage division module, the primary reference voltage driving module, the voltage reference module and the secondary reference voltage driving module respectively after detecting that the high-voltage power supply VDD is lower than a preset lowest working voltage, wherein the power output module, the primary voltage division module, the primary reference voltage driving module, the voltage reference module and the secondary reference voltage driving module are all in a sleep mode, at the moment, a stable voltage source circuit is closed, the chip low-voltage MOS circuit is switched off to prevent additional standby power consumption, the power output module receives a weak driving voltage source input by the high-voltage power supply module and outputs the weak driving voltage source to the POR starting module so as to ensure that the POR starting module can generate a normal power-on signal; meanwhile, a turn-off signal is provided for subsequent circuits (a primary voltage division module, a primary reference voltage driving module, a voltage reference module and a secondary reference voltage driving module), and the static power consumption is about 5 uW. The sleep signal may turn off the secondary reference voltage drive module.

Preferably, as shown in fig. 2, the high voltage power supply module includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a load resistor R0, a first capacitor C1, and a first zener diode D1, wherein, the grid of the first PMOS pipe PM1 is connected with the grid of the third PMOS pipe PM3, the gate of the first PMOS transistor PM2 is connected to the gate of the third PMOS transistor PM4, the drain electrode of the first PMOS pipe PM1 and the drain electrode of the third PMOS pipe PM3 are both connected with the chip external high-voltage VDD input port, the source of the first PMOS transistor PM1 is connected to the drain of the second PMOS transistor PM2, the source of the second PMOS transistor PM2 is connected to one end of the load resistor R0, the other end of the load resistor R0 is connected to one end of the first capacitor C1 and the anode of the first zener diode D1 respectively, the source electrode of the third PMOS tube PM3 is connected with the drain electrode of the fourth PMOS tube PM4, the source electrode of the fourth PMOS transistor PM4 is respectively connected to the other end of the first capacitor C1 and the cathode of the first zener diode D1; the high-voltage power supply module is used for converting a high-voltage power supply VDD input from an external high-voltage VDD input port of the chip into a weak driving voltage source.

Specifically, the high-voltage power supply module is mainly responsible for providing a relatively stable power supply with weak driving capability, and is responsible for providing a weak driving voltage source and a power-on reference point for the POR start module through the power output module in a sleep mode (a low power consumption mode adopted when the chip enters a standby sleep state). The part is protected by a high-voltage PMOS current mirror and a Zener diode, and can normally provide output in a range of 24V. In sleep mode, the larger resistor R0 ensures that the loss current of the current mirror is within an acceptable range (standard value of 200 nA), and does not generate excessive burden on the standby power consumption of the chip.

Preferably, as shown in fig. 3, the power output module includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a second capacitor C2, and an inverter I1, a source of the fifth PMOS transistor PM5 and a source of the sixth PMOS transistor PM6 are both connected to the weak driving voltage source, a gate of the fifth PMOS transistor PM5 is respectively connected to a POR enable signal and an input end of the inverter I1, the POR enable signal includes the VDD enable signal and a sleep signal, a drain of the fifth PMOS transistor PM5 is respectively connected to a source of a sixth PMOS transistor PM6 and the second capacitor C2, a gate of the sixth PMOS transistor PM6 is connected to an output end of the inverter I1, and a drain of the sixth PMOS transistor PM6 is connected to the stable voltage source.

Specifically, the power output module is responsible for controlling the regulated voltage source VDD1 that it ultimately outputs.

The power output module obtains a weak driving voltage source VDD-in from the high-voltage power supply module, and in a sleep mode, the power output module outputs the processed weak driving voltage source to the POR starting module so as to ensure that the POR starting module can generate a normal power-on signal; and under the operating condition (when the power output module receives a VDD starting signal), the power output module switches the POR starting module and the chip low-voltage MOS circuit into a stable voltage source VDD1 with high driving capability, so that the chip low-voltage MOS circuit can stably work. The stable voltage source VDD stable in fig. 3 is the vref voltage source (stable voltage source) output by the secondary reference voltage driving module.

Preferably, as shown in fig. 4, the primary voltage dividing module includes a first NMOS tube NM1, a second NMOS tube NM2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a second zener diode D2, one end of the first resistor R1 is connected to the chip external high voltage VDD input port, the other end of the first resistor R1 is connected to one end of the second resistor R2, the drain of the first NMOS tube NM1, one end of the third zener C3, and the negative electrode of the second diode D2, the other end of the second resistor R2 is connected to one end of the third resistor R3 and the gate of the first NMOS tube NM1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the source of the second NMOS tube NM2, the other end of the third capacitor NM6 3, and the positive electrode of the second zener diode D87458, the gate of the second NMOS transistor NM2 is connected to the sleep signal.

Specifically, the primary voltage division module adopts a large resistor R1-R3 and an overvoltage protection zener diode D2 as a starting circuit of the primary reference voltage driving module and a signal source of the voltage reference module, converts and extracts the high-voltage power supply VDD into gentle signals input to the gates of the low-voltage MOS transistors (the gate of the third NMOS transistor NM3 and the gate of the fifth NMOS transistor NM5 in fig. 5) and inputs the gentle signals as low-voltage reference signals (i.e., voltage signal input in fig. 5) to the primary reference voltage driving module. Meanwhile, the loss current in the sleep state is reduced by setting the larger resistor R4.

Preferably, as shown in fig. 5, the primary reference voltage driving module and the secondary reference voltage driving module have the same structure, and the primary reference voltage driving module or the secondary reference voltage driving module includes a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a fifth resistor R5, a sixth resistor R6, a fourth capacitor C4, and a third zener diode D3, gates of the third and fifth NMOS tubes NM3 and NM5 are all connected to an externally input voltage signal, the voltage signal includes a low voltage reference signal and a reference voltage signal, gates of the third and fifth NMOS tubes NM3 and NM5 of the primary reference voltage driving module are both connected to the low voltage reference signal input by the primary voltage dividing module, gates of the third and fifth NMOS tubes NM3 and NM5 of the secondary reference voltage driving module are both connected to the reference voltage input module, the drain of the third NMOS transistor NM3 is connected to the source of the seventh PMOS transistor PM7 and the gate of the ninth PMOS transistor PM9, the source of the third NMOS transistor NM3 is connected to the drain of the fifth NMOS transistor NM5 and the source of the fourth NMOS transistor NM4, the source of the fifth NMOS transistor NM5 is connected to the drain of the sixth NMOS transistor NM6 and one end of the sixth resistor R6, the gate of the sixth NMOS transistor NM6 is connected to the sleep signal, the source of the sixth NMOS transistor NM6 is connected to the ground, the drain of the seventh PMOS transistor PM7, the drain of the eighth PMOS transistor PM8 and the drain of the ninth PMOS transistor PM9 are all connected to the chip external VDD high voltage input port, the source of the eighth PMOS transistor PM8 is connected to the gate of the seventh PMOS transistor PM7, the gate of the eighth PMOS transistor PM5 and the drain of the fourth NMOS transistor NM4, the drain of the fourth NMOS transistor NM4 is connected to the fifth end of the fifth PMOS transistor NM4 and the other end of the sixth resistor R5, the ninth resistor R599 and the other end of the ninth resistor R599, the seventh PMOS transistor PM 599, the drain of the seventh PMOS transistor NM 6384 and the drain of the eighth PMOS transistor NM 6342, respectively, and the drain of the eighth PMOS transistor NM9, and the drain of the eighth PMOS transistor NM9, the sixth resistor R9, and the fourth PMOS transistor NM9, and the drain of the fourth PMOS transistor NM9, the sixth resistor R9, the fourth PMOS transistor NM5 are connected to the drain of the fourth resistor R9, The cathode of the third zener diode D3 and one end of the fourth capacitor C4, and the anode of the third zener diode D3 is connected with the other end of the fourth capacitor C4;

Specifically, the reference voltage driving module adopts a symmetrical matching MOS transistor structure, and the divided voltage generated by the mirror current on the resistors R5 and R6 is used as an input to the power supply driving of the next stage. The primary reference voltage driving module and the secondary reference voltage driving module have the same structure, and are both the circuit structure shown in fig. 5. The voltage output range of the primary reference voltage driving module is 3-6V, and the voltage output of the secondary reference voltage driving module is a stable value (standard value 4VVDD _ stable). The output voltage range of the secondary reference voltage driving module can be modified by changing the resistance values accessed by the resistors R5 and R6.

Preferably, the voltage reference module adopts a band-gap reference voltage source structure, generates a bias independent of a power supply by using transistor characteristics, converts an unstable input power supply (which refers to a 3-6V voltage output by the primary reference voltage driving module) provided by a front port into a 1.2V reference signal with a good power supply rejection ratio, and has good temperature characteristics, wherein the power supply rejection ratio is more than 60 dB. The 1.2V reference signal is sent to the secondary reference voltage driving module, and the secondary reference voltage driving module outputs a stable voltage source VDD stable.

Preferably, as shown in fig. 6, the POR start-up module includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a seventh NMOS NM7, an eighth NMOS NM8, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a tenth PMOS PM10, an eleventh PMOS PM11, a twelfth PMOS PM12 and a thirteenth PMOS PM13, a gate of the seventh NMOS NM 13 is connected to the high voltage power supply VDD power-up completion signal, a drain of the seventh NMOS NM 13 is connected to one end of the eighth resistor R13 and one end of the ninth resistor R13, the other end of the eighth resistor R13 is connected to one end of the seventh resistor R13, one end of the fifth capacitor NM C13 and the other end of the eighth NMOS NM 13, and the other end of the seventh NMOS R13 is connected to the source of the seventh NMOS 13, the seventh NMOS 13 and the other end of the NMOS 13, the source of the seventh NMOS 13 are connected to the external resistor R13 and the ninth NMOS 13, the drain of the tenth PMOS transistor PM10, the drain of the eleventh PMOS transistor PM11, the drain of the twelfth PMOS transistor PM12, and the drain of the thirteenth PMOS transistor PM13 are all connected to a weak driving voltage source or a stable voltage source input by the power output module, the source of the tenth PMOS transistor PM10 is connected to the drain of the tenth NMOS transistor NM10, the gate of the tenth NMOS transistor NM10, the gate of the eleventh NMOS transistor NM11, the gate of the twelfth NMOS transistor NM12, one end of the sixth capacitor C6, and the gate of the ninth NMOS transistor NM9, the source of the tenth NMOS transistor NM10 is connected to the other end of the sixth capacitor C6, the source of the eleventh NMOS transistor NM11, and the source of the twelfth NMOS transistor NM12, the gate of the eleventh PMOS transistor PM11 is connected to the gate of the twelfth PMOS transistor PM12, the source of the eleventh PMOS transistor PM11 is connected to the drain of the eighth NMOS transistor NM8, the source of the twelfth PMOS transistor PM 24 is connected to the drain of the ninth NMOS 9, the ninth capacitor NM 599, the ninth transistor PM 599, and the ninth NMOS 369, the source of the eighth NMOS transistor NM8, the source of the ninth NMOS transistor NM9, and the drain of the eleventh NMOS transistor NM11 are connected, and the source of the thirteenth PMOS transistor PM13 is connected to the other end of the seventh capacitor C7 and the drain of the twelfth NMOS transistor NM12, respectively.

Specifically, the POR starting module is a power-on reset starting module. The high voltage VDD input signal is compared with the comparator part of sign2 in the POR start module at the signal sign1 of the divider resistor (R7 \8\ 9) (two places Vsign1 and Vsign2 in FIG. 6 represent that the lines are connected, and are the voltage signals input to the comparator), so as to obtain the power-on voltage reference point of the POR, and finally obtain the POR output signal. And after the high-voltage power supply VDD reaches the rated voltage, setting a power-on completion signal of the high-voltage VDD to be 0, completing power-on of the POR starting module, and enabling the POR starting module to enter a stable state.

For satisfying the compatibility of a large amount of chip designs on low pressure technology, and consider the not enough of high-voltage circuit on output parameter stability, the utility model provides a high accuracy constant voltage power supply circuit has reduced the use to the high-voltage device, only uses high-pressure P/N MOS as withstand voltage device in high voltage power supply module, one-level reference voltage drive module and second grade reference voltage drive module, and all the other modules all work under the conventional voltage of 5V (standard value), need not to introduce a large amount of high-voltage device, can be applicable to different technologies, possesses good compatible ability.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and although the present invention has been disclosed with reference to the preferred embodiment, it is not intended to limit the present invention, and any person skilled in the art can make some changes or modifications to equivalent embodiments without departing from the scope of the present invention, and any simple modification, equivalent change and modification made to the above embodiments by the technical essence of the present invention will still fall within the scope of the technical solution of the present invention.

Claims

1. The utility model provides a high accuracy constant voltage power supply circuit, its characterized in that, includes high voltage power supply module, power output module, POR start module, elementary partial pressure module, reference voltage drive module and voltage reference module, wherein, reference voltage drive module includes one-level reference voltage drive module and second grade reference voltage drive module, chip outside high pressure VDD input port is all connected to high voltage power supply module, POR start module, elementary partial pressure module, one-level reference voltage drive module and second grade reference voltage drive module, high voltage power supply module still passes through power output module with POR start module connects, elementary partial pressure module, one-level reference voltage drive module, voltage reference module, second grade reference voltage drive module and power output module connect gradually, elementary partial pressure module, one-level reference voltage drive module, voltage reference module, second grade reference voltage drive module and power output module, And the voltage reference module and the secondary reference voltage driving module are connected with the POR starting module, and the power output module is also connected with a chip low-voltage MOS circuit.

2. A high-precision voltage-stabilized power supply circuit according to claim 1, wherein the high-voltage power supply module comprises a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a load resistor R0, a first capacitor C1, and a first zener diode D1, wherein a gate of the first PMOS transistor PM1 and a gate of the third PMOS transistor PM3 are connected, a gate of the first PMOS transistor PM2 and a gate of the third PMOS transistor PM4 are connected, a drain of the first PMOS transistor PM 6342 and a drain of the third PMOS transistor PM3 are both connected to the chip external high-voltage VDD input port, a source of the first PMOS transistor PM1 and a drain of the second PMOS transistor PM2 are connected, a source of the second PMOS transistor PM2 is connected to one end of the load resistor R0, and the other end of the load resistor R0 is connected to one end of the first capacitor C1 and the source of the first PMOS transistor PM 585, the drain of the first PMOS transistor PM 4624 and the fourth PMOS transistor PM 57324, the source electrode of the fourth PMOS transistor PM4 is respectively connected to the other end of the first capacitor C1 and the cathode of the first zener diode D1; the high-voltage power supply module is used for converting a high-voltage power supply VDD input from an external high-voltage VDD input port of the chip into a weak driving voltage source.

3. A high-precision voltage-stabilized power supply circuit according to claim 1, wherein the power output module includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a second capacitor C2 and an inverter I1, a source of the fifth PMOS transistor PM5 and a source of the sixth PMOS transistor PM6 are both connected to a weak driving voltage source, a gate of the fifth PMOS transistor PM5 is respectively connected to a POR enable signal and an input end of the inverter I1, the POR enable signal includes a VDD enable signal and a sleep signal, a drain of the fifth PMOS transistor PM5 is respectively connected to a source of a sixth PMOS transistor PM6 and the second capacitor C2, a gate of the sixth PMOS transistor PM6 is connected to an output end of the inverter I1, and a drain of the sixth PMOS transistor PM6 is connected to a stable voltage source.

4. A high precision voltage-stabilized power supply circuit according to claim 1, wherein the primary voltage-dividing module includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a third capacitor C3 and a second zener diode D2, one end of the first resistor R1 is connected to the chip external high voltage VDD input port, the other end of the first resistor R1 is connected to one end of the second resistor R2, the drain of the first NMOS transistor NM1, one end of the third capacitor C3 and the cathode of the second zener diode D2, the other end of the second resistor R2 is connected to one end of the third resistor R3 and the gate of the first NMOS transistor NM1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the source of the second NMOS transistor NM 6342, the positive electrode of the third resistor R3 and the positive electrode of the second zener diode D469, the source of the first NMOS transistor NM1 is connected to the drain of the second NMOS transistor NM2, and the gate of the second NMOS transistor NM2 is connected to a sleep signal.

5. A high precision regulated power supply circuit according to claim 1, wherein the primary reference voltage driving module and the secondary reference voltage driving module have the same structure, the primary reference voltage driving module or the secondary reference voltage driving module comprises a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a fifth resistor R5, a sixth resistor R6, a fourth capacitor C4, and a third zener diode D3, the gate of the third NMOS transistor NM3 and the gate of the fifth NMOS transistor NM5 are connected to an externally input voltage signal, the voltage signal comprises a low voltage reference signal and a reference voltage signal, the gate of the third NMOS transistor NM3 and the gate of the fifth NMOS transistor 5 of the primary reference voltage driving module are connected to the low voltage reference signal input by the primary voltage dividing module, a gate of a third NMOS transistor NM3 and a gate of a fifth NMOS transistor NM5 of the secondary reference voltage driving module are both connected to the reference voltage signal input by the voltage reference module, a drain of the third NMOS transistor NM3 is connected to a source of the seventh PMOS transistor PM7 and a gate of a ninth PMOS transistor PM9, a source of the third NMOS transistor NM3 is connected to a drain of the fifth NMOS transistor NM5 and a source of the fourth NMOS transistor NM4, a source of the fifth NMOS transistor NM5 is connected to a drain of the sixth NMOS transistor NM6 and one end of a sixth resistor R6, a gate of the sixth NMOS transistor NM6 is connected to a sleep signal, a source of the sixth NMOS transistor NM6 is grounded, a drain of the seventh PMOS transistor PM7, a drain of the eighth PMOS transistor PM8 and a drain of the ninth PMOS transistor PM9 are both connected to the external drain input port of the PMOS chip, a source of the eighth PMOS transistor NM6 is connected to drain electrodes of the seventh PMOS transistor PM 73742, the eighth PMOS transistor PM 35 8 and the fourth PMOS transistor PM4, the grid electrode of the fourth NMOS transistor NM4 is respectively connected to one end of a fifth resistor R5 and the other end of a sixth resistor R6, the other end of the fifth resistor R5 is respectively connected to the source electrode of the ninth PMOS transistor PM9, the cathode electrode of the third zener diode D3 and one end of a fourth capacitor C4, and the anode electrode of the third zener diode D3 is connected to the other end of the fourth capacitor C4;

the primary reference voltage driving module outputs 3-6V voltage to the voltage reference module, the voltage reference module outputs 1.2V reference voltage signals to the secondary reference voltage driving module, and the secondary reference voltage driving module outputs a stable voltage source to the power output module.

6. A high precision regulated power supply circuit according to claim 1 wherein said voltage reference module employs a bandgap reference voltage source configuration.

7. A high precision voltage-stabilized power supply circuit according to claim 1, wherein the POR start-up module includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a seventh NMOS NM7, an eighth NMOS NM8, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a tenth PMOS NM10, an eleventh PMOS PM11, a twelfth PMOS NM12, and a thirteenth PMOS PM13, a gate of the seventh NMOS NM9 is connected to a high voltage power supply VDD power-up completion signal, a drain of the seventh NMOS NM7 is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9, respectively, another end of the eighth resistor R8 is connected to one end of the seventh R7, a fifth end of the fifth capacitor C5, and an external gate of the seventh NMOS 8 of the high voltage power supply VDD chip, the source of the seventh NMOS transistor NM7 is connected to the other end of a ninth resistor R9 and the other end of a fifth capacitor C5, the drain of the tenth PMOS transistor PM10, the drain of the eleventh PMOS transistor PM11, the drain of the twelfth PMOS transistor PM12, and the drain of the thirteenth PMOS transistor PM13 are all connected to a weak driving voltage source or a stable voltage source input by the power output module, the source of the tenth PMOS transistor PM10 is connected to the drain of the tenth NMOS transistor NM10, the gate of the tenth NMOS transistor NM8, the gate of the eleventh NMOS transistor NM11, the gate of the twelfth NMOS transistor NM12, one end of the sixth capacitor C6, and the gate of the ninth NMOS transistor NM9, the source of the tenth NMOS transistor NM10 is connected to the other end of the sixth capacitor C6, the source of the eleventh NMOS transistor NM11, and the source of the twelfth NMOS transistor NM12, the gate of the eleventh PMOS transistor PM11 and the source of the twelfth PMOS transistor NM5, the eleventh PMOS transistor PM 3723 is connected to the drain of the eighth NMOS 573 5857324, a source of the twelfth PMOS transistor PM12 is connected to a drain of the ninth NMOS transistor NM9, one end of the seventh capacitor C7, and a gate of the thirteenth PMOS transistor PM13, a source of the eighth NMOS transistor NM8, a source of the ninth NMOS transistor NM9, and a drain of the eleventh NMOS transistor NM11 are connected, and a source of the thirteenth PMOS transistor PM13 is connected to the other end of the seventh capacitor C7 and the drain of the twelfth NMOS transistor NM12, respectively.