CN217470000U - Mainboard and switch - Google Patents

Abstract

The utility model provides a mainboard and switch, the mainboard includes power module, clock module, central processing unit, exchange chip and programmable logic device, central processing unit includes DDR3 memory Bus interface 0, DDR3 memory Bus interface 1, the parallel Bus interface of NAND, SPI serial Bus interface, USB Bus interface, UART Bus interface, SGMII0 Bus interface, PCIE Bus interface, SGMII1 Bus interface and Local Bus interface, central processing unit through SGMII0 Bus interface, PCIE Bus interface and SGMII1 Bus interface with the exchange chip is connected, central processing unit is connected with programmable logic device through Local Bus interface. The utility model provides a large number of abundant interfaces, which greatly enriches the application scene of the data center switch provided by the utility model; the independent development and development of the switch core device in China are realized, the whole machine localization rate is 100% by design, and the independent controllable requirement of a special application scene is realized.

Description

Mainboard and switch

Technical Field

The utility model relates to a network communication equipment field especially relates to a mainboard and switch.

Background

A routing switch is a network device for electrical (optical) signal forwarding that provides an exclusive electrical signal path for any two network nodes that access the switch, which functions to connect machines together to form a local area network. With the deep application of cloud services and big data, the mass flow transmission of network data becomes the focus of more and more deep attention of people, and a switch is a core device in network data transmission.

The data flow interface that present traditional switch provided is limited, has restricted certain application scene, the utility model provides a data transmission system and built-in this data transmission system's switch, it passes through PHY chip and network transformer conversion, provides 10M 12 net mouth connectors outward altogether, very big abundance the utility model provides a data center switch application scene.

In addition, the chip is imported abroad to traditional switch adoption mostly at present, lacks the security in special application field, the utility model provides a hardware structure overall arrangement of switch adopts the domestic chip central processing unit CPU, and the domestic memory, the domestic PHY chip of making up has realized the internal independently development and development of switch core device, and the design realizes 100% complete machine localization rate, has realized the independently controllable requirement of special application scene.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a mainboard and switch, aim at satisfying under the application of the present stage cloud business in this area and big data's the deep background of using, to the improvement of switch performance requirement.

In order to realize the above object, the utility model provides a mainboard, the mainboard includes power module, clock module, central processing unit, switching chip and programmable logic device, central processing unit includes DDR3 memory Bus interface 0, DDR3 memory Bus interface 1, NAND parallel Bus interface, SPI serial Bus interface, USB Bus interface, UART Bus interface, SGMII0 Bus interface, PCIE Bus interface, SGMII1 Bus interface and Local Bus interface, central processing unit pass through SGMII0 Bus interface, PCIE Bus interface and SGMII1 Bus interface with the switching chip is connected, central processing unit passes through Local Bus interface and is connected with programmable logic device.

Further, the central processing unit is connected with the 4 pieces of DDR memory particles through a DDR3 memory bus interface 0, and the central processing unit is connected with the 4 pieces of DDR memory particles through a DDR3 memory bus interface 1.

Furthermore, the central processing unit is connected with the NADA Flash memory chip through a NAND parallel bus interface, and the central processing unit is connected with the SPI Flash memory chip through an SPI serial bus interface.

Furthermore, the central processing unit is connected with the USB panel interface through a USB bus interface, and the central processing unit is connected with the serial panel interface through a UART bus interface.

Further, the switch chip comprises an SGMII0 bus interface, a PCIE bus interface, an SGMII1 bus interface, a QSGMII0 bus interface, an SMI0 bus interface, a QSGMII1 bus interface, an SGMII2 bus interface, an SMI1 bus interface, and an SGMII3 bus interface.

Further, the switch chip is connected with the PHY chip 0 through a QSGMII0 bus interface, a SMI0 bus interface and a QSGMII1 bus interface, the PHY chip 0 is connected with a network transformer through an MDI bus, and the network transformer is connected with a 2 × 4M 12 network port connector through a 4 × RJ45 network port.

Further, the switch chip is connected with the PHY chip 1 through an SGMII2 bus interface, an SMI1 bus interface, and an SGMII3 bus interface, the PHY chip 1 is connected with a network transformer through an MDI bus, and the network transformer is connected with a 2 × 1M 12 network port connector through an RJ45 network port.

Further, the programmable logic device is connected with the RTC clock controller, the EEPROM, the LM75 temperature sensor 1, the LM75 temperature sensor 2 and the fan through an IIC bus interface.

Further, a switch is provided, comprising at least one motherboard according to any of the above.

Compared with the prior art, the utility model has the advantages of it is following: a large number of abundant interfaces are provided, and the application scenes of the data center switch provided by the utility model are greatly enriched; the independent development and development of the switch core device in China are realized, the whole machine localization rate is 100% by design, and the independent controllable requirement of a special application scene is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic diagram of a network data processing system according to the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

The utility model discloses a central processing unit that adopts uses national Feiteng CPUFT2000/4, PHY chip uses national flourishing branch of academic or vocational study's CTC21108, the DRAM uses the SCC04GX03A1F1C-26V of purple light country core, programmable logic device uses purple light creative PGC1KG _6CFBG256, network transformer uses Shenzhen city liang Taixing's HST-88029DR, SPi memory chip uses Beijing Mbeige innovative science and technology's GD25Q128ESIGR, EEPROM uses Shanghai connector complex denier microelectronics FM24C128D-SO-T-G-AX, power module mainly uses tin-free purple light microelectronics SM53319, silicon force Jie semiconductor 24302, Jie Huate microelectronics' JWH5276, clock module mainly uses Ningbo Orra 5410, Au5411A-QMR, Au 5410-QMR A-QMR, SQ A-QMR uses Leqing city electronic corporation's Qiqing Qin City electronic network uses Qin City Qin 5-Qin electronic corporation's Qin 760445002, Qin Qing electronic corporation's Qin Qing 3688182 uses electronic corporation's Qin.

The central processing unit is used as the core of the whole system to realize the functions of system management, interface configuration, protocol message processing and the like. The central processing unit is internally provided with 2 DDR3SDRAM controllers, wherein a DDR3 memory controller 0 is externally connected with 4 pieces of DDR3 particles, and a DDR3 memory controller 1 is externally connected with 4 pieces of DDR3 particles.

The central processing unit supports 1 group of PCIE bus interfaces, is connected to the exchange chip and performs interface configuration and control information transmission on the exchange chip. Support 2 groups of SGMII buses SGMII0 and SGMII1, wherein the 2 groups of SGMII buses are connected to the switching chip for data signal transmission.

The exchange chip supports 2 groups of QSGMII bus interfaces, 4 groups of SGMII bus interfaces, 2 groups of SMI bus interfaces and 1 group of PCIE interfaces. The PCIE interface is connected to the central processing unit for control information transmission. The 2 groups of SGMII bus interfaces SGMII0 and SGMII1 are connected to the central processing unit for data information transmission. The 2 sets of QSGMII bus interfaces QSGMII0 and QSGMII1 are connected to PHY chip 1 extension 8 sets of MDI bus connections and connected to the 2 x 4 network port connector of the front panel through network transformers, and the SMI0 bus is responsible for controlling PHY chip 0 and reading the state of PHY chip 0. The 2 groups of SGMII bus interfaces SGMII2 and SGMII3 are connected to PHY chip 2 extension 2 groups MDI bus connection and are connected to 2 x 1 network port connector of the front panel through network transformers, and SMI1 bus is responsible for control of PHY chip 1 and reading state of PHY chip 1.

A LocalBus bus interface of the central processing unit is connected to the programmable logic device through a LocalBus bus, and is switched to an IIC bus through the programmable logic device, the IIC bus is connected with an RTC clock chip to record the current time, is connected with EEPROM storage equipment production manufacturing information, and is connected with a 2pcs temperature sensor to realize fan rotating speed regulation, wherein the temperature sensor 1 is placed at an equipment air inlet, and the temperature sensor 2 is placed at an equipment air outlet.

The Uart bus of the central processor is connected to the front panel, extending the RJ45 serial port connector. The NAND bus is connected with a NAND flash memory chip to store an operating system. The SPI bus is connected to the SPIFlash memory chip to store the BIOS boot system. The USB2.0 bus is directly connected to the front panel expansion USB interface.

The system uses a DCDC power supply module to generate voltages required by chips of 5V, 1.2V, 3.3V, 2.5V, 1.8V, 0.75V, 1.25V and the like, and uses a clock module to generate clocks required by chips of 25Mhz, 125Mhz, 50Mhz, 24Mhz and 32.768 Khz.

The utility model provides a mainboard, the mainboard includes power module, clock module, central processing unit, exchange chip and programmable logic device, central processing unit includes DDR3 memory Bus interface 0, DDR3 memory Bus interface 1, the parallel Bus interface of NAND, SPI serial Bus interface, USB Bus interface, UART Bus interface, SGMII0 Bus interface, PCIE Bus interface, SGMII1 Bus interface and Local Bus interface, central processing unit through SGMII0 Bus interface, PCIE Bus interface and SGMII1 Bus interface with exchange chip connects, central processing unit is connected with programmable logic device through Local Bus interface.

Further, the central processing unit is connected with the 4 pieces of DDR memory particles through a DDR3 memory bus interface 0, and the central processing unit is connected with the 4 pieces of DDR memory particles through a DDR3 memory bus interface 1.

Furthermore, the central processing unit is connected with the NADA Flash memory chip through a NAND parallel bus interface, and the central processing unit is connected with the SPI Flash memory chip through an SPI serial bus interface.

Furthermore, the central processing unit is connected with the USB panel interface through a USB bus interface, and the central processing unit is connected with the serial panel interface through a UART bus interface.

Further, the switch chip comprises an SGMII0 bus interface, a PCIE bus interface, an SGMII1 bus interface, a QSGMII0 bus interface, an SMI0 bus interface, a QSGMII1 bus interface, an SGMII2 bus interface, an SMI1 bus interface, and an SGMII3 bus interface.

Further, the switch chip is connected with the PHY chip 0 through a QSGMII0 bus interface, a SMI0 bus interface and a QSGMII1 bus interface, the PHY chip 0 is connected with a network transformer through an MDI bus, and the network transformer is connected with a 2 × 4M 12 network port connector through a 4 × RJ45 network port.

Further, the switch chip is connected with the PHY chip 1 through an SGMII2 bus interface, an SMI1 bus interface, and an SGMII3 bus interface, the PHY chip 1 is connected with a network transformer through an MDI bus, and the network transformer is connected with a 2 × 1M 12 network port connector through an RJ45 network port.

Further, the programmable logic device is connected with the RTC clock controller, the EEPROM, the LM75 temperature sensor 1, the LM75 temperature sensor 2 and the fan through an IIC bus interface.

A switch is provided, which at least comprises the mainboard. The other hardware configuration of the switch is not particularly limited. The utility model provides a relevant necessary hardware structures such as shell, antenna that the switch has general switch and possesses.

The embodiments described above are only a part of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated herein and in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other changes or substitutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Claims (9)

1. The mainboard is characterized by comprising a power supply module, a clock module, a central processing unit, an exchange chip and a programmable logic device, wherein the central processing unit comprises a DDR3 memory Bus interface 0, a DDR3 memory Bus interface 1, a NAND parallel Bus interface, an SPI serial Bus interface, a USB Bus interface, a UART Bus interface, an SGMII0 Bus interface, a PCIE Bus interface, an SGMII1 Bus interface and a Local Bus interface, the central processing unit is connected with the exchange chip through the SGMII0 Bus interface, the PCIE Bus interface and the SGMII1 Bus interface, and the central processing unit is connected with the programmable logic device through the Local Bus interface.

2. The motherboard of claim 1, wherein the central processing unit is connected to the 4 DDR memory granules through a DDR3 memory bus interface 0, and the central processing unit is connected to the 4 DDR memory granules through a DDR3 memory bus interface 1.

3. The motherboard of claim 2, wherein the central processing unit is connected to the NADA Flash memory chip via a NAND parallel bus interface, and the central processing unit is connected to the SPI Flash memory chip via an SPI serial bus interface.

4. The motherboard of claim 3, wherein the central processor is connected to the USB panel interface via a USB bus interface, and the central processor is connected to the serial panel interface via a UART bus interface.

5. The motherboard of claim 1 or 4, wherein the switch chip comprises an SGMII0 bus interface, a PCIE bus interface, an SGMII1 bus interface, a QSGMII0 bus interface, an SMI0 bus interface, a QSGMII1 bus interface, an SGMII2 bus interface, an SMI1 bus interface, and an SGMII3 bus interface.

6. The motherboard of claim 5 wherein the switch chip is connected to PHY chip 0 via QSGMII0 bus interface, SMI0 bus interface, and QSGMII1 bus interface, the PHY chip 0 being connected to a network transformer via MDI bus, the network transformer being connected to 2M 12 port connector via 4 RJ45 port.

7. The motherboard of claim 6 wherein the switch chip is connected to PHY chip 1 via SGMII2 bus interface, SMI1 bus interface, and SGMII3 bus interface, the PHY chip 1 being connected to the network transformer via MDI bus, the network transformer being connected to 2 x 1M 12 port connector via RJ45 port.

8. The motherboard of claim 1 or 7, wherein the programmable logic device is connected to the RTC clock controller, the EEPROM memory, the LM75 temperature sensor 1, the LM75 temperature sensor 2 and the fan through the IIC bus interface.

9. A switch comprising a motherboard as claimed in any one of claims 1 to 8.

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