CN217643405U

CN217643405U - Mainboard and switch

Info

Publication number: CN217643405U
Application number: CN202222379542.7U
Authority: CN
Inventors: 王健; 阎博; 赵立伟; 韩思宇
Original assignee: Ziguang Hengyue Technology Co ltd
Current assignee: Ziguang Hengyue Technology Co ltd
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2022-10-21
Anticipated expiration: 2032-09-08

Abstract

The utility model provides a mainboard and switch, the mainboard includes power module, clock module, central processing unit, programmable logic device, exchange chip 0, exchange chip 1, exchange chip 2 and exchange chip 3, central processing unit through Uart bus interface, SPI bus interface and QSPI bus interface with programmable logic device connects. The utility model discloses the switch that records has following advantage: the utility model discloses hardware module uses the high-end exchange chip module of home-made for the first time in the design, has realized 32 a 100G optical port data port, satisfies in the data center applied scene many close 100G interface demands to the localization.

Description

Mainboard and switch

Technical Field

The utility model belongs to the technical field of data transmission communication, concretely relates to mainboard and switch.

Background

A switch means a "switch" is a network device used for the forwarding of electrical (optical) signals. It may provide an exclusive electrical signal path for any two network nodes accessing the switch. The most common switch is an ethernet switch. Other common are telephone voice switches, fiber switches, and the like. A network switch is a device for expanding a network, and can provide more connection ports for a sub-network so as to connect more computers. With the development of the communication industry and the promotion of informatization of national economy, the network switch market is in a steady rising situation. The method has the characteristics of high cost performance, high flexibility, relative simplicity, easy realization and the like.

According to the traditional domestic autonomous switch, a service port is mainly designed to realize a 1GE data port or a 10G optical port data port, the application requirement of a traditional access scene is mainly met, a domestic high-end switching chip module is firstly used in the design of the hardware module, 32 100G optical port data ports are firstly realized, and the requirement of a domestic multi-density 100G interface in a data center application scene is met.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a mainboard and switch aims at satisfying the requirement of network data transfer to the switch performance.

In order to realize the above-mentioned purpose, the utility model provides a mainboard, the mainboard includes power module, clock module, central processing unit, programmable logic device, exchange chip 0, exchange chip 1, exchange chip 2 and exchange chip 3, central processing unit includes PCIE0 bus interface, SGMII bus interface, SMI bus interface, DDR4SDRAM bus interface 0, DDR4SDRAM bus interface 1, IIC0 bus interface, IIC1 bus interface, PCIE4 bus interface, PCIE3 bus interface, PCIE2 bus interface, PCIE1 bus interface, uart bus interface, SPI bus interface and QSPI bus interface, central processing unit pass through Uart bus interface, SPI bus interface and QSPI bus interface with programmable logic device connects.

Furthermore, the central processing unit is connected with a PCIE-to-USB chip through a PCIE0 bus interface, the PCIE-to-USB chip is connected with a USB memory card and a USB2.0 connector through a USB2.0 bus, the central processing unit is connected with the PHY chip through an SGMII bus interface and an SMI bus interface, and the PHY chip is connected with an RJ45 gigabit management port through an MDI bus.

Furthermore, the central processing unit is connected with the RTC clock chip, the voltage monitoring chip, the memory bank EEPROM memory chip and the single-board EEPROM memory chip through the IIC0 bus interface.

Further, the central processing unit is connected with the primary power supply, the SFP optical module, the temperature sensing chip 1 and the temperature sensing chip 2 through an IIC1 bus interface.

Furthermore, the programmable logic device is respectively connected with the SPI Flash main storage chip and the SPI Flash spare storage chip through QSPI buses, the programmable logic device is connected with the serial port chip through a Uart bus, the serial port chip is connected with an RJ45 serial port, and the programmable logic device is connected with an FAN FAN, a system monitoring chip and an interrupt controller.

Further, the central processing unit is connected to a switching chip 0 through a PCIE1 bus interface, the switching chip 0 is connected to a 2 × 2 optical port connector 1 through an HSS10 bus interface and an HSS11 bus interface, the switching chip 0 is connected to a 2 × 2 optical port connector 2 through an HSS00 bus interface and an HSS01 bus interface, and the switching chip 0 is connected to the backplane connector through a CS bus interface.

Further, the central processing unit is connected with the switching chip 2 through a PCIE2 bus interface, the switching chip 2 is connected with the 2 × 2 optical connector 3 through an HSS10 bus interface and an HSS11 bus interface, the switching chip 2 is connected with the 2 × 2 optical connector 4 through an HSS00 bus interface and an HSS01 bus interface, and the switching chip 2 is connected with the backplane connector through a CS bus interface.

Further, the central processing unit is connected with the switching chip 1 through a PCIE3 bus interface, the switching chip 1 is connected with the 2 × 2 optical connector 5 through an HSS10 bus interface and an HSS11 bus interface, the switching chip 1 is connected with the 2 × 2 optical connector 6 through an HSS00 bus interface and an HSS01 bus interface, and the switching chip 1 is connected with the backplane connector through a CS bus interface.

Further, the central processing unit is connected with the switching chip 3 through a PCIE4 bus interface, the switching chip 3 is connected with the 2 × 2 optical connector 7 through an HSS10 bus interface and an HSS11 bus interface, the switching chip 3 is connected with the 2 × 2 optical connector 8 through an HSS00 bus interface and an HSS01 bus interface, and the switching chip 3 is connected with the backplane connector through a CS bus interface.

Further, the switch includes at least the motherboard according to any one of 1 to 9 above.

Compared with the prior art, the utility model discloses the switch that records has following advantage: the utility model discloses hardware module uses the high-end exchange chip module of homemade for the first time in the design, has realized 32 a 100G optical port data port, satisfies in the data center application scene to the many close 100G interface demands of localization.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a logic structure diagram of the present invention.

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic concept of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, amount and proportion of each component may be changed arbitrarily and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides the logic structure diagram of the present invention.

The central processing unit is used as the core of the whole system to realize the functions of system management, interface configuration, protocol message processing and the like. The central processing unit is internally provided with 2 DDR4SDRAM controllers, wherein a DDR4 bus interface 0 is externally connected with 1 4GBDDR4 memory bank 0, and a DDR4 bus interface 1 is externally connected with 1 4GBDDR4 memory bank 1.

The central processing unit supports 5 sets of high-speed PCIE bus interfaces, wherein the PCIE0 bus interface is externally connected with a PCIE-to-USB chip for expanding 2 sets of USB2.0 bus interfaces, 1 path of USB bus interface is expanded to a panel USB connector for expanding 1 set of USB interfaces, and the other 1 path of USB bus interface is connected with a USB card-buckling storage operating system. And the PCIE1 bus interface is connected with the exchange chip 0 to realize management data interaction. And the PCIE2 bus interface is connected with the exchange chip 1 to realize management data interaction. And the PCIE3 bus interface is connected with the exchange chip 2 to realize management data interaction. And the PCIE4 bus interface is connected with the exchange chip 3 to realize management data interaction.

The central processing unit supports 1 group of high-speed SGMII bus interfaces to be connected to the PHY chip, the PHY chip leads out the MDI bus to the RJ45 management network port on the front panel, and the SMI bus of the central processing unit configures the PHY chip.

The central processing unit can expand 2 groups of IIC bus interfaces, the IIC0 bus interface is connected with an RTC clock chip to read a current system clock, and is connected with a voltage monitoring chip to monitor the voltage of each power supply of the system, single-board EEPROM storage equipment production and manufacture information, and a memory bank EEPROM storage memory bank manufacturer, the capacity of the memory bank and other information. The IIC1 is connected with a 2pcs temperature sensor to achieve fan rotating speed regulation, wherein the temperature sensor 1 is placed at an equipment air inlet, the temperature sensor 2 is placed at an equipment air outlet, the SFP optical module is connected to read optical module manufacturer information, and a primary power supply is connected to read power supply to obtain manufacturing information, power supply in-place information and the like.

The Uart bus of the central processing unit is connected to the programmable logic device CPLD, and is connected with the serial port chip after passing through the CPLD to carry out voltage transformation and then to the RJ45 serial port of the panel.

The QSPI bus of the central processor is connected to the programmable logic device CPLD and is connected to the SPIFlash main memory chip 0 and the SPIFlash main memory chip 1 through the programmable logic device.

The LPC bus of the central processing unit is connected to the CPLD to realize the reading, writing and configuration of the internal registers of the CPLD, the CPLD controls the interrupt signals of the system to be gathered and reported to the central processing unit through the CPLD, the system monitoring chip is connected to the CPLD to realize the system operation monitoring, and the CPLD controls the PWM signals of the fan to realize the speed regulation of the fan at different speeds.

The switching chip realizes the forwarding of two-layer service data and the reporting of three-layer service data to a central processing unit, the hardware system relates to a 4pcs switching chip, each switching chip can be configured with 1 group of high-speed PCIE bus, 1 group of high-speed CS bus, 2 groups of high-speed HSS bus HSS0[0-1] and HSS1[0-1].

The PCIE bus of the exchange chip 0 is connected to the PCIE1 bus interface of the central processing unit to realize management data exchange, the CS bus of the exchange chip 0 is connected to the backplane connector, and four groups of bus interfaces of HSS00, HSS01, HSS10 and HSS11 of the exchange chip 0 are directly connected to 8 100G optical connectors of the panel.

The PCIE bus of the exchange chip 1 is connected to the PCIE2 bus interface of the central processing unit to realize management data exchange, the CS bus of the exchange chip 1 is connected to the backplane connector, and four groups of bus interfaces of HSS00, HSS01, HSS10 and HSS11 of the exchange chip 1 are directly connected to 8 100G optical connectors of the panel.

The PCIE bus of the exchange chip 2 is connected to the PCIE3 bus interface of the central processing unit to realize management data exchange, the CS bus of the exchange chip 2 is connected to the backplane connector, and four groups of bus interfaces of HSS00, HSS01, HSS10 and HSS11 of the exchange chip 2 are directly connected to 8 100G optical connectors of the panel.

The PCIE bus of the exchange chip 3 is connected to the PCIE4 bus interface of the central processing unit to realize management data exchange, the CS bus of the exchange chip 3 is connected to the backplane connector, and four groups of bus interfaces of HSS00, HSS01, HSS10 and HSS11 of the exchange chip 3 are directly connected to 8 100G optical connectors of the panel.

The system uses a DCDC power supply module to generate voltages required by chips such as 5V, 1.2V, 3.3V, 2.5V, 1.8V, 0.75V, 1.25V and the like, and uses a clock module to generate clocks required by chips such as 25Mhz, 125Mhz, 50Mhz, 24Mhz and 32.768 Khz.

The utility model provides a mainboard, the mainboard includes power module, clock module, central processing unit, programmable logic device, exchange chip 0, exchange chip 1, exchange chip 2 and exchange chip 3, central processing unit includes PCIE0 bus interface, SGMII bus interface, SMI bus interface, DDR4SDRAM bus interface 0, DDR4SDRAM bus interface 1, IIC0 bus interface, IIC1 bus interface, PCIE4 bus interface, PCIE3 bus interface, PCIE2 bus interface, PCIE1 bus interface, uart bus interface, SPI bus interface and QSPI bus interface, central processing unit pass through Uart bus interface, SPI bus interface and QSPI bus interface with programmable logic device connects.

Furthermore, the central processing unit is connected with a PCIE to USB chip through a PCIE0 bus interface, the PCIE to USB chip is connected with a USB memory card and a USB2.0 connector through a USB2.0 bus, the central processing unit is connected with the PHY chip through an SGMII bus interface and an SMI bus interface, and the PHY chip is connected with an RJ45 kilomega management port through an MDI bus.

Furthermore, the central processing unit is connected with the RTC clock chip, the voltage monitoring chip, the memory bank EEPROM memory chip and the single board EEPROM memory chip through the IIC0 bus interface.

Furthermore, the programmable logic device is respectively connected with the SPI Flash main storage chip and the SPI Flash spare storage chip through a QSPI bus, the programmable logic device is connected with the serial port chip through a Uart bus, the serial port chip is connected with an RJ45 serial port, and the programmable logic device is connected with the FAN FAN, the system monitoring chip and the interrupt controller.

Further, the central processing unit is connected with the switching chip 0 through a PCIE1 bus interface, the switching chip 0 is connected with the 2 × 2 optical connector 1 through an HSS10 bus interface and an HSS11 bus interface, the switching chip 0 is connected with the 2 × 2 optical connector 2 through an HSS00 bus interface and an HSS01 bus interface, and the switching chip 0 is connected with the backplane connector through a CS bus interface.

Further, the switch at least comprises the main board described in any one of the above.

There is provided a switch comprising at least the data transmission system as described above. The circuit board inside the switch is used as a carrier. The other hardware configuration of the switch is not particularly limited. The utility model provides a relevant necessary hardware structures such as shell, antenna that the switch has general switch and possesses.

The embodiments described above are only a part of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated herein and in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other changes or substitutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Claims

1. A mainboard is characterized by comprising a power module, a clock module, a central processing unit, a programmable logic device, an exchange chip 0, an exchange chip 1, an exchange chip 2 and an exchange chip 3, wherein the central processing unit comprises a PCIE0 bus interface, an SGMII bus interface, an SMI bus interface, a DDR4SDRAM bus interface 0, a DDR4SDRAM bus interface 1, an IIC0 bus interface, an IIC1 bus interface, a PCIE4 bus interface, a PCIE3 bus interface, a PCIE2 bus interface, a PCIE1 bus interface, a Uart bus interface, an SPI bus interface and a QSPI bus interface, and the central processing unit is connected with the programmable logic device through the Uart bus interface, the SPI bus interface and the QSPI bus interface.

2. The motherboard of claim 1, wherein the central processing unit is connected to a PCIE-to-USB chip via a PCIE0 bus interface, the PCIE-to-USB chip is connected to a USB memory card and a USB2.0 connector via a USB2.0 bus, respectively, the central processing unit is connected to a PHY chip via an SGMII bus interface and an SMI bus interface, and the PHY chip is connected to an RJ45 gigabit management port via an MDI bus.

3. The main board according to claim 1 or 2, wherein the central processing unit is connected to the RTC clock chip, the voltage monitoring chip, the memory bank EEPROM memory chip, and the single board EEPROM memory chip through an IIC0 bus interface.

4. The main board according to claim 3, wherein the central processing unit is connected with the primary power supply, the SFP optical module, the temperature sensing chip 1 and the temperature sensing chip 2 through an IIC1 bus interface.

5. The motherboard of claim 4 wherein the programmable logic device is connected to the SPI Flash main memory chip and the SPI Flash spare memory chip via QSPI buses, the programmable logic device is connected to the serial port chip via a Uart bus, the serial port chip is connected to an RJ45 serial port, and the programmable logic device is connected to the FAN FAN, the system monitoring chip, and the interrupt controller.

6. The motherboard of claim 1 or 5, wherein the central processing unit is connected to the switch chip 0 via a PCIE1 bus interface, the switch chip 0 is connected to the 2 × 2 optical connector 1 via an HSS10 bus interface and an HSS11 bus interface, the switch chip 0 is connected to the 2 × 2 optical connector 2 via an HSS00 bus interface and an HSS01 bus interface, and the switch chip 0 is connected to the backplane connector via a CS bus interface.

7. The motherboard of claim 6, wherein the central processing unit is connected to the switch chip 2 via a PCIE2 bus interface, the switch chip 2 is connected to the 2 × 2 optical connector 3 via an HSS10 bus interface and an HSS11 bus interface, the switch chip 2 is connected to the 2 × 2 optical connector 4 via an HSS00 bus interface and an HSS01 bus interface, and the switch chip 2 is connected to the backplane connector via a CS bus interface.

8. The motherboard of claim 7, wherein the central processing unit is connected to the switch chip 1 via a PCIE3 bus interface, the switch chip 1 is connected to the 2 × 2 optical connector 5 via an HSS10 bus interface and an HSS11 bus interface, the switch chip 1 is connected to the 2 × 2 optical connector 6 via an HSS00 bus interface and an HSS01 bus interface, and the switch chip 1 is connected to the backplane connector via a CS bus interface.

9. The motherboard of claim 8, wherein the central processing unit is connected to the switch chip 3 via a PCIE4 bus interface, the switch chip 3 is connected to the 2 × 2 optical connector 7 via an HSS10 bus interface and an HSS11 bus interface, the switch chip 3 is connected to the 2 × 2 optical connector 8 via an HSS00 bus interface and an HSS01 bus interface, and the switch chip 3 is connected to the backplane connector via a CS bus interface.

10. A switch comprising a motherboard according to any one of claims 1 to 9.