CN217445265U

CN217445265U - Current limit control circuit

Info

Publication number: CN217445265U
Application number: CN202221396185.9U
Authority: CN
Inventors: 李富华; 宋爱武
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2022-06-07
Filing date: 2022-06-07
Publication date: 2022-09-16
Anticipated expiration: 2032-06-07

Abstract

The application provides a current limit control circuit, the source electrode of power tube M1 is connected with sampling circuit, sampling circuit comprises sampling tube M2 and sampling resistor Rs, the source electrode of sampling tube M2 is connected with the in-phase end of voltage comparator, current source, line voltage compensation circuit and resistor R form reference voltage and are connected with the inverting end of voltage comparator, the grid electrode of power tube M1 is connected with leading edge blanking circuit, leading edge blanking circuit makes delay to the conducting signal of power tube M1, prevent current spike mistake turn-off power tube M1; the sampling resistor Rs is also connected with a current limit state machine, the current limit state machine is a digital circuit module, and the resistance value of the sampling resistor Rs is adjusted by detecting the load change of the output end, so that the current limit point is adjusted in a jumping manner; the current source is connected with the bypass capacitor detection circuit, and the bypass capacitor detection circuit adjusts the bias current by detecting the size of the bypass capacitor, so that the bias voltage and the reference voltage are changed to adjust the current limiting point.

Description

Current limit control circuit

Technical Field

The utility model relates to an electricity field, more specifically relates to a current limit control circuit.

Background

The switching power supply system comprises a preceding stage circuit, a high-frequency transformer, a power output circuit, a sampling circuit, a feedback circuit and the like, realizes the function of converting input alternating voltage into direct voltage, for example, converting commercial power into direct-current bus voltage through a rectifier and a capacitor, and then reducing the voltage through the transformer, and generally controls the switching power supply system through a power tube, a driving chip, the sampling circuit and a comparator in order to ensure constant output power. Under some operating conditions, even a single cycle of overcurrent can cause the associated magnetic element to saturate rapidly, producing a very sharp current spike that can damage the power transistor. Therefore, a current limit is usually set, and if the current breaks through a threshold, the power tube is immediately turned off, so that the current limit control is realized, and the current on the power tube is limited cycle by cycle.

The basic circuit of the current limit control module is shown in fig. 1, the sampling circuit consists of a sampling tube M2 and a sampling resistor R, the current of the power tube M1 is sampled, and the sampled voltage is compared with the reference voltage V of the current comparator _limit In comparison, when the current of the power transistor M1 rises and the sampling voltage rises to the reference voltage, the power transistor M1 is turned off, wherein the reference voltage V _limit The current limit regulator can be used for changing to realize the control of the current limit point of the power tube. The core of the current limit control module is that the current limiting point of the power tube is adjusted by detecting the load state, so that the output voltage stabilization is realized. However, due to the influence of system delay on peak current under different line voltages, the prior art, for example, chinese patent 202120952652.0, discloses a line voltage supplement circuit of a flyback AC/DC switching power supply, further designs a line voltage compensation circuit to maintain the stability of a current-limiting point, thereby ensuring that the peak power is constant.

However, the current limit control circuit of the prior art, the adjustment of the current limit point, is also affected by the load change and the load condition. The reference voltage is the sum of a bias voltage and a compensation voltage, the compensation voltage is controlled by a compensation circuit, the bias voltage is the product of a bias current I1 and a resistor R1, wherein the bias current I1 is fixed and unchangeable, a plurality of full-load power tube current limiting points cannot be set, and the power-down time cannot be detected. In addition, it is impossible to prevent the power tube from being turned off by mistake due to the current spike generated by the capacitor and the reverse recovery time of the secondary rectifier tube.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a current limit control circuit, under the prerequisite of guaranteeing output constancy, regulation current-limiting point that can be good to reduce the maloperation.

A current limit control circuit, the source of the power tube M1 is connected with the sampling circuit, the sampling circuit is made up of sampling tube M2 and sampling resistance Rs, one end of the sampling resistance Rs is connected with the source of the sampling tube M2, the other end is grounded, the source of the sampling tube M2 is connected with the non-inverting terminal of the voltage comparator, the current source, the line voltage compensation circuit and the resistance R form the reference voltage and are connected with the inverting terminal of the voltage comparator, the output terminal of the voltage comparator is connected with the grid of the power tube M1, the output signal controls the on-off of the power tube M1; the grid of the power tube M1 is connected with a leading edge blanking circuit, and the leading edge blanking circuit is used for delaying the conducting signal of the power tube M1 and preventing current spikes from mistakenly turning off the power tube M1; the sampling resistor Rs is also connected with a current limit state machine, and the current limit state machine is a digital circuit module and is used for adjusting the resistance value of the sampling resistor Rs by detecting the load change of an output end so as to jump and adjust a current limit point; the current source is connected with the bypass capacitor detection circuit, and the bypass capacitor detection circuit is used for adjusting the bias current by detecting the size of the bypass capacitor, so that the bias voltage and the reference voltage are changed to adjust the current limiting point.

In some embodiments, the leading edge blanking circuit delays the turn-on signal TON _ p of the power transistor M1, the output signal of the leading edge blanking circuit is LEB, LEB is a delay signal of the TON _ p signal, and TON _ p is a high level to control the turn-on of the power transistor M1.

Further, the leading edge blanking circuit includes a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a capacitor C11, and a diode D11, the turn-on signal TON _ p is connected to gates of the MOS transistor M11 and the MOS transistor M12, a source of the MOS transistor M11 is connected to the power supply, a drain of the MOS transistor M11 is connected to a drain of the MOS transistor M12, the capacitor C11 is connected to an anode of the diode D11, the MOS transistor M11 and the MOS transistor M12 form an inverter, a connection point where the capacitor C11 is connected to the anode of the diode D11 is a point a, a source of the MOS transistor M12 is connected to the drain of the MOS transistor M13, a source of the MOS transistor M13 is grounded, the other end of the capacitor C11 is grounded, a cathode of the diode D11 is an output end, and outputs a signal LEB.

Further, the MOS transistor M13 provides the discharge current I to the capacitor C11, so that the signal at point a is flipped from high level to low level to generate a delay, and the calculation formula of the delay time t is S1:

where Δ V is the supply voltage, C is the charge of capacitor C11, and I is the set leading edge blanking time.

In some embodiments, the sampling resistor Rs is a resistor network formed by a plurality of resistors and a switching tube, and the current limit state machine changes the resistance value of the sampling resistor through the short-circuit resistor network to achieve the purpose of adjusting the current limit point.

Furthermore, the resistor network comprises a plurality of resistors connected in series, each resistor is connected with a switch tube, and the current limit state machine changes the resistance value of the sampling resistor Rs by controlling the on-off of the switch tubes.

Further, the sampling resistor includes a resistor R21, a resistor R22, a resistor R23, a resistor R24, a switch tube M21, a switch tube M22, and a switch tube M23, the resistor R21, the resistor R22, the resistor R23, and the resistor R24 are sequentially connected in series, one end of the resistor R21 is connected to the non-inverting terminal of the voltage comparator, the other end of the resistor R22 is connected to the resistor R23, the other end of the resistor R24 is connected to ground, the drain of the switch tube M21 is connected to the lead between the resistor R1 and the resistor R2, the source is connected to ground, and the gate is connected to the output terminal of the current-limiting state machine, the drain and the source of the switch tube M22 are connected to the two ends of the resistor R23, and the gate is connected to the output terminal of the current-limiting state machine, the drain and the source of the switch tube M23 are connected to the two ends of the resistor R24, and the gate is connected to the output terminal of the current-limiting state machine.

In some embodiments, the current limit state machine sets four load states, the output of the current limit state machine is a digital signal, the current limit state machine outputs different digital logic signals according to the change of the load, and the digital logic signals control the resistance value of the sampling resistor Rs.

Further, when the current limit state machine detects that 6 EN _ P are low level or high level during load change, the current limit state machine adjusts the current limit point to keep energy supply balance, responds to sudden change of load, and achieves stabilization of output voltage, wherein the load state is full load, heavy load, medium load and light load.

In some embodiments, the bypass capacitance detection circuit includes a 7-bit counter and a latch, an output terminal of the 7-bit counter is connected to input terminals of two latches, output signals of the two latches are CAP _ H and CAP _ L, respectively, and the output CAP _ H and CAP _ L can control a bias current to achieve a purpose of adjusting a full-load current-limiting point.

Further, the outputs of the 7-bit counter are T2QN, T3QN, T4QN and T6QN, the initial value is low level, POR is a power-on reset signal, the switch power supply is low level when powered on, the power supply is high level after the power on is finished, and the initial state of the RS latch can be determined through the POR signal; CAP _ H and CAP _ L output level 0 or 1, POR, T3QN, T4QN, T6QN are low level when the switching power supply is not electrified, and CAP _ H initial state is determined to be 0; the POR signal is low level, and the initial state of CAP _ L is 1; the time required for T2QN, T4QN to flip to 11 is 10 clock cycles, and the time required for T3QN, T4QN, T6QN to flip to 111 is 44 clock cycles.

Furthermore, the logic of the bypass capacitance detection circuit finds that when the bypass capacitance C is equal to 0.1uF, the power-down time T is less than 10T, and the bypass capacitance detection circuit outputs CAP _ H equal to 0 and CAP _ L equal to 1; when the bypass capacitor C is equal to 1uF, the power-down time is 10T < T < 44T, and the output of the bypass capacitor detection circuit is CAP _ H equal to 0 and CAP _ L equal to 0; when the bypass capacitance C is 10uF, the power-down time T > 44T, and the bypass capacitance detection circuit outputs CAP _ H ═ 1 and CAP _ L ═ 0.

In some embodiments, the compensation current Icm output by the line voltage compensation circuit is converted into a compensation voltage Vcm, Vcm is Icm × R1 by a resistor R1, the bias current I1 output by the current source is converted into a bias voltage V1 by a resistor R1, V1 is I1R 1, the reference voltage VREF is V1+ Vcm, the compensation current Icm is proportional to the on-time of the power tube M1, the smaller the line voltage is, the longer the on-time of the power tube M1 is, the larger the compensation current Icm is, the larger the reference voltage is, the sampling voltage VCS at the time of the voltage comparator inversion is increased, and the peak power is constant.

Drawings

The above described and other features of the present disclosure will be more fully described when read in conjunction with the following drawings. It is appreciated that these drawings depict only several embodiments of the disclosure and are therefore not to be considered limiting of its scope. The present disclosure will be described more clearly and in detail by using the accompanying drawings.

Fig. 1 is a basic circuit diagram of a current limit control circuit of the prior art.

Fig. 2 is a circuit diagram of a current limit control circuit of the present application.

Fig. 3 is a circuit diagram of a leading edge blanking circuit of the current limit control circuit of the present application.

Fig. 4 is a circuit diagram of a sampling resistor of the current limit control circuit of the present application.

Fig. 5 is a circuit diagram of a bypass capacitance detection circuit of the current limit control circuit of the present application.

Detailed Description

The following examples are described to aid in the understanding of the present application and are not, and should not be, construed to limit the scope of the present application in any way.

In the following description, those skilled in the art will recognize that components may be described throughout this discussion as separate functional units (which may include sub-units), but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or may be integrated together (including being integrated within a single system or component).

Also, connections between components or systems are not intended to be limited to direct connections, but rather, data between these components may be modified, reformatted, or otherwise changed by intervening components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled," "connected," or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections.

Example 1:

referring to the switching power supply circuit of fig. 1, the commercial power is converted into a dc bus voltage through a rectifier and a capacitor C1, and then the voltage is reduced through a transformer, a power tube M1 is connected to the transformer, and a power tube M1 is also connected to a current limit control circuit for controlling the on/off and on time of the power tube M1. Referring to fig. 2, the drain of the power transistor M1 is connected to the transformer, the source of the power transistor M1 is connected to the sampling circuit, the gate of the power transistor M1 is connected to the leading edge blanking circuit, and the leading edge blanking circuit delays the turn-on signal of the power transistor M1 to prevent current spikes from turning off the power transistor M1 by mistake. The sampling circuit comprises sampling pipe M2 and sampling resistor Rs, the source electrode of power tube M1 is connected with the drain electrode of sampling pipe M2, the one end of sampling resistor Rs is connected with the source electrode of sampling pipe M2, the other end ground connection, the source electrode of sampling pipe M2 is connected with the homophase end of voltage comparator, sampling resistor Rs still is connected with the current limit state machine, the current limit state machine is the digital circuit module, change through detecting output end load is in order to adjust the resistance of sampling resistor Rs, thereby jump and adjust the current limit point. The bias current I1 output by the current source is converted into bias voltage through a resistor R, the compensation current Icm output by the line voltage compensation circuit is converted into compensation voltage through the resistor R, the sum of the bias voltage and the compensation voltage is reference voltage, the reference voltage is input into the inverting terminal of the voltage comparator, the output terminal of the voltage comparator is connected with the grid electrode of the power tube M1, and the output signal controls the on-off of the power tube M1; the current source is connected with the bypass capacitor detection circuit, and the bypass capacitor detection circuit adjusts the bias current by detecting the size of the bypass capacitor, so that the bias voltage and the reference voltage are changed to adjust the current limiting point.

Referring to fig. 3, the leading edge blanking circuit delays the on signal TON _ p of the power transistor M1, the output signal of the leading edge blanking circuit is LEB, LEB is the delayed signal of the TON _ p signal, and TON _ p is high level to control the on of the power transistor M1. The leading edge blanking circuit comprises a MOS tube M11, a MOS tube M12, a MOS tube M13, a capacitor C11 and a diode D11, a conducting signal TON _ p is connected with the grids of the MOS tube M11 and the MOS tube M12, the source of the MOS tube M11 is connected with a power supply, the drain of the MOS tube M11 is connected with the drain of the MOS tube M12, the capacitor C11 and the anode of the diode D11, the MOS tube M11 and the MOS tube M12 form an inverter, the connection point of the capacitor C11 and the anode of the diode D11 is a point A, the source of the MOS tube M12 is connected with the drain of the MOS tube M13, the source of the MOS tube M13 is grounded, the other end of the capacitor C11 is grounded, the cathode of the diode D11 is an output end, and the signal LEB is output. The MOS transistor M13 provides a discharge current I to the capacitor C11, so that the signal at point a is inverted from high level to low level to generate a delay, and the calculation formula of the delay time t is S1:

Referring to fig. 4, the sampling resistor Rs is a resistor network consisting of 4 resistors and 3 switching tubes, and the current limit state machine changes the resistance value of the sampling resistor through the short-circuit resistor network, so as to achieve the purpose of adjusting the current limit point. The 4 resistors are sequentially connected in series, each resistor is connected with one switch tube, and the flow limit state machine changes the resistance value of the sampling resistor Rs by controlling the on-off of the switch tubes. The sampling resistor comprises a resistor R21, a resistor R22, a resistor R23, a resistor R24, a switch tube M21, a switch tube M22 and a switch tube M23, the resistor R21, the resistor R22, the resistor R23 and the resistor R24 are sequentially connected in series, one end of the resistor R21 is connected with the in-phase end of the voltage comparator, the other end of the resistor R8652 is connected with the resistor R22, one end of the resistor R24 is connected with the resistor R23, the other end of the resistor R24 is grounded, the drain of the switch tube M21 is connected with a lead between the resistor R1 and the resistor R2, the source is grounded, the grid is connected with the output end of the current-limiting state machine, the drain and the source of the switch tube M22 are respectively connected with two ends of a resistor R23, the grid is connected with the output end of the current-limiting state machine, the drain and the source of the switch tube M23 are respectively connected with two ends of a resistor R24, and the grid is connected with the output end of the current-limiting state machine.

The flow limit state machine is set with four load states, the output of the flow limit state machine is a digital signal, the flow limit state machine outputs different digital logic signals according to the change of the load, and the digital logic signals control the resistance value of the sampling resistor Rs. When the current limit state machine detects that 6 EN _ P are low level or high level when the load changes, the current limit point is adjusted to keep energy supply balance, the output voltage is stable in response to sudden change of the load, and the load state is full load, heavy load, medium load and light load.

Referring to fig. 5, the bypass capacitance detection circuit includes a 7-bit counter and a latch, an output terminal of the 7-bit counter is connected to input terminals of two latches, output signals of the two latches are CAP _ H and CAP _ L, respectively, and the output signals of CAP _ H and CAP _ L can control a bias current, thereby achieving the purpose of adjusting a full load current-limiting point. The output of the 7-bit counter is T2QN, T3QN, T4QN and T6QN, the initial value is low level, POR is a power-on reset signal, the power-on reset signal is low level when the switching power supply is powered on, the power-on reset signal is high level after the power-on reset signal is powered on, and the initial state of the RS latch can be determined through the POR signal; CAP _ H and CAP _ L output level 0 or 1, POR, T3QN, T4QN and T6QN are low level when the switching power supply is not electrified, and the initial state of CAP _ H is determined to be 0; the POR signal is low level, and the initial state of CAP _ L is 1; the time required for T2QN, T4QN to flip to 11 is 10 clock cycles, and the time required for T3QN, T4QN, T6QN to flip to 111 is 44 clock cycles. The logic of the bypass capacitance detection circuit can know that when the bypass capacitance C is equal to 0.1uF, the power-down time T is less than 10T, and the bypass capacitance detection circuit outputs CAP _ H equal to 0 and CAP _ L equal to 1; when the bypass capacitor C is equal to 1uF, the power-down time is 10T < T < 44T, and the output of the bypass capacitor detection circuit is CAP _ H equal to 0 and CAP _ L equal to 0; when the bypass capacitance C is 10uF, the power-down time T is greater than 44T, and the bypass capacitance detection circuit outputs CAP _ H1 and CAP _ L0.

The compensation current Icm output by the line voltage compensation circuit is converted into a compensation voltage Vcm through a resistor R1, Vcm equals to Icm R1, the bias current I1 output by the current source is converted into a bias voltage V1 through a resistor R1, V1 equals to I1R 1, the reference voltage VREF equals to V1+ Vcm, the compensation current Icm is proportional to the on-time of the power tube M1, the line voltage is smaller, the on-time of the power tube M1 is longer, the compensation current Icm is also larger, the reference voltage VREF is larger, the sampling voltage VCS when the voltage comparator is inverted is larger, and the peak power is constant.

While various aspects and embodiments have been disclosed herein, it will be apparent to those skilled in the art that other aspects and embodiments can be made without departing from the spirit of the disclosure, and that several modifications and improvements can be made without departing from the spirit of the disclosure. The various aspects and embodiments disclosed herein are presented by way of example only and are not intended to limit the present disclosure, which is to be controlled in the spirit and scope of the appended claims.

Claims

1. A current limit control circuit, the source of the power tube M1 is connected with the sampling circuit, the sampling circuit is made up of sampling tube M2 and sampling resistance Rs, one end of the sampling resistance Rs is connected with the source of the sampling tube M2, the other end is grounded, the source of the sampling tube M2 is connected with the non-inverting terminal of the voltage comparator, the current source, the line voltage compensation circuit and the resistance R form the reference voltage and are connected with the inverting terminal of the voltage comparator, the output terminal of the voltage comparator is connected with the grid of the power tube M1, the output signal controls the on-off of the power tube M1; the power tube switching circuit is characterized in that a grid electrode of the power tube M1 is connected with a leading edge blanking circuit, and the leading edge blanking circuit is used for delaying a conducting signal of the power tube M1 and preventing current spikes from mistakenly switching off the power tube M1; the sampling resistor Rs is also connected with a current limit state machine, and the current limit state machine is a digital circuit module and is used for adjusting the resistance value of the sampling resistor Rs by detecting the change of the load of the output end so as to jump and adjust a current limit point; the current source is connected with the bypass capacitor detection circuit, and the bypass capacitor detection circuit is used for adjusting the bias current by detecting the size of the bypass capacitor, so that the bias voltage and the reference voltage are changed to adjust the current limiting point.

2. The current limit control circuit as claimed in claim 1, wherein the leading edge blanking circuit is configured to delay the turn-on signal TON _ p of the power transistor M1, the output signal of the leading edge blanking circuit is LEB, LEB is the delay signal of the TON _ p signal, and TON _ p is high to control the turn-on of the power transistor M1.

3. The current limit control circuit of claim 2, wherein the leading edge blanking circuit comprises a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a capacitor C11 and a diode D11, the turn-on signal TON _ p is connected to gates of the MOS transistor M11 and the MOS transistor M12, a source of the MOS transistor M11 is connected to the power supply, a drain of the MOS transistor M11 is connected to a drain of the MOS transistor M12, the capacitor C11 is connected to an anode of the diode D11, the MOS transistor M11 and the MOS transistor M12 form an inverter, a connection point where the capacitor C11 is connected to the anode of the diode D11 is a point a, a source of the MOS transistor M12 is connected to the drain of the MOS transistor M13, a source of the MOS transistor M13 is grounded, the other end of the capacitor C11 is grounded, a cathode of the diode D11 is an output terminal, and the signal LEB is output.

4. The current limit control circuit of claim 3, wherein the MOS transistor M13 provides the discharge current I to the capacitor C11, so that the signal at the point A flips from high level to low level to generate a delay time, and the calculation formula of the delay time t is S1:

5. The current limit control circuit according to claim 1, wherein the sampling resistor Rs is a resistor network formed by a plurality of resistors and switching tubes, and the current limit state machine changes the resistance value of the sampling resistor through the short-circuit resistor network to achieve the purpose of adjusting the current limit point; the resistance network comprises a plurality of resistors which are connected in series, each resistor is connected with a switch tube, and the current limit state machine changes the resistance value of the sampling resistor Rs by controlling the on-off of the switch tubes.

6. The current limit control circuit according to claim 5, wherein the sampling resistor comprises a resistor R21, a resistor R22, a resistor R23, a resistor R24, a switch M21, a switch M22 and a switch M23, the resistor R21, the resistor R22, the resistor R23 and the resistor R24 are sequentially connected in series, one end of a resistor R21 is connected with a non-inverting terminal of the voltage comparator, the other end of the resistor R6725 is connected with a resistor R22, one end of a resistor R24 is connected with a resistor R23, the other end of the resistor R24 is connected with ground, a drain of the switch M21 is connected with a conducting wire between the resistor R1 and the resistor R2, a source of the resistor R5631 is connected with a ground, a gate of the switch M22 is connected with two ends of a resistor R23, a gate of the drain and a source of the switch M23 are connected with two ends of a resistor R24, and a gate of the switch M23 is connected with an output of the current-limiting state machine.

7. The current limit control circuit of claim 1, wherein the current limit state machine sets four load states, the output of the current limit state machine is a digital signal, the current limit state machine outputs different digital logic signals according to the change of the load, and the digital logic signals control the resistance value of the sampling resistor Rs; when the load changes, the current limit state machine detects that 6 EN _ P are low level or high level, the current limit point is adjusted to keep energy supply balance, the stability of output voltage is realized in response to sudden change of the load, and the load state is full load, heavy load, medium load and light load.

8. The current limit control circuit of claim 1, wherein the bypass capacitor detection circuit comprises a 7-bit counter and a latch, wherein an output terminal of the 7-bit counter is connected to input terminals of the two latches, output signals of the two latches are CAP _ H and CAP _ L, respectively, and the output CAP _ H and CAP _ L can control the bias current to achieve the purpose of adjusting the full-load current limit point.

9. The current limit control circuit of claim 8, wherein the outputs of the 7-bit counter are T2QN, T3QN, T4QN and T6QN, the initial value is low level, POR is a power-on reset signal, the switching power supply is low level when powered on, and high level after power on is completed, and the initial state of the RS latch is determined by the POR signal; CAP _ H and CAP _ L output level 0 or 1, POR, T3QN, T4QN and T6QN are low level when the switching power supply is not electrified, and the initial state of CAP _ H is determined to be 0; the POR signal is low level, and the initial state of CAP _ L is 1; the time required for T2QN, T4QN to flip to 11 is 10 clock cycles, and the time required for T3QN, T4QN, T6QN to flip to 111 is 44 clock cycles.

10. The current limit control circuit of claim 1, wherein the compensation current Icm output by the line voltage compensation circuit is converted into a compensation voltage Vcm by a resistor R1, Vcm is Icm R1, the bias current I1 output by the current source is converted into a bias voltage V1 by a resistor R1, V1 is I1R 1, the reference voltage VREF is V1+ Vcm, the compensation current Icm is proportional to the on-time of the power transistor M1, the smaller the line voltage, the longer the on-time of the power transistor M1, the larger the compensation current Icm and the reference voltage VREF, the larger the sampling voltage VCS when the voltage comparator is flipped, and the peak power is constant.