CN217404786U - CMOS circuit capable of automatically adjusting along with load change - Google Patents
CMOS circuit capable of automatically adjusting along with load change Download PDFInfo
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- CN217404786U CN217404786U CN202123215853.1U CN202123215853U CN217404786U CN 217404786 U CN217404786 U CN 217404786U CN 202123215853 U CN202123215853 U CN 202123215853U CN 217404786 U CN217404786 U CN 217404786U
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Abstract
The utility model discloses a CMOS circuit along with load change automatic adjustment contains: the first constant current source is used for providing constant current; the bias circuit is connected with the first constant current source and an external VDD input end and used for providing bias voltage; the current mirror is connected with the bias circuit and the VDD input end; the voltage matching circuit is connected with the current mirror; the amplifying circuit is connected with the biasing circuit, the current mirror and the voltage matching circuit; and the filter circuit is connected with the current mirror, the voltage matching circuit and the amplifying circuit. The utility model discloses float the ground of setting reference voltage's component alone, keep apart load and quiescent current and can remove this offset voltage, constituted an cophase feedback path simultaneously. The feedback gain of a positive feedback loop is much smaller than its negative feedback gain, so its effect on the system regulation performance is usually controllable.
Description
Technical Field
The utility model relates to a chip circuit technical field, in particular to CMOS circuit along with load change automatic adjustment.
Background
A change in the load of the power supply will cause a change in the output of the power supply, with an increase in load and a decrease in output, and conversely, a decrease in load and an increase in output. Good power supply load variations cause less output variation. The load regulation rate is an index for measuring the power supply quality. And when the good power supply output is connected with a load, the voltage drop is small. One way to increase the loop gain is to shift the steady state output voltage by a voltage that just offsets the effects of steady state changes in the output current, i.e., to compromise the phase margin for load regulation.
The conventional approach employs shifting the adjustment point of the linear regulator to counteract the effects of load adjustment, and matching and tracking the load to the closed loop impedance is not an easy matter. The biggest disadvantage is that the circuit needs a special reference voltage VREF, because shifting VR horizontally, the quiescent current through the load will generate a systematic offset voltage, making it no longer usable by other analog circuits in the system that require a precise reference voltage.
Disclosure of Invention
According to the embodiment of the utility model provides a CMOS circuit along with load change automatic adjustment is provided, contains:
the first constant current source is used for providing constant current;
the bias circuit is connected with the first constant current source and an external VDD input end and used for providing bias voltage;
the current mirror is connected with the bias circuit and the VDD input end;
the voltage matching circuit is connected with the current mirror;
the amplifying circuit is connected with the biasing circuit, the current mirror and the voltage matching circuit;
and the filter circuit is connected with the current mirror, the voltage matching circuit and the amplifying circuit.
Further, the bias circuit includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a third MOS transistor;
the grid of first MOS pipe links to each other back and with the drain electrode of first MOS pipe with the grid of second MOS pipe, and the drain electrode of first MOS pipe links to each other with first constant current source, and the source electrode of first MOS pipe and the source electrode of second MOS pipe all ground connection, and the drain electrode of second MOS pipe links to each other with the drain electrode of third MOS pipe, the grid of third MOS pipe, and the source electrode of third MOS pipe links to each other with VDD input, amplifier circuit and current mirror.
Furthermore, the first MOS tube and the second MOS tube are both NMOS tubes, and the third MOS tube is a PMOS tube.
Further, the current mirror includes: a fourth MOS transistor and a fifth MOS transistor;
and a grid electrode of the fourth MOS tube is connected with a grid electrode of the fifth MOS tube and then connected with the amplifying circuit and the biasing circuit, a source electrode of the fourth MOS tube and a source electrode of the fifth MOS tube are both connected with the VDD input end, a drain electrode of the fourth MOS tube is connected with the voltage matching circuit, and a drain electrode of the fifth MOS tube is connected with the voltage matching circuit, the amplifying circuit and the filter circuit.
Furthermore, the fourth MOS transistor and the fifth MOS transistor are both PMOS transistors.
Further, the voltage matching circuit includes: the first triode, the second triode and the second constant current source;
the base electrode of the first triode is connected with the base electrode of the second triode and then is connected with the collector electrode of the second triode, the collector electrode of the second triode is connected with one end of the second constant current source, the emitter electrode of the first triode is connected with the current mirror, the collector electrode of the first triode is connected with the amplifying circuit, the collector electrode of the second triode is connected with the current mirror, the amplifying circuit and the filter circuit, and the other end of the second constant current source is grounded.
Further, the amplifying circuit includes: the circuit comprises an operational amplifier, a first capacitor, a load resistor, a first resistor and a second resistor;
the output end of the operational amplifier is connected with the bias circuit and the current mirror, the homodromous input end of the operational amplifier is connected with one end of the first capacitor, one end of the load resistor and the voltage matching circuit, the inverting input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the other end of the first capacitor, the other end of the load resistor and the other end of the second resistor are all grounded, and the other end of the first resistor is connected with the voltage matching circuit, the filter circuit and the current mirror.
Further, the filter circuit includes: the third resistor, the second capacitor, the third constant current source and the Vo output end;
one end of the third resistor is connected with the Vo output end, the current mirror, the voltage matching circuit and the amplifying circuit, the other end of the third resistor is connected with one end of the second capacitor, the other end of the second capacitor is connected with one end of the third constant current source and is grounded, and the third constant current source is connected with the Vo output end.
According to the utility model discloses CMOS circuit along with load change automatic adjustment floats the ground that sets up reference voltage's component alone, can remove this offset voltage with load and quiescent current isolation, has constituted a homophase feedback path simultaneously. The feedback gain of the positive feedback loop is much smaller than its negative feedback gain, so its effect on the system regulation performance is usually controllable.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed technology.
Drawings
Fig. 1 is a circuit diagram of a CMOS circuit that automatically adjusts according to load variations according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and the present invention will be further explained.
First, a CMOS circuit capable of automatically adjusting with load change according to an embodiment of the present invention will be described with reference to fig. 1, which is used for adjusting the load influence in a chip and has a wide application range.
As shown in fig. 1, the CMOS circuit capable of automatically adjusting with load change according to the embodiment of the present invention includes: the circuit comprises a first constant current source IS, a bias circuit, a current mirror, a voltage matching circuit, an amplifying circuit and a filter circuit.
Specifically, as shown in fig. 1, in the present embodiment, the first constant current source IS configured to provide a constant current, the bias circuit IS connected to the first constant current source IS and an external VDD input terminal, the bias circuit IS configured to provide a bias voltage, the current mirror IS connected to the bias circuit and the VDD input terminal, the voltage matching circuit IS connected to the current mirror and IS configured to match a voltage of the current mirror, the amplifier circuit IS connected to the bias circuit, the current mirror and the voltage matching circuit, the amplifier circuit IS configured to amplify a signal error to improve sensitivity of the control system, improve adjustment accuracy and reduce an adjustment error, the filter circuit IS connected to the current mirror, the voltage matching circuit and the amplifier circuit, and the filter circuit IS configured to perform filtering processing.
Further, as shown in fig. 1, in the present embodiment, the bias circuit includes: a first MOS transistor M4, a second MOS transistor M3, and a third MOS transistor M2. The grid of the first MOS tube M4 IS connected with the grid of the second MOS tube M3 and then connected with the drain of the first MOS tube M4, the drain of the first MOS tube M4 IS connected with a first constant current source IS, the source of the first MOS tube M4 and the source of the second MOS tube M3 are both grounded, the drain of the second MOS tube M3 IS connected with the drain of the third MOS tube M2 and the grid of the third MOS tube M2, the source of the third MOS tube M2 IS connected with a VDD input end, an amplifying circuit and a current mirror, and a bias circuit IS formed by the first MOS tube M4, the second MOS tube M3 and the third MOS tube M2 to improve a bias voltage.
Further, as shown in fig. 1, in this embodiment, the first MOS transistor M4 and the second MOS transistor M3 are both NMOS transistors, and the third MOS transistor M2 is a PMOS transistor.
Further, as shown in fig. 1, in the present embodiment, the current mirror includes: a fourth MOS transistor M0 and a fifth MOS transistor M1. The grid of the fourth MOS transistor M0 is connected with the grid of the fifth MOS transistor M1 and then connected with the amplifying circuit and the bias circuit, the source of the fourth MOS transistor M0 and the source of the fifth MOS transistor M1 are both connected with the VDD input end, the drain of the fourth MOS transistor M0 is connected with the voltage matching circuit, the drain of the fifth MOS transistor M1 is connected with the voltage matching circuit, the amplifying circuit and the filter circuit, the fifth MOS transistor M1 mirrors the circuit of the fourth MOS transistor M0 with a very small proportion, the current flows into a load resistor R0 which is connected with the reference voltage in series, and when the load current is low, the current of the fourth MOS transistor M0 is very small.
Further, as shown in fig. 1, in this embodiment, the fourth MOS transistor M0 and the fifth MOS transistor M1 are both PMOS transistors.
Further, as shown in fig. 1, in the present embodiment, the voltage matching circuit includes: a first transistor Q0, a second transistor Q1, and a second constant current source I3. The base of the first triode Q0 is connected with the base of the second triode Q1 and then connected with the collector of the second triode Q1, the collector of the second triode Q1 is connected with one end of a second constant current source I3, the emitter of the first triode Q0 is connected with a current mirror, the collector of the first triode Q0 is connected with an amplifying circuit, the collector of the second triode Q1 is connected with the current mirror, the amplifying circuit and a filter circuit, the other end of the second constant current source I3 is grounded, the first triode Q0 and the second triode Q1 are used for first-order matching with the source-drain voltages of the fourth MOS tube M0 and the fifth MOS tube M1, and the second constant current source I3 is used for providing stable current.
Further, as shown in fig. 1, in the present embodiment, the amplifying circuit includes: the circuit comprises an operational amplifier I0, a first capacitor C1, a load resistor R0, a first resistor R1 and a second resistor R2. The output end of an operational amplifier I0 is connected with a bias circuit and a current mirror, the homodromous input end of an operational amplifier I0 is connected with one end of a first capacitor C1, one end of a load resistor R0 and a voltage matching circuit, the reverse input end of the operational amplifier I0 is connected with one end of a first resistor R1 and one end of a second resistor R2, the other end of the first capacitor C1, the other end of the load resistor R0 and the other end of the second resistor R2 are all grounded, the other end of the first resistor R1 is connected with the voltage matching circuit, a filter circuit and the current mirror, the operational amplifier I0 is used for amplifying an error signal to improve the sensitivity of a control system, improve the adjustment precision and reduce the adjustment error, the first capacitor C1 plays a role in shunting noise and influence of displacement current on the voltage on the load resistor R0, the first resistor R1 and the second resistor R2 are balance resistors of the operational amplifier I0, reducing the effect of the input bias current on the output, the load resistor R0 has little effect on the power conversion efficiency because the quiescent current is low when the load is light, and although the load current increases with increasing quiescent current, the load current is only a small proportion of the quiescent current over the full range. The load resistor R0 has no significant effect on the frequency response characteristic or phase margin because the small signal injected by the load resistor R0 is a common mode signal for the entire circuit.
As further shown in fig. 1, in the present embodiment, the filter circuit includes: a third resistor R3, a second capacitor C0, a third constant current source IL and a Vo output terminal. One end of a third resistor R3 is connected with the Vo output end, the current mirror, the voltage matching circuit and the amplifying circuit, the other end of the third resistor R3 is connected with one end of a second capacitor C0, the other end of the second capacitor C0 is connected with one end of a third constant current source IL and is grounded, the third constant current source IL is connected with the Vo output end, and the third resistor R3 and the second capacitor C0 are connected in series to filter the voltage to be output by the Vo output end.
When the circuit is used, the circuit is connected with a chip system, a small proportion of output current of the fifth MOS transistor M1 is sensed through the matching of the first triode Q0 and the second triode Q1 and fed back to the load resistor R0, and a voltage is generated to translate a reference voltage in the chip system.
In the above, referring to fig. 1, the CMOS circuit according to the embodiment of the present invention is described, the ground of the component for setting the reference voltage is floated alone, the offset voltage can be removed by isolating the load from the quiescent current, and the operational amplifier I0, the fourth MOS transistor M0, the first transistor Q0, the load resistor R0, the first capacitor C1 and the reference voltage constitute an in-phase feedback path. The feedback gain of a positive feedback loop is much smaller than its negative feedback gain, so its effect on the system regulation performance is usually controllable.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described in detail with reference to the preferred embodiments thereof, it should be understood that the above description should not be taken as limiting the present invention. Numerous modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (8)
1. A CMOS circuit that automatically adjusts with load changes, comprising:
the first constant current source is used for providing constant current;
the bias circuit is connected with the first constant current source and an external VDD input end and used for providing bias voltage;
the current mirror is connected with the bias circuit and the VDD input end;
the voltage matching circuit is connected with the current mirror;
the amplifying circuit is connected with the bias circuit, the current mirror and the voltage matching circuit;
and the filter circuit is connected with the current mirror, the voltage matching circuit and the amplifying circuit.
2. The CMOS circuit that automatically adjusts for load changes of claim 1, wherein the bias circuit comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a third MOS transistor;
the grid of first MOS pipe with after the grid of second MOS pipe links to each other and with the drain electrode of first MOS pipe links to each other, the drain electrode of first MOS pipe with first constant current source links to each other, the source electrode of first MOS pipe with the source electrode of second MOS pipe all grounds, the drain electrode of second MOS pipe with the drain electrode of third MOS pipe the grid of third MOS pipe links to each other, the source electrode of third MOS pipe with the VDD input, amplifier circuit and the current mirror links to each other.
3. The CMOS circuit of claim 2 wherein the first and second MOS transistors are NMOS transistors and the third MOS transistor is PMOS transistor.
4. The CMOS circuit that automatically adjusts as a function of load as recited in claim 1 wherein said current mirror comprises: a fourth MOS transistor and a fifth MOS transistor;
the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube and then is connected with the amplifying circuit and the biasing circuit, the source electrode of the fourth MOS tube and the source electrode of the fifth MOS tube are both connected with the VDD input end, the drain electrode of the fourth MOS tube is connected with the voltage matching circuit, and the drain electrode of the fifth MOS tube is connected with the voltage matching circuit, the amplifying circuit and the filter circuit.
5. The CMOS circuit capable of automatically adjusting according to the load change of claim 4, wherein the fourth MOS transistor and the fifth MOS transistor are both PMOS transistors.
6. The CMOS circuit that automatically adjusts as a function of load as recited in claim 1, wherein said voltage matching circuit comprises: the first triode, the second triode and the second constant current source;
the base of the first triode and the base of the second triode are connected and then connected with the collector of the second triode, the collector of the second triode is connected with one end of the second constant current source, the emitter of the first triode is connected with the current mirror, the collector of the first triode is connected with the amplifying circuit, the collector of the second triode is connected with the current mirror, the amplifying circuit and the filter circuit, and the other end of the second constant current source is grounded.
7. The CMOS circuit that automatically adjusts for load changes of claim 1, wherein the amplification circuit comprises: the circuit comprises an operational amplifier, a first capacitor, a load resistor, a first resistor and a second resistor;
the output end of the operational amplifier is connected with the bias circuit and the current mirror, the homodromous input end of the operational amplifier is connected with one end of the first capacitor, one end of the load resistor and the voltage matching circuit, the reverse input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the other end of the first capacitor, the other end of the load resistor and the other end of the second resistor are all grounded, and the other end of the first resistor is connected with the voltage matching circuit, the filter circuit and the current mirror.
8. The CMOS circuit that automatically adjusts for load changes of claim 1, wherein the filter circuit comprises: the third resistor, the second capacitor, the third constant current source and the Vo output end;
one end of the third resistor is connected with the Vo output end, the current mirror, the voltage matching circuit and the amplifying circuit, the other end of the third resistor is connected with one end of the second capacitor, the other end of the second capacitor is connected with one end of the third constant current source and grounded, and the third constant current source is connected with the Vo output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123215853.1U CN217404786U (en) | 2021-12-21 | 2021-12-21 | CMOS circuit capable of automatically adjusting along with load change |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123215853.1U CN217404786U (en) | 2021-12-21 | 2021-12-21 | CMOS circuit capable of automatically adjusting along with load change |
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| Publication Number | Publication Date |
|---|---|
| CN217404786U true CN217404786U (en) | 2022-09-09 |
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| CN202123215853.1U Active CN217404786U (en) | 2021-12-21 | 2021-12-21 | CMOS circuit capable of automatically adjusting along with load change |
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