CN217306507U - Pixel structure, image sensor and electronic device - Google Patents

Abstract

The utility model provides a pixel structure, image sensor, electronic equipment, pixel structure include semiconductor substrate, photoelectric conversion district, floating diffusion district, first transmission control gate and second transmission control gate. The utility model discloses a be formed with two transmission control gates in the pixel structural design, first transmission control gate and second transmission control gate promptly can turn off and transmit the electric field between gate and other parts (like the diffusion zone that floats) to the opening of device and carry out nimble regulation and control based on exerting voltage on two transmission control gates to satisfy the actual demand of device. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field can be modulated on the basis of two transfer control gates. When a high potential difference is formed between the grid electrode of the charge transfer transistor and the floating diffusion active region, the high potential difference can be reduced through the second transfer control gate, so that grid induced leakage is reduced, the problem of image white spots and bad pixels is solved, and the image quality of the CIS is improved.

Description

Pixel structure, image sensor and electronic device

Technical Field

The utility model belongs to the technical field of the semiconductor, especially, relate to a pixel structure, image sensor, electronic equipment.

Background

Today, CMOS Image Sensors (CIS) are ubiquitous in our daily lives, from smart phones to automobiles, security cameras, robots, and AR/VR entertainment devices. As we gradually transitioned into the era of internet of things, the strong demand for intelligent, interconnected, and autonomous consumer products has driven this trend. In response, leading image sensor designers, vendors, and world foundries continue to advance technological innovations to facilitate pixel pitch scaling to smaller dimensions and to achieve greater CIS/ISP integration through pixel-level interconnects. Recently, under the strong demand driving force of the mobile phone market, CMOS image sensor products with smaller pixel size, such as 0.7um pixels, are required. CIS pixel sizes are continuously shrinking, which enables manufacturers to use smaller line widths and higher precision process platforms to fabricate products. Most CIS use n-type metal oxide semiconductor (nMOS) transistors, including charge transfer transistors and source follower amplifiers, based on high mobility.

With the miniaturization trend of the production process, the gate oxide layer and the side wall process of the nMOS charge transfer transistor become thinner and shorter, which causes the electric field between the charge transfer transistor and the drain end (i.e., the floating diffusion active region) thereof to be difficult to be effectively controlled, and in addition, the above trend also makes the problem of gate induced leakage (GIDL) more practical and novel. In the CIS pixel, during exposure, the grid of the charge transfer transistor is biased to be negative voltage so as to completely prevent any electrons from flowing into the photodiode under the dark condition; the gate of the charge transfer transistor and its drain terminal (i.e., the floating diffusion active region) constitute a high potential difference, and GIDL phenomenon easily occurs. The GIDL phenomenon causes a problem of white spots and bad pixels of the CIS image, thereby reducing image quality of the CIS.

Therefore, it is necessary to provide a pixel structure, an image sensor, and an electronic device to solve the above technical problems in the prior art.

It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel structure, an image sensor, and an electronic device, which are used to solve the problems in the prior art that the electric field between the charge transfer transistor and the floating diffusion active region is difficult to be effectively controlled and the gate induced leakage is difficult to be effectively solved.

To achieve the above and other related objects, the present invention provides a pixel structure, including:

a semiconductor substrate having a first surface and a second surface opposite to each other;

the photoelectric conversion region extends from the first surface to the semiconductor substrate and is used for receiving an optical signal to generate an electric signal;

a floating diffusion region extending from the first face into the semiconductor substrate and having a spacing from the photoelectric conversion region;

first transmission control gate and second transmission control gate all set up on the first face, and correspond set gradually photoelectric conversion district with between the diffusion region floats, in order based on first transmission control gate with second transmission control gate will photoelectric conversion district's signal of telecommunication shifts to the diffusion region floats.

Optionally, the first transmission control gate is at least located on the first surface, the second transmission control gate is at least located on the first surface, and a control gate overlapping region is further formed between the first transmission control gate and the second transmission control gate, so as to form a communicating channel between the photoelectric conversion region and the floating diffusion region.

Optionally, the width of the control gate overlap region is less than 0.2 μm.

Optionally, the second transmission control gate extends onto the first transmission control gate or the first transmission control gate extends onto the second transmission control gate to form the control gate overlap region.

Optionally, the first transmission control gate includes a first gate dielectric layer and a first transmission control gate electrode stacked from bottom to top, the second transmission control gate includes a second gate dielectric layer and a second transmission control gate electrode stacked from bottom to top, the first transmission control gate electrode is close to one side of the second transmission control gate and extends beyond the outer edge of the first gate dielectric layer or the second transmission control gate electrode is close to one side of the first transmission control gate and extends beyond the outer edge of the second gate dielectric layer to form a control gate overlapping portion, a spacing portion is further formed between the first transmission control gate electrode and the second transmission control gate electrode corresponding to the control gate overlapping portion, and the control gate overlapping portion and the spacing portion form the control gate overlapping region.

Optionally, the thicknesses of the first gate dielectric layer and the second gate dielectric layer are the same or different.

Optionally, the thickness of the first gate dielectric layer or the second gate dielectric layer corresponding to the spacer and the side portion thereof is the same.

Optionally, the materials of the first gate dielectric layer, the second gate dielectric layer and the spacer are the same or different.

Optionally, the spacer is in contact with a side surface of the corresponding first gate dielectric layer or a side surface of the corresponding second gate dielectric layer.

Optionally, the thickness of the first gate dielectric layer is less than 10nm, the thickness of the second gate dielectric layer is less than 10nm, and the thickness of the spacer is less than 10 nm.

Optionally, at least the second transfer control gate has an overlap region with the floating diffusion region.

Optionally, a projection area of the first transmission control gate on the first surface is larger than a projection area of the second transmission control gate on the first surface.

Optionally, the first transmission control gate and the second transmission control gate have the same working time sequence, the off-state voltage of the second transmission control gate is greater than the off-state voltage of the first transmission control gate, and the on-state voltage is greater than or equal to the on-state voltage of the first transmission control gate.

The utility model also provides an image sensor, include as in any one of above-mentioned scheme the pixel structure.

The utility model also provides an electronic equipment, include as in any one of above-mentioned scheme image sensor.

The utility model also provides a preparation method of pixel structure, wherein, preparation method can be any one in above-mentioned scheme the preparation method of pixel structure, of course, any one in above-mentioned scheme the pixel structure also can adopt other methods to prepare. The preparation method of the pixel structure comprises the following steps:

providing the semiconductor substrate having the first and second opposing faces;

forming the first transmission control gate and the second transmission control gate on the first surface of the semiconductor substrate;

the photoelectric conversion region and the floating diffusion region are prepared in the semiconductor substrate from the first face.

Optionally, when the first transmission control gate includes the first gate dielectric layer and the first transmission control gate electrode, and the second transmission control gate includes the second gate dielectric layer and the second transmission control gate electrode, and the control gate overlapping region formed by the control gate overlapping portion and the spacing portion is formed, the spacing portion and the first gate dielectric layer or the second gate dielectric layer are formed at the same time.

Optionally, the first transmission control gate, the second transmission control gate and the control gate overlapping region form a control gate overlapping region including the following steps:

forming a second transmission control gate on the first surface of the semiconductor substrate;

forming a first gate dielectric material layer on the exposed surface of the second transmission control gate and the surrounding first surface;

forming a first transmission control gate electrode material layer on the first gate dielectric material layer;

etching the first transmission control gate electrode material layer to form the first transmission control gate electrode and the control gate overlapping part;

etching the first gate dielectric material layer to form the first gate dielectric layer and the spacing part;

alternatively, the first and second electrodes may be,

forming the first transmission control gate on the first surface of the semiconductor substrate;

forming a second gate dielectric material layer on the exposed surface of the first transmission control gate and the surrounding first surface;

forming a second transmission control gate electrode material layer on the second gate dielectric material layer;

etching the second transmission control gate electrode material layer to form a second transmission control gate electrode and a control gate overlapping part;

and etching the second gate dielectric material layer to form the second gate dielectric layer and the spacing part.

Optionally, the forming of the first transmission control gate includes a step of forming the first gate dielectric layer based on a first oxidation process, wherein a temperature of the first oxidation process is greater than 600 ℃; and/or forming the second gate dielectric material layer based on a second oxidation process, wherein the temperature of the second oxidation process is more than 600 ℃; and/or forming the second transmission control gate comprises the step of forming the second gate dielectric layer based on a third oxidation process, wherein the temperature of the third oxidation process is higher than 600 ℃; and/or forming the first gate dielectric material layer based on a fourth oxidation process, wherein the temperature of the fourth oxidation process is more than 600 ℃.

As described above, the utility model discloses a pixel structure, image sensor, electronic equipment, the utility model discloses an among the pixel structural design, be formed with two transmission control gates, first transmission control gate and second transmission control gate promptly can turn off and the electric field between transmission control gate and other parts (like the diffusion of floating) is regulated and control in a flexible way to opening of device based on exerting voltage on two transmission control gates to satisfy the actual demand of device, the flexibility of the device control of improvement. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on two transfer control gate electrodes. When a high potential difference is formed between the grid electrode (such as a first transmission control gate) of the charge transmission transistor and the drain electrode end (a floating diffusion active region) of the charge transmission transistor, the high potential difference can be reduced through the second transmission control gate, so that grid induced leakage (GIDL) is reduced, the problem of white spots and bad pixels of CIS images is solved, and the image quality of the CIS is improved.

Drawings

Fig. 1 shows a pixel circuit of an image sensor commonly used in the prior art.

Fig. 2 is a cross-sectional view of the corresponding device structure in the dashed line box of the pixel circuit shown in fig. 1.

FIG. 3 is a graph of TCAD simulation data showing the highest electric field strength and gate polysilicon layer voltage in the structure of FIG. 2.

Fig. 4 is a schematic diagram of a pixel circuit corresponding to the pixel structure provided by the present invention.

Fig. 5 is a flow chart of a manufacturing process of the pixel structure provided by the present invention.

Fig. 6 to 19 are schematic structural diagrams illustrating a pixel structure and a structure obtained in each step of a manufacturing process according to an embodiment of the present invention.

Fig. 20 is a schematic diagram of a pixel structure according to a second embodiment of the present invention.

Description of the element reference numerals

201 photodiode

202 first transmission control gate

203 second transmission control gate

204 reset transistor

205 source follower transistor

206 pixel select transistor

300 semiconductor substrate

300a first side

300b second side

301 second layer of gate dielectric material

302 second transmission control gate material layer

303 first patterned mask layer

304 second transfer gate control gate

305 second gate dielectric layer

306 second transmission control gate

307 first gate dielectric material layer

308 first transmission control gate material layer

309 second patterned mask layer

310 first transmission control gate

311 control gate overlap

312 first gate dielectric layer

313 first transmission control door

314 spacer portion

315 control gate overlap region

316 photoelectric conversion region

317 floating diffusion region

S1-S3

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used in the present invention includes both endpoints.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

In the prior art, the image sensor pixel mostly uses the circuit schematic structure shown in fig. 1, and includes a photodiode 101, a charge transfer transistor 102, a reset transistor 103, a source follower transistor 104, a pixel selection transistor 105, and a floating diffusion active region FD. In addition, with the push of the mobile market of mobile phones to the miniaturization requirement of image sensor products, a sharing layout mode is often adopted among pixels; in an image sensor product with small-area pixels, a sharing structure is usually adopted between pixels, in which a plurality of photodiodes 101 and charge transfer transistors 102 are connected in parallel and are commonly connected to the FD terminal of the floating diffusion active region, for example, a four-pixel sharing structure disclosed in application publication No. CN110336953A and a two-pixel sharing structure disclosed in application publication No. CN 110061026A.

Along with the miniaturization trend of production process, the gate oxide layer and the side wall process of the nMOS charge transfer transistor are thinner and shorter, the electric field between the charge transfer transistor and the drain end (namely, a floating diffusion active region) of the charge transfer transistor is difficult to be effectively regulated and controlled, the problem of grid induced leakage (GIDL) is more practical and novel, and white-point bad pixels are difficult to be effectively solved. The image sensor collects white spot bad pixels of an image and mainly comprises two parts of sources: a photodiode 101 and a floating diffusion active region FD. Specifically, the photodiode 101 generates a white-point defective pixel due to pixel signal malfunction caused by channel leakage of the charge transfer transistor 102, and in order to suppress this white-point factor, the gate of the charge transfer transistor 102 is usually set to be under negative bias in the prior art; however, the negative bias charge transfer transistor 102 is more likely to cause gate induced leakage (GIDL), which causes signal aberration in the floating diffusion active region FD, thereby causing the image pixel to turn white and bright. Especially, the pixels in the shared structure mode and the pixels in the shared layout mode have the defect that an image is easy to have white-point bad pixels, wherein one pixel has a GIDL problem, and then the image signals of all the pixels in the shared structure are represented as an abnormal condition of white and bright.

Fig. 2 shows a schematic cross-sectional view of the device shown in fig. 1, dashed box 100. In fig. 2, the cross-sectional view includes the photodiode 101, the gate oxide layer 201 of the charge transfer transistor 102, the gate polysilicon layer 202 of the charge transfer transistor 102, the floating diffusion active region FD (N + region in fig. 2) as a high concentration N-type impurity ion region, and P-epi (P-type semiconductor silicon substrate). In the normal operation of the image sensor pixel, the N + region of the FD is set to a high voltage state, e.g., 2.5V, and the gate polysilicon layer 202 is set to a negative voltage, e.g., -2V; a high voltage bias state is formed between the gate polysilicon layer 202 and the N + region of the FD, and silicon surfaces of the gate oxide layer 201 region and the N + region between the two overlapping regions are in a high electric field intensity state, which easily causes a charge tunneling phenomenon between the gate polysilicon layer 202 and the N + region of the FD, thereby causing a GIDL defect; silicon dangling bonds and defects exist on the silicon surface of the N + region between the overlapping regions, charges tunneled from the grid polycrystalline silicon layer 202 can be captured and released, and the strength of GIDL is further promoted under the action of a high electric field; the strength of GIDL exhibits an exponential growth relationship with the highest electric field strength. In addition, fig. 3 is a graph of TCAD (process computer aided design) simulation data of the highest electric field strength and the voltage of the gate polysilicon layer 202 in the device having the structure of fig. 2, and it can be seen from fig. 3 that the more negative the voltage of the gate polysilicon layer 202 is, the higher the highest electric field strength is, and the more obvious GIDL problem is caused by the higher the highest electric field strength.

In view of the above problem, the utility model provides a pixel structure, image sensor, electronic equipment, pixel structure includes: the photoelectric conversion device comprises a semiconductor substrate, a photoelectric conversion region, a floating diffusion region, a first transmission control gate and a second transmission control gate. The utility model discloses an among the pixel structural design, be formed with two transmission control gates, first transmission control gate and second transmission control gate promptly can turn off and the transmission control gate carries out nimble regulation and control with the electric field between other parts (like the diffusion zone that floats) to opening of device based on exerting voltage on two transmission control gates to satisfy the actual demand of device, the flexibility of the device control of improvement. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field can be modulated based on two transfer control gate electrodes. When a high potential difference is formed between the grid electrode (such as a first transmission control gate) of the charge transmission transistor and the drain electrode end (a floating diffusion active region) of the charge transmission transistor, the high potential difference can be reduced through the second transmission control gate, so that grid induced leakage (GIDL) is reduced, the problem of white spots and bad pixels of CIS images is solved, and the image quality of the CIS is improved.

Fig. 4 is a circuit diagram of a pixel structure according to the present invention. Fig. 5 is a flow chart of a manufacturing process of the pixel structure of the present invention. Fig. 6-19 show a schematic structural diagram of a pixel structure and the steps in the manufacturing process thereof according to the present invention. Fig. 20 is a schematic diagram of another pixel structure provided by the present invention.

The pixel structure and the manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

The first embodiment is as follows:

as shown in fig. 4, a pixel circuit diagram corresponding to the pixel structure provided by the present invention is shown. The pixel circuit in fig. 4 includes a photodiode 201, a first transfer control gate 202, a second transfer control gate 203, a reset transistor 204, a source follower transistor 205, and a pixel select transistor 206, FD is a floating diffusion active region, and a dashed box 200 marks the position of the device. In the pixel circuit of this embodiment, two transfer transistors are disposed between the photoelectric conversion region (e.g., the photodiode 201) and the floating diffusion FD for charge transfer of the photoelectric conversion region to the floating diffusion, and two transfer control gates can flexibly modulate the electric field.

As shown in fig. 5, the present invention provides a method for manufacturing a pixel structure, wherein the pixel structure provided by the present invention is preferably manufactured by the manufacturing method provided by the present embodiment, and of course, can be manufactured by other methods. As shown in fig. 5, the method for manufacturing the pixel structure provided in this embodiment includes the following steps:

s1: providing the semiconductor substrate having the first and second opposing faces;

s2: forming the first transmission control gate and the second transmission control gate on the first surface of the semiconductor substrate;

s3: the photoelectric conversion region and the floating diffusion region are prepared in the semiconductor substrate from the first face.

The following will describe the method for manufacturing a pixel structure according to the present invention in detail with reference to the accompanying drawings, wherein fig. 6 to 19 represent schematic structural diagrams obtained in each step in the pixel structure manufacturing of this embodiment. In addition, it should be noted that the above sequence does not strictly represent the preparation sequence of the pixel structure protected by the present invention, and those skilled in the art can change the sequence according to the actual process steps. Fig. 4 shows only a sequence of steps for manufacturing a pixel structure in an example provided by the present invention.

First, as shown in S1 in fig. 5 and fig. 6, the semiconductor substrate 300 having the first face 300a and the second face 300b opposed to each other is provided.

Specifically, the semiconductor substrate 300 may be any structure used in the field of image sensors for preparing various functional regions of an image sensor, such as a photosensitive element and various control transistors of a CMOS image sensor based on the semiconductor substrate 300. The semiconductor substrate 300 may be a structure formed by a single layer of material, including but not limited to a silicon substrate, in which elements in each region are prepared, and may be single crystal silicon, single crystal germanium, polycrystalline silicon, amorphous silicon, a silicon germanium compound, or the like.

In addition, the semiconductor substrate 300 may also be a stacked structure of two or more material layers, each region being prepared in any desired layer thereof. For example, the semiconductor substrate 300 includes a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate in which the photosensitive elements and the respective control transistors and the like are fabricated, as can a backside illuminated (BSI) image sensor based on the above-described structure. In addition, the semiconductor substrate 300 may be Silicon On Insulator (SOI). In addition, the semiconductor substrate 300 may also be a structure with N-type doping or P-type doping to meet the functional requirements of the device.

In this embodiment, the semiconductor substrate 300 is selected to be a P-epi single crystal material with a P-type epitaxial layer, and the silicon substrate is exposed on the surface.

Next, as shown in S2 in fig. 5 and fig. 18, the first transfer control gate 306 and the second transfer control gate 313 are formed on the first surface of the semiconductor substrate 300.

By way of example, the first transmission control gate 313 includes a first gate dielectric layer 312 and a first transmission control gate electrode 310, and the second transmission control gate 306 includes a second gate dielectric layer 305 and a second transmission control gate electrode 304.

As an example, as shown in fig. 18, a first transfer control gate 313 is located on the surface of the first face 300a of the semiconductor substrate 300, a second transfer control gate 306 is located on the surface of the first face 300a of the semiconductor substrate 300, and a control gate overlap region 315 is formed between the first transfer control gate 313 and the second transfer control gate 306 to form a communicating channel between the photoelectric conversion region and the floating diffusion region.

In a further example, the first transmission control gate electrode 312 extends beyond the outer edge of the second gate dielectric layer 312 near the second transmission control gate 306 to form a control gate overlapping portion 311, a spacer portion 314 is further formed between the second transmission control gate electrode 304 corresponding to the control gate overlapping portion 311 and the first transmission control gate electrode 310, and the control gate overlapping portion 311 and the spacer portion 314 form a control gate overlapping region 315.

In one example, when the control gate overlap region 315 including the control gate overlap portion 311 and the spacer portion 314 is formed, the spacer portion 314 is formed simultaneously with the first gate dielectric layer 312.

In this embodiment, the formation of the first transmission control gate 313, the second transmission control gate 306 and the control gate overlapping region 315 includes the following steps:

as shown in fig. 7 to 12, a second transfer control gate 306 is formed on the first face 300a of the semiconductor substrate 300; the specific process can be as follows: as shown in fig. 7, a second gate dielectric material layer 301 is formed on the surface of the first face 300a, and the material of the second gate dielectric material layer 301 may be selected from existing gate oxide materials, including but not limited to silicon oxide.

In one example, the second gate dielectric material layer 310 is formed by a third oxidation process, and the temperature of the third oxidation process is 600 ℃ or higher, for example, 800 ℃, 900 ℃, 1000 ℃. The length of the oxidation time can be adjusted, a gate oxide material layer with a preset thickness can be manufactured to obtain a gate oxide layer with a required thickness, and the thickness can be consistent with the technical parameters of the existing process platform.

Next, as shown in fig. 8, a second transfer control gate electrode material layer 302 is formed on the second gate dielectric material layer 301. The second transfer gate electrode material layer 302 may be formed by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), and the like, and the material includes, but is not limited to, polysilicon, so as to obtain a subsequent second transfer control gate electrode.

Next, as shown in fig. 9-12, the second transmission control gate electrode material layer 302 and the second gate dielectric material layer 310 are etched to form a second transmission control gate 306 including a second gate dielectric layer 305 and a second transmission gate control gate electrode 304 stacked from bottom to top. The specific process steps can be as follows:

first, a first patterned mask layer 303 is obtained, for example, a spin-on photoresist is obtained, and is developed, as shown in fig. 9, a layer of photoresist is spin-coated above the polysilicon layer deposited in the previous step to be used as a photoresist, and the photoresist is only left at a position preset to form a second transmission control gate 306; then, the second transmission control gate electrode material 302 is etched, for example, a polysilicon material is etched, as shown in fig. 10, and an unnecessary polysilicon layer is etched away; then, after the etching is finished, removing the first patterned mask layer 303, and as shown in fig. 11, removing the photoresist; finally, wet etching is performed on the second gate dielectric material layer 301, as shown in fig. 12, for example, the unnecessary oxide layer is etched away, so as to obtain a second gate dielectric layer 305.

Continuing, as shown in fig. 13, a first gate dielectric material layer 307 is formed on the exposed surface of the second transmission control gate 306 and the surrounding first surface 300a of the semiconductor substrate 300.

In one example, the first gate dielectric material layer 307 is formed by a fourth oxidation process, and the temperature of the fourth oxidation process is 600 ℃ or higher, for example, 800 ℃, 900 ℃, 1000 ℃. The oxidation time length can be adjusted, and a material layer with a preset thickness can be manufactured to obtain a subsequent first gate dielectric layer and a subsequent interval part.

Next, as shown in fig. 14, a first transmission control gate electrode material layer 308 is formed on the first gate dielectric material layer 307. The first transmission gate electrode material layer 308 may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like, and may include, but is not limited to, polysilicon, to obtain a subsequent first transmission control gate electrode and control gate overlap.

Next, as shown in fig. 15-17, the first transmission control gate electrode material layer 308 is etched to form the first transmission control gate electrode 310 and the control gate overlapping portion 311. The second patterned mask layer 309 may be formed first, as shown in fig. 15, a photoresist may be spin-coated and developed, a layer of photoresist is spin-coated above the polysilicon layer deposited in the previous step to be used as a photoresist, and the photoresist is only left at a position where the first transmission control gate and the control gate overlapping region are preset to be formed; then, as shown in fig. 16, the first transmission control gate electrode material layer 308 is etched, for example, the polysilicon material is etched, and the unnecessary polysilicon layer is etched away; finally, as shown in fig. 17, the second patterned mask layer 309 is removed, and after the etching is completed, the photoresist is removed, so as to obtain the first transmission control gate electrode 310 and the control gate overlapping portion 311, which are formed simultaneously, thereby simplifying the process.

Next, as shown in fig. 18, the first gate dielectric material layer 307 is etched to form the first gate dielectric layer 312 and the spacer 314, for example, oxide on the exposed silicon-based surface and the polysilicon surface is etched away, so as to obtain a first transmission control gate 313 and a control gate overlap region 315 that facilitates forming a continuous channel between the two transmission control gates.

Finally, as shown in S3 in fig. 5 and fig. 19, the photoelectric conversion region (PD)316 and the floating diffusion region (FD)317 are prepared in the semiconductor substrate 300 from the first face 300 a.

Specifically, the photoelectric conversion region (PD)211 and the floating diffusion region (FD) 212 may be formed by conventional ion implantation processes, for example, n-type ion doping, and conventional processes may be used. In an alternative example, the photoelectric conversion region 211 may form a photodiode. In addition, in other embodiments, a manner of preparing the photoelectric conversion element first and then preparing the transmission control gate may be adopted, and of course, other suitable preparation sequences may also be adopted.

It should be noted that the pixel structure obtained in this embodiment includes: a semiconductor substrate 300, a photoelectric conversion region 316, a floating diffusion region 317, and a first transfer control gate 313 and a second transfer control gate 306. Wherein the semiconductor substrate 300 has a first surface 300a and a second surface 300b opposite to each other; the photoelectric conversion region 316 extends from the first surface 300a into the semiconductor substrate 300 and is used for receiving an optical signal to generate an electrical signal; a floating diffusion region 317 extending from the first face 300a into the semiconductor substrate 300 with a space from the photoelectric conversion region 316; in addition, a first transmission control gate 313 and a second transmission control gate 306 are disposed on the first face 300a, and are correspondingly disposed between the photoelectric conversion region 316 and the floating diffusion region 317 in sequence, so as to transfer an electrical signal of the photoelectric conversion region 316 to the floating diffusion region 317 based on the first transmission control gate 313 and the second transmission control gate 306. It is understood that, here, the edge of the transfer control gate electrode may be aligned with the edge of the corresponding photoelectric conversion region 316 or the floating diffusion region 317, and also the edge of the transfer control gate electrode may correspond to and overlap with both sides to form an effective device channel, so as to realize charge transfer of the image sensor.

Two transmission control gates, namely a first transmission control gate 313 and a second transmission control gate 306, are formed, and the on/off of the device and the electric field between the transmission control gate and other parts (such as a floating diffusion region) can be flexibly regulated and controlled based on the voltage applied to the two transmission control gates, so that the actual requirements of the device can be met, and the flexibility of device control is improved. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on two transfer control gate electrodes. It can also be said that the modulation can be based on the introduction of the second transfer control gate 306 when an electric field is formed between the first transfer control gate 313 and the floating diffusion region 317. When a high potential difference is formed between the gate (e.g., the first transmission control gate) of the charge transfer transistor and the drain terminal (the floating diffusion active region) thereof, for example, when the gate bias voltage of the charge transfer transistor (the first transmission control gate) is negative during exposure of the CIS pixel, the high potential difference can be reduced by the second transmission control gate 306, so that gate induced leakage (GIDL) is reduced, the problem of white point and bad pixel of the CIS image is improved, and the image quality of the CIS is improved.

By way of example, the width d of the control gate overlap region 315 is less than 0.2 μm, and may be 0.1 μm, 0.15 μm, for example. Thereby being beneficial to forming an effective continuous channel and simultaneously reducing the influence of the overlapping control area material layer on the performance of the device.

As an example, the thicknesses of the first gate dielectric layer 312 and the second gate dielectric layer 305 are the same or different; both can be designed according to actual requirements. As an example, the thicknesses of the first gate dielectric layer 312 and the spacer 314 are the same, so that the spacer and other material layers can be simultaneously prepared, and an extra process is not wasted for forming the control gate overlapping region.

By way of example, the thickness of the first gate dielectric layer is less than 10nm, and may be 6nm or 8 nm; the thickness of the second gate dielectric layer is less than 10nm, and can be 6nm or 8 nm; the thickness of the spacer is less than 10nm, and may be 6nm or 8 nm.

As an example, the materials of the first gate dielectric layer 312, the second gate dielectric layer 305 and the spacer 314 may be the same or different. As an example, the spacers 314 contact with corresponding sides of the first gate dielectric layer 312 to facilitate isolation of gate electrodes of the transmission control gates and prevent electrical connection between the two transmission control gates.

As an example, at least the second transfer control gate 306 and the floating diffusion 317 have an overlapping region therebetween, as shown by the dashed box in fig. 19, so that the electric field existing in the overlapping region can be effectively adjusted based on the second transfer control gate 306, for example, the electric field in the region is improved, the GIDL of the device can be effectively improved, the white point is improved, and the image quality is improved.

As an example, a projected area of the first transmission control gate 313 on the first surface is larger than a projected area of the second transmission control gate 306 on the first surface. Thereby facilitating the control of the transfer of charge between the photoelectric conversion region 316 and the floating diffusion region 317 based on the first transfer control gate 313 and the modulation of the electric field based on the second transfer control gate 306.

For example, the first transmission control gate 313 and the second transmission control gate 306 have the same operation timing, and the off-state voltage of the second transmission control gate 306 is greater than the off-state voltage of the first transmission control gate 313, and the on-state voltage of the second transmission control gate 306 is greater than or equal to the on-state voltage of the first transmission control gate 313.

Specifically, in one example, during operation of the device, the operating voltage of the first transmission control gate 313, the low voltage (which may be the turn-off voltage of the tube, for example) is a negative voltage, for example, generally less than-0.5V, and the operating voltage of the second transmission control gate 306, the low voltage is greater than the low voltage of the first transmission control gate 313, for example, 0V; in another example, during operation of the device, the operating voltage of the first transmission control gate 313, the high voltage (e.g., the on-state voltage of the transistor), and the second transmission control gate 306 are set to be greater than or equal to the on-state voltage of the first transmission control gate 313. When the device is normally operated, for example, the image sensor pixel is normally operated, the operation timings of the first transfer control gate 313 and the second transfer control gate 306 are the same, for example, the operation timings may be consistent with the operation timings of the image sensor pixel in the prior art, and the formation and transfer of charges may be performed. In this example, the off-voltage low voltage of the second transfer control gate 306 is greater than the off-voltage low voltage of the first transfer control gate 313, and the electric field strength formed by the second transfer control gate 306 and the floating diffusion FD (e.g., N + region) is decoupled from the first transfer control gate 313, and the electric field strength can be adjusted by using the setting voltage of the second transfer control gate 306 to improve the gate-induced leakage problem of the electric field, so that GIDL can be improved, and white spots and image quality can be improved.

Example two:

as shown in fig. 20, the second embodiment provides another pixel structure and a corresponding manufacturing method, and the second embodiment is different from the first embodiment mainly in the position and the forming process of the gate overlapping region, and the difference between the first embodiment and the second embodiment will be described in detail below with reference to the drawings, and other related structures and manufacturing processes may be referred to in the first embodiment and will not be described again here.

In the second embodiment, the pixel structure includes a semiconductor substrate 400, a photoelectric conversion region 410, a floating diffusion region 411, and a first transfer control gate 404 and a second transfer control gate 401; in this embodiment, the second transmission control gate 404 extends to the first transmission control gate 401 to form the control gate overlapping region 409.

As an example, the first transmission control gate 401 includes a first gate dielectric layer 403 and a first transmission gate 402 stacked from bottom to top, the second transmission control gate 404 includes a second gate dielectric layer 406 and a second transmission gate 405 stacked from bottom to top, the second transmission gate 405 extends beyond an outer edge of the second gate dielectric layer 406 near one side of the first transmission control gate 401 to form a control gate overlapping portion 408, a spacing portion 407 is further formed between the first transmission gate 402 and the second transmission gate 405 (or the control gate overlapping portion 408) corresponding to the control gate overlapping portion 408, and the control gate overlapping portion 408 and the spacing portion 407 form the control gate overlapping region 409.

In addition, the device structure of this embodiment can also be prepared as in embodiment one, except that the first transmission control gate 409 is formed first, and then the control gate overlapping region 409 is formed during the formation of the second transmission control gate 404.

The specific process can comprise the following steps: forming the first transmission control gate 401 on the first surface of the semiconductor substrate 400; the forming process of the first transfer gate 401 may refer to the forming process of the second transfer control gate 306 in the first embodiment, and in the forming process, the forming process includes a step of forming the first gate dielectric layer 403 based on a first oxidation process, where a temperature of the first oxidation process is greater than 600 ℃, and specific processes may refer to processes and conditions for forming the second gate dielectric layer in the first embodiment. Then, after forming the first transmission control gate 401, forming a second gate dielectric material layer (not shown in the figure) on the exposed surface of the first transmission control gate 401 and the surrounding first surface; the second gate dielectric material layer (not shown in the figure) is formed based on a second oxidation process, the temperature of the second oxidation process is greater than 600 ℃, and specific processes can refer to the process and conditions for forming the first gate dielectric material layer in the embodiment. Next, forming a second transmission control gate electrode material layer (not shown in the figure) on the second gate dielectric material layer; finally, etching the second transmission control gate electrode material layer to form the second transmission control gate electrode 405 and the control gate overlapping part 408; and etching the second gate dielectric material layer to form the second gate dielectric layer 406 and the spacer 407, thereby forming a second transmission control gate 404 and a control gate overlapping region 409.

Example three:

a third embodiment provides an image sensor, which includes the pixel structure according to any aspect of the present invention, for example, the pixel structure according to any one of the first embodiment and the second embodiment. The utility model discloses an image sensor can CMOS image sensor. In addition, this embodiment still provides an electronic equipment, includes like the utility model discloses an arbitrary scheme the image sensor. The electronic equipment can be equipment such as a security camera device, an automobile electronic camera device, a mobile phone camera device, an unmanned aerial vehicle, machine vision and an existing camera.

To sum up, the utility model provides a pixel structure, image sensor, electronic equipment, the utility model discloses an among the pixel structural design, be formed with two transmission control gates, first transmission control gate and second transmission control gate promptly can turn off and transmit the electric field between gate and other parts (if the diffusion zone floats) to turn on and shut off and the transmission control gate carries out nimble regulation and control to opening of device based on exerting voltage on two transmission control gates to satisfy the actual demand of device, the flexibility of the device control of improvement. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on two transfer control gate electrodes. When a high potential difference is formed between the grid (such as a first transmission control gate) of the charge transmission transistor and the drain terminal (a floating diffusion active region) of the charge transmission transistor, the high potential difference can be reduced through the second transmission control gate, so that grid induced leakage (GIDL) is reduced, the problem of white spots and bad pixels of CIS images is solved, and the image quality of the CIS is improved. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A pixel structure, comprising:

a semiconductor substrate having a first surface and a second surface opposite to each other;

the photoelectric conversion region extends from the first surface to the semiconductor substrate and is used for receiving an optical signal to generate an electric signal;

a floating diffusion region extending from the first face into the semiconductor substrate and having a spacing from the photoelectric conversion region;

first transmission control gate and second transmission control gate all set up on the first face, and correspond set gradually photoelectric conversion district with between the diffusion region floats, in order based on first transmission control gate with second transmission control gate will photoelectric conversion district's signal of telecommunication shifts to the diffusion region floats.

2. The pixel structure of claim 1, wherein the first transfer control gate is located on the first face surface, the second transfer control gate is located on the first face surface, and a control gate overlap region is further formed between the first transfer control gate and the second transfer control gate to form a communicating channel between the photoelectric conversion region and the floating diffusion region.

3. The pixel structure of claim 2, wherein the width of the control gate overlap region is less than 0.2 μm.

4. The pixel structure of claim 2, wherein the second transfer control gate extends onto the first transfer control gate or the first transfer control gate extends onto the second transfer control gate to form the control gate overlap region.

5. The pixel structure of claim 4, wherein the first transmission control gate comprises a first gate dielectric layer and a first transmission control gate electrode stacked from bottom to top, the second transmission control gate comprises a second gate dielectric layer and a second transmission control gate electrode stacked from bottom to top, the first transmission control gate electrode extends beyond the outer edge of the first gate dielectric layer on a side close to the second transmission control gate or extends beyond the outer edge of the second gate dielectric layer on a side close to the first transmission control gate to form a control gate overlapping portion, a spacer portion is further formed between the first transmission control gate electrode and the second transmission control gate electrode corresponding to the control gate overlapping portion, and the control gate overlapping portion and the spacer portion form the control gate overlapping region.

6. The pixel structure according to claim 5, wherein the thicknesses of the first gate dielectric layer and the second gate dielectric layer are the same or different; and/or the thickness of the first gate dielectric layer or the second gate dielectric layer corresponding to the spacer and the side part of the spacer is the same; and/or the materials of the first gate dielectric layer, the second gate dielectric layer and the spacing part are the same or different; and/or the spacing part is contacted with the side surface of the corresponding first gate dielectric layer or the side surface of the corresponding second gate dielectric layer; and/or the thickness of the first gate dielectric layer is less than 10nm, the thickness of the second gate dielectric layer is less than 10nm, and the thickness of the spacing part is less than 10 nm.

7. The pixel structure of claim 1, wherein the second transfer control gate has an overlap region with the floating diffusion region.

8. The pixel structure of claim 1, wherein a projected area of the first transfer control gate on the first side is larger than a projected area of the second transfer control gate on the first side.

9. The pixel structure according to any one of claims 1 to 8, wherein the first transmission control gate and the second transmission control gate operate at the same timing, and the off-state voltage of the second transmission control gate is greater than the off-state voltage of the first transmission control gate, and the on-state voltage is greater than or equal to the on-state voltage of the first transmission control gate.

10. An image sensor comprising a pixel structure according to any one of claims 1 to 9.

11. An electronic device characterized by comprising the image sensor of claim 10.

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