CN217768385U - Image sensor with improved pixel field effect transistor GIDL - Google Patents

Abstract

The utility model provides an improve pixel field effect transistor GIDL's image sensor, image sensor includes pixel field effect transistor and peripheral logic field effect transistor, pixel field effect transistor includes charge transfer grid and floating diffusion active area, the grid marginal area that is close to floating diffusion active area one end in the charge transfer grid has different structures with peripheral logic field effect transistor's grid marginal area, make the electric field intensity that is close to floating diffusion active area one end's grid marginal area in the charge transfer grid be less than the electric field intensity of the grid central area of charge transfer grid, in order to improve pixel field effect transistor's GIDL phenomenon, CIS's image quality is improved.

Description

Image sensor with improved pixel field effect transistor GIDL

Technical Field

The utility model relates to a sensor technology field especially relates to an improve pixel field effect transistor GIDL's image sensor.

Background

The image sensor is a functional device which converts a light image on a light-sensing surface into an electrical signal in a proportional relationship with the light image by using a photoelectric conversion function of a photoelectric device. The image sensor includes two types, namely a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a CCD (Charged Coupled Device) image sensor, and can be widely applied to digital cameras, mobile phones, medical devices, automobiles and other application occasions.

In a CMOS Image Sensor (CIS), a photosensitive pixel array and a peripheral logic circuit system are provided, the photosensitive pixel array is used to collect photoelectric signal information of an image, external light irradiates on the pixel array, a photoelectric effect occurs, and corresponding charges are generated in pixel units to collect image signals, as shown in fig. 1, the photosensitive pixel array generally includes a photodiode 101, a charge transfer gate 102, a reset transistor 103, a source follower transistor 104, and a floating diffusion active region FD, and the peripheral logic circuit system includes a peripheral logic field effect transistor to control and read the photosensitive pixel array.

CIS has become ubiquitous in our daily lives, and with the advent of the internet of things era, it has become a trend of development of CIS to promote the reduction of pixel pitches to smaller sizes and to achieve greater integration through pixel-level interconnections. However, as the manufacturing process of the CIS is miniaturized, the Gate dielectric layer of the charge transfer Gate in the CIS is thinner, the floating diffusion active region is formed shallower, and the doping amount is higher, and as shown in fig. 2, in order to prevent electrons from flowing into the photodiode 101 under a dark condition during the exposure period of the CIS, the Gate bias of the charge transfer Gate 102 is negative, so that the Gate of the charge transfer Gate 102 and the Drain thereof, i.e., the floating diffusion active region FD, form a high potential difference, which causes a depletion region on the surface of the overlapping region of the Gate and the Drain of the charge transfer Gate 102, positive and negative charge carriers respectively flow to the Drain and the substrate under the action of a strong electric field, thereby causing a Leakage current between the Drain and the Gate, causing a Gate-Induced Leakage (GIDL) phenomenon, which causes a problem of image CIS white-point bad pixels, and thus reducing the image quality of the CIS.

Therefore, it is desirable to provide an image sensor with improved pixel field effect transistor GIDL.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, the present invention provides an image sensor with improved pixel field effect transistor GIDL, which is used to solve the problem of pixel field effect transistor GIDL of the image sensor in the prior art.

In order to achieve the above and other related objects, the present invention provides an image sensor with improved pixel field effect transistor GIDL, the image sensor includes a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor includes a charge transfer gate and a floating diffusion active region, the charge transfer gate is close to a gate edge region of one end of the floating diffusion active region and a gate edge region corresponding to the peripheral logic field effect transistor have different structures, the charge transfer gate is close to an electric field strength of the gate edge region of one end of the floating diffusion active region is lower than an electric field strength of a central region of the charge transfer gate.

Optionally, the thickness of the edge region of the gate dielectric layer at the end of the charge transfer gate close to the floating diffusion active region is greater than the thickness of the central region of the gate dielectric layer.

Optionally, a dielectric constant of an edge region of the gate dielectric layer near one end of the floating diffusion active region is smaller than a dielectric constant of a central region of the gate dielectric layer.

Optionally, the gate dielectric layer of the charge transfer gate central region and the gate dielectric layer of the peripheral logic field effect transistor have the same material and thickness.

Optionally, the surface of the charge transfer gate is covered with a positively charged thin film, and the work function of the gate edge region near one end of the floating diffusion active region is changed by the positively charged thin film to reduce the electric field intensity.

Optionally, the positively charged thin film comprises one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer.

Optionally, the gate polysilicon layer at the end of the charge transfer gate close to the floating diffusion active region and the gate polysilicon layer at the end of the charge transfer gate close to the photosensitive region have different doping types, so as to change the work function of the gate edge region at the end close to the floating diffusion active region and reduce the electric field strength.

Optionally, the width of the gate polysilicon layer with different doping types near one end of the floating diffusion active region is between 40nm and 50 nm.

Optionally, the floating diffusion active region and the drain region of the peripheral logic field effect transistor both sequentially include a shallow doped drain region and a drain body region, and a depth of the shallow doped drain region of the floating diffusion active region is greater than a depth of the shallow doped drain region corresponding to the drain region of the peripheral logic field effect transistor.

Optionally, the doping concentration of the shallow doped drain region of the floating diffusion active region is less than the doping concentration of the shallow doped drain region corresponding to the peripheral logic field effect transistor drain region.

As described above, the present invention provides an image sensor for improving pixel fet GIDL, the image sensor includes a pixel fet and a peripheral logic fet, the pixel fet includes a charge transfer gate and a floating diffusion active region, a gate edge region of the charge transfer gate corresponding to one end of the floating diffusion active region and a gate edge region of the peripheral logic fet have different structures, including one or a combination of making an edge thickness of a gate dielectric layer close to one end of the floating diffusion active region greater than a center thickness of the gate dielectric layer, reducing an edge dielectric constant of the gate dielectric layer, covering a positive charge film on a surface of the charge transfer gate, doping different conductive types at an edge of a gate polysilicon layer corresponding to one end of the floating diffusion active region, increasing a depth of a shallow doped drain region of the floating diffusion active region, and reducing a doping concentration of the shallow doped drain region of the floating diffusion active region, so that an electric field strength of the gate edge region close to one end of the floating diffusion active region in the charge transfer gate is lower than an electric field strength of the gate center region of the charge transfer gate, thereby improving a GIDL phenomenon of the CIS and improving an image quality.

Drawings

Fig. 1 is a circuit diagram of an image sensor in the prior art.

Fig. 2 is a schematic cross-sectional view of the device in the region indicated by the dashed line a in fig. 1.

Fig. 3, fig. 7, and fig. 8 are schematic diagrams showing 3 different structures of the image sensor for improving the pixel field effect transistor GIDL according to the embodiment of the present invention.

Fig. 4 to 6 are schematic diagrams illustrating steps in the preparation of an image sensor according to the embodiment of fig. 3.

Fig. 9 to 12 are schematic diagrams illustrating steps in the fabrication of an image sensor according to the embodiment of fig. 8.

Fig. 13-15 illustrate formation of lightly doped drain and drain body regions based on the embodiments shown in fig. 9-12.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can be implemented or applied by other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not enlarged partially in general scale for the convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Expressions such as "between 8230 \\8230"; "between 8230"; "may be used herein, inclusive, and expressions such as" plurality "may be used, inclusive, and expressions such as two or more, unless specifically limited otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 3 to fig. 15, the present embodiment provides an image sensor for improving a pixel field effect transistor GIDL, the image sensor includes a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor includes a charge transfer gate 102 and a floating diffusion active region FD, a gate edge region of the charge transfer gate 102 close to one end of the floating diffusion active region FD and a gate edge region corresponding to the peripheral logic field effect transistor have different structures, and an electric field intensity of a gate edge region B of the charge transfer gate 102 close to one end of the floating diffusion active region FD is lower than an electric field intensity of a gate center region C of the charge transfer gate 102, so as to improve the GIDL phenomenon of the pixel field effect transistor and improve the image quality of the image sensor.

Specifically, the gate edge region of the charge transfer gate 102 corresponding to the end close to the floating diffusion active region FD and the gate edge region corresponding to the peripheral logic field effect transistor have different structures, which includes one or a combination of making the edge thickness of the gate dielectric layer 112 close to the end close to the floating diffusion active region FD larger than the center thickness of the gate dielectric layer, decreasing the dielectric constant of the edge region of the gate dielectric layer 112 close to the end close to the floating diffusion active region FD, covering the positive charge film 200 on the surface of the gate structure of the charge transfer gate 102, doping the edge of the gate polysilicon layer 122 close to the end close to the floating diffusion active region FD with different conductivity types, increasing the depth of the shallow doped drain region 401 in the floating diffusion active region FD, and decreasing the doping concentration of the shallow doped drain region 401 in the floating diffusion active region FD.

By way of example, the charge transfer gate 102 can include an N-type charge transfer gate or a P-type charge transfer gate.

Specifically, in order to make the image sensor have high mobility, the charge transfer gate 102 of the image sensor in this embodiment is an N-type charge transfer gate, that is, the charge transfer transistor in the pixel region is selected to be an N-type transistor; in the image sensor, during the exposure period, the gate bias of the charge transfer gate 102 is negative to completely prevent any electrons from flowing into the photodiode 101 in the absence of light, but the invention is not limited thereto, and a P-type charge transfer gate can be used as the charge transfer gate 102 as required. In addition, in this embodiment, the peripheral logic region may adopt the design of the peripheral logic region of the image sensor in the prior art, and adopt the existing circuit and the corresponding field effect transistor, for example, the peripheral logic region may include a circuit for forming a gate control signal of a charge transfer Transistor (TX). In an optional example, the pixel region includes a charge transfer transistor (including the charge transfer gate), a reset transistor, a source follower transistor, and a pixel selection transistor, and optionally, the transistors are NMOS transistors; in addition, the peripheral logic area comprises an NMOS tube and a PMOS tube which can form a corresponding demand circuit and can be set according to actual demands.

The following describes the structures and manufacturing methods of the image sensor of the present embodiment for improving the pixel field effect transistor GIDL with reference to fig. 3 to 15.

When the image sensor is manufactured, the pixel field effect transistor and the peripheral logic field effect transistor can be manufactured on a provided substrate based on different mask plates, so that the grid edge region of one end, close to the floating diffusion active region FD, of the charge transfer grid and the grid edge region corresponding to the peripheral logic field effect transistor have different structures, and the electric field intensity of the grid edge region corresponding to one end, close to the floating diffusion active region FD, of the charge transfer grid is lower than that of the central region of the grid of the charge transfer transistor.

As shown in fig. 3 to 6, the thickness of the edge region B of the gate dielectric layer 112 corresponding to the end of the charge transfer gate 102 close to the floating diffusion active region FD is greater than the thickness of the central region C of the gate dielectric layer 112.

Specifically, in this structure, when the image sensor is during exposure, the gate edge of the charge transfer gate 102 and the drain end thereof, that is, the floating diffusion active region FD, constitute a high potential difference, as in the B region in fig. 3. By setting the edge thickness of the gate dielectric layer 112 at one end of the charge transfer gate 102 close to the floating diffusion active region FD to be greater than the center thickness of the gate dielectric layer 112, the electric field intensity of the floating diffusion active region FD at one side close to the channel of the charge transfer gate 102 can be effectively reduced, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of a CIS image white point bad pixel, and further improving the image quality of the CIS.

As an example, the gate dielectric layer 112 of the charge transfer gate 102 may include one or a combination of a silicon dioxide layer, a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer. Specifically, in the present embodiment, the gate dielectric layer 112 is a silicon dioxide layer, but is not limited thereto.

In one example, as shown in fig. 4 to 6, the preparing of the charge transfer gate in the pixel field effect transistor may include the steps of:

s1-1: providing a substrate structure 500, wherein the substrate structure 500 may have the photodiode therein;

s1-2: forming a stacked gate dielectric material layer 501 and a gate polysilicon material layer 502 on the gate dielectric material layer 501 on the substrate structure 500;

s1-3: forming a patterned photoresist 503 on the surface of the gate polysilicon material layer 502, as shown in fig. 4;

s1-4: with the photoresist 503 as a mask, etching the gate polysilicon material layer 502 and the gate dielectric material layer 501, and removing the photoresist 503 to obtain an initial gate dielectric layer 505 and a gate electrode layer 504, as shown in fig. 5;

s1-5: at least the exposed gate dielectric material layer is oxidized, such as by obtaining exposed sidewalls of the initial gate dielectric layer 505, to obtain the gate dielectric layer 112 with an edge thickness greater than a center thickness, so as to prepare the charge transfer gate 102 having the gate dielectric layer 112 and the gate polysilicon layer 122. In one embodiment, as shown in fig. 6, an oxidation layer, for example, an oxidation layer with a thickness of 2nm, is formed on the surface of the obtained initial gate structure and the surrounding active region by using a high temperature oxidation process, for example, 900 ℃, so that a gate dielectric layer with a thin middle and a thick edge, that is, a gate dielectric layer with an edge region 507 and a central region 506, can be obtained based on the process.

The method for fabricating the charge transfer gate 102 is not limited thereto, and may be adapted according to the need, and the gate dielectric layer 112 is not limited to a silicon dioxide layer, and other insulating dielectric layers may also be used, which is not limited herein. The edge thickness of the gate dielectric layer 112 corresponding to the end of the charge transfer gate close to the floating diffusion active region FD may include 1nm to 10nm, such as 1nm, 5nm, 10nm, and may be specifically selected according to the requirement.

As an example, the gate dielectric layer 112 of the charge transfer gate 102 is made of a material layer with different material, and the dielectric constant of the edge of the gate dielectric layer 112 corresponding to the end close to the floating diffusion active region FD is smaller than the dielectric constant of the center of the gate dielectric layer 112. For example, the central region is a High-k film, such as SiN, hfO, or SiN ₂ 、Al ₂ O ₃ Layers, etc.; the edge region is a Low-k film, which may be SiO ₂ Layer to mitigate GIDL. The structure of the gate dielectric layer in this example can be obtained based on the above process, and of course, other process methods in the art can also be used.

As an example, the gate dielectric layer 112 corresponding to the central region of the charge transfer gate 102 and the gate dielectric layer corresponding to the peripheral logic field effect transistor have the same material and thickness.

Specifically, by increasing the thickness of the gate dielectric layer 112 corresponding to one end of the floating diffusion active region FD or/and reducing the dielectric constant of the gate dielectric layer 112 at one end of the charge transfer gate 102 close to the floating diffusion active region FD, the electric field strength of the floating diffusion active region FD near one side of the charge transfer gate 102 channel can be effectively reduced, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of a CIS image white dot bad pixel, and further improving the image quality of the CIS.

As shown in fig. 7, the surface of the gate structure of the charge transfer gate 102 may be covered with a positive charge film 200, so as to change the work function of the gate edge region corresponding to one end close to the floating diffusion active region FD through the positive charge film 200, thereby reducing the electric field strength of the floating diffusion active region FD region close to the channel side of the charge transfer gate 102, so as to improve the GIDL leakage problem of the pixel field effect transistor, improve the defect of a CIS image white defective pixel, and further improve the image quality of the CIS.

As an example, the positively charged thin film 200 may include one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer.

Specifically, the positive charge film 200 may be a high-dielectric-constant material layer, and may be one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer, and the method for forming the positive charge film 200 may employ a deposition method such as CVD to cover the charge transfer gate 102 near one end of the floating diffusion active region FD, so as to improve the work function of the gate edge region near one end of the floating diffusion active region FD through the positive charge film 200, reduce the electric field intensity of the gate edge region near one end of the floating diffusion active region FD of the charge transfer gate 102, improve the GIDL leakage problem of the pixel field effect transistor, improve the defect of the CIS image white spot bad pixel, and further improve the image quality of the CIS.

As shown in fig. 8, the gate polysilicon layer 122 of the charge transfer gate 102 near the end of the floating diffusion active region FD is doped differently from the gate polysilicon layer of the charge transfer gate 102 near the end of the photosensitive region, so as to change the work function of the gate edge region corresponding to the end of the floating diffusion active region FD and reduce the electric field strength.

Specifically, in this embodiment, the gate polysilicon layer 122 of the charge transfer gate 102 is an N-type doped polysilicon layer, and the P-type gate polysilicon layer 132 is formed at the edge of the gate polysilicon layer 122 close to one end of the floating diffusion active region FD, so that the gate edge region work function corresponding to one end close to the floating diffusion active region FD can be changed by the P-type gate polysilicon layer 132, so as to effectively reduce the electric field intensity of the floating diffusion active region FD close to one side of the channel of the charge transfer gate 102, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of a CIS image white dot bad pixel, and further improving the image quality of the CIS.

In one example, referring to fig. 9-12, forming the charge transfer gates of different doping types may include the steps of:

s2-1: providing a substrate structure 600, wherein the photodiode can be arranged in the substrate structure 600;

s2-2: forming a stacked gate dielectric material layer 601 and an N-type gate polysilicon material layer 602 on the gate dielectric material layer 601 on the substrate structure 600, as shown in fig. 9;

s2-3: performing ion implantation on the edge region of the N-type gate polycrystalline silicon material layer 602 to form a P-type gate polycrystalline silicon material layer 603, as shown in fig. 10;

s2-4: forming a patterned photoresist 604, as shown in fig. 11, etching the N-type gate polysilicon material layer 602 and the gate dielectric material layer 601 by using the photoresist 604 as a mask, forming the charge transfer gate 605 including the gate dielectric layer 606, the N-type gate polysilicon layer, and the P-type gate polysilicon layer 605a is located at an edge of the N-type gate polysilicon layer near one end of the floating diffusion active region FD, as shown in fig. 12.

The method for fabricating the charge transfer gate 102 is not limited thereto, and may be adapted according to the need, and is not limited thereto. The width of the P-type gate polysilicon layer 132 corresponding to the end close to the floating diffusion active region FD may be 40nm to 50nm, such as 40nm, 45nm, 50nm, and may be specifically selected according to the requirement.

Further, the charge transfer gate 102 may further include a gate sidewall 300, the floating diffusion active region FD may include a shallow doped drain region 401 and a drain body region 402, the shallow doped drain region 401 is located above the drain body region 402, and the doping concentration of the shallow doped drain region 401 is less than that of the drain body region 402, so that doped regions with different doping amounts may be prepared in the floating diffusion active region FD by the gate sidewall 300. The utility model discloses can reduce and be close to charge transfer gate 102 channel one side float the electric field strength that diffuses the active area FD district, thereby improve pixel field effect transistor 102's GIDL electric leakage problem improves the shortcoming of CIS image white point bad pixel, and then has promoted CIS's image quality.

In one example, referring to fig. 13 to 14, the step of forming the lightly doped drain region and the drain body region may include:

the steps S2-1 to S2-4 are executed, but not limited to, the steps S1-1 to S1-5 may be executed, and in this embodiment, taking the steps S2-1 to S2-4 as an example, as shown in fig. 9 to 12, the following steps are executed:

s2-5: performing ion implantation to form the lightly doped drain region 607 of N-type light doping, as shown in fig. 13;

s2-6: forming the gate sidewall 608, as shown in fig. 14, the material of the gate sidewall 608 is not limited herein;

s2-7: the drain body region 609 is formed on the basis of the gate sidewall 608, as shown in fig. 15.

As an example, the floating diffusion active region FD and the drain region of the peripheral logic field effect transistor each sequentially include a shallow doped drain region and a drain body region, and a depth of the shallow doped drain region 401 corresponding to the floating diffusion active region FD is greater than a depth of the shallow doped drain region corresponding to the peripheral logic field effect transistor; and/or the doping concentration of the shallow doped drain region 401 corresponding to the floating diffusion active region FD is less than the doping concentration of the shallow doped drain region corresponding to the peripheral logic field effect transistor.

Specifically, when the floating diffusion active region FD is formed, the shallow doped drain region 401 with a large depth may be formed in the pixel field effect transistor through a high-energy and low-dose doping manner, so that the electric field intensity of the floating diffusion active region FD near the channel side of the charge transfer gate 102 may be effectively reduced, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of a CIS image white spot and improving the image quality of the CIS. In addition, the low doping dose can further contribute to the reduction of the electric field intensity of the corresponding position, and the GIDL is improved.

To sum up, the utility model discloses an improve image sensor of pixel field effect transistor GIDL, image sensor includes pixel field effect transistor and peripheral logic field effect transistor, pixel field effect transistor includes charge transfer grid and floating diffusion active area, the grid marginal zone that is close to floating diffusion active area one end correspondence in the charge transfer grid has different structures with the grid marginal zone that peripheral logic field effect transistor corresponds, include that the marginal thickness that makes the grid dielectric layer that is close to floating diffusion active area one end is greater than the central thickness of grid dielectric layer, reduce the marginal dielectric constant of grid dielectric layer, cover positive charge film on the surface of charge transfer grid, carry out the doping of different conductivity types near the grid polycrystalline silicon layer edge that floating diffusion active area one end corresponds, increase the shallow doping drain region depth of floating diffusion active area, and reduce one kind or the combination in the doping concentration of the shallow doping drain region of floating diffusion active area, make the grid marginal zone that is close to floating diffusion active area one end in the charge transfer grid be less than the electric field intensity of grid central zone of charge transfer grid, in order to improve pixel field effect transistor GIDL phenomenon, improve the image quality of CIS.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. An image sensor for improving GIDL is characterized in that the image sensor comprises a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor comprises a charge transfer grid and a floating diffusion active region, the grid edge region of one end, close to the floating diffusion active region, of the charge transfer grid and the grid edge region corresponding to the peripheral logic field effect transistor have different structures, and the electric field intensity of the grid edge region of one end, close to the floating diffusion active region, of the charge transfer grid is lower than that of the central region of the charge transfer grid.

2. The image sensor of claim 1, wherein: the thickness of the edge area of the grid dielectric layer at one end of the charge transfer grid, which is close to the floating diffusion active area, is larger than that of the central area of the grid dielectric layer.

3. The image sensor of claim 2, wherein: the dielectric constant of the edge area of the grid dielectric layer close to one end of the floating diffusion active area is smaller than that of the central area of the grid dielectric layer.

4. The image sensor of claim 2, wherein: the grid dielectric layer of the central area of the charge transmission grid and the grid dielectric layer of the peripheral logic field effect transistor have the same material and thickness.

5. The image sensor of claim 1, wherein: the surface of the charge transmission grid electrode is covered with a positive charge film, and the work function of the edge area of the grid electrode close to one end of the floating diffusion active area is changed through the positive charge film so as to reduce the electric field intensity.

6. The image sensor of claim 5, wherein: the positive charge film comprises one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer and a silicon oxynitride layer.

7. The image sensor of claim 1, wherein: the grid polycrystalline silicon layer at one end of the charge transfer grid close to the floating diffusion active region and the grid polycrystalline silicon layer at one end of the charge transfer grid close to the photosensitive region have different doping types so as to change the work function of the grid edge region at one end of the floating diffusion active region and reduce the electric field intensity.

8. The image sensor of claim 7, wherein: the width of the grid polycrystalline silicon layer with different doping types close to one end of the floating diffusion active region is between 40nm and 50 nm.

9. The image sensor of any one of claims 1-8, wherein: the floating diffusion active region and the drain region of the peripheral logic field effect transistor sequentially comprise a shallow doped drain region and a drain main body region, and the depth of the shallow doped drain region of the floating diffusion active region is larger than that of the shallow doped drain region corresponding to the drain region of the peripheral logic field effect transistor.

10. The image sensor of claim 9, wherein: and the doping concentration of the shallow doping drain region of the floating diffusion active region is less than that of the shallow doping drain region corresponding to the peripheral logic field effect transistor drain region.

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