CN116936583A - Pixel structure, preparation method, image sensor and electronic equipment - Google Patents
Pixel structure, preparation method, image sensor and electronic equipment Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 230000005540 biological transmission Effects 0.000 claims abstract description 187
- 238000012546 transfer Methods 0.000 claims abstract description 101
- 238000009792 diffusion process Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 46
- 230000008569 process Effects 0.000 claims description 41
- 239000003989 dielectric material Substances 0.000 claims description 33
- 125000006850 spacer group Chemical group 0.000 claims description 32
- 238000006243 chemical reaction Methods 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 22
- 238000007254 oxidation reaction Methods 0.000 claims description 22
- 239000007772 electrode material Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 230000003287 optical effect Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 32
- 238000013461 design Methods 0.000 abstract description 4
- 241000519995 Stachys sylvatica Species 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000001105 regulatory effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000004075 alteration Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 150000002500 ions Chemical group 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
The invention provides a pixel structure, a preparation method, an image sensor and electronic equipment. The pixel structure design of the invention is provided with two transmission control gates, namely a first transmission control gate and a second transmission control gate, which can flexibly regulate and control the on-off of the device and the electric field between the transmission control gate and other parts (such as a floating diffusion region) based on the voltage applied to the two transmission control gates so as to meet the actual requirements of the device. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on two transfer control gates. When a high potential difference is formed between the grid electrode of the charge transfer transistor and the floating diffusion active region, the high potential difference can be reduced through the second transfer control gate, so that the grid electrode induced electric leakage is reduced, the problem of bad pixels of image white spots is solved, and the image quality of the CIS is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a pixel structure, a preparation method, an image sensor and electronic equipment.
Background
Today, CMOS Image Sensors (CIS) have been ubiquitous in our everyday life, ranging from smartphones to automobiles, security cameras, robots, and AR/VR entertainment devices. As we gradually transition to the internet of things age, the strong demand for intelligent, interconnected and autonomous consumer products has driven this trend. In response, leading image sensor designers, suppliers, and world foundries continue to advance technological innovations to facilitate pixel pitch scaling to smaller dimensions and greater CIS/ISP integration through pixel-level interconnects. Recently, CMOS image sensor products of smaller pixel size, e.g., 0.7um pixels, are demanded under the strong demand driving force of the mobile phone market. The CIS pixel size is continuously reduced, so that production merchants adopt a process platform with smaller line width and higher precision to manufacture products. Based on high mobility, most CIS use n-type metal oxide semiconductor (nMOS) transistors, including charge transfer transistors and source follower amplifiers.
Along with the miniaturization trend of the production process, the gate oxide layer and the side wall process of the nMOS charge transport transistor are thinner and shorter, so that the electric field between the charge transport transistor and the drain end (i.e., the floating diffusion active region) of the nMOS charge transport transistor is difficult to effectively regulate, and in addition, the trend also promotes the problem of gate induced leakage (GIDL) to be more obvious. During exposure of the CIS pixel, the gate bias of the charge transfer transistor is negative to completely prevent any electrons from flowing into the photodiode in the dark condition; the gate of the charge transfer transistor and its drain terminal (i.e., the floating diffusion active region) form a high potential difference, and GIDL phenomenon easily occurs. GIDL phenomenon causes a problem of a bad pixel of a CIS image white point, thereby degrading the image quality of the CIS.
Therefore, it is necessary to provide a pixel structure, a manufacturing method, an image sensor, and an electronic device to solve the above technical problems in the prior art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a pixel structure, a manufacturing method thereof, an image sensor, and an electronic device, which are used for solving the problems that in the prior art, an electric field between a charge transfer transistor and a floating diffusion active region is difficult to be effectively regulated and controlled, and gate induced leakage is difficult to be effectively solved.
To achieve the above and other related objects, the present application provides a pixel structure including:
a semiconductor substrate having a first surface and a second surface opposite to each other;
a photoelectric conversion region extending from the first face into the semiconductor substrate for receiving an optical signal to generate an electrical signal;
A floating diffusion region extending from the first face into the semiconductor substrate and having a pitch from the photoelectric conversion region;
the first transmission control gate and the second transmission control gate are arranged on the first surface and correspondingly and sequentially arranged between the photoelectric conversion region and the floating diffusion region, so that the electric signals of the photoelectric conversion region are transferred to the floating diffusion region based on the first transmission control gate and the second transmission control gate.
Optionally, the first transmission control gate is at least located on the first surface, the second transmission control gate is at least located on the first surface, and a control gate overlapping region is further formed between the first transmission control gate and the second transmission control gate, so as to form a communicating channel between the photoelectric conversion region and the floating diffusion region.
Optionally, the width of the control gate overlap region is less than 0.2 μm.
Optionally, the second transmission control gate extends onto the first transmission control gate or the first transmission control gate extends onto the second transmission control gate to form the control gate overlap region.
Optionally, the first transmission control gate includes a first gate dielectric layer and a first transmission control gate electrode stacked from bottom to top, the second transmission control gate includes a second gate dielectric layer and a second transmission control gate electrode stacked from bottom to top, the first transmission control gate electrode extends beyond the outer edge of the first gate dielectric layer near one side of the second transmission control gate or the second transmission control gate electrode extends beyond the outer edge of the second gate dielectric layer near one side of the first transmission control gate to form a control gate overlapping portion, and a spacer is further formed between the first transmission control gate electrode and the second transmission control gate electrode corresponding to the control gate overlapping portion, and the control gate overlapping portion and the spacer form the control gate overlapping region.
Optionally, the thicknesses of the first gate dielectric layer and the second gate dielectric layer are the same or different.
Optionally, the thickness of the first gate dielectric layer or the second gate dielectric layer corresponding to the side portion of the spacer is the same.
Optionally, the materials of the first gate dielectric layer, the second gate dielectric layer and the spacer are the same or different.
Optionally, the spacer is in contact with a side surface of the corresponding first gate dielectric layer or a side surface of the corresponding second gate dielectric layer.
Optionally, the thickness of the first gate dielectric layer is less than 10nm, the thickness of the second gate dielectric layer is less than 10nm, and the thickness of the spacer is less than 10nm.
Optionally, at least the second transmission control gate has an overlap region with the floating diffusion region.
Optionally, the projection area of the first transmission control gate on the first surface is larger than the projection area of the second transmission control gate on the first surface.
Optionally, the working time sequence of the first transmission control gate and the working time sequence of the second transmission control gate are the same, the off-state voltage of the second transmission control gate is larger than the off-state voltage of the first transmission control gate, and the on-state voltage is larger than or equal to the on-state voltage of the first transmission control gate.
The invention also provides an image sensor comprising the pixel structure according to any one of the above schemes.
The invention also provides electronic equipment comprising the image sensor according to any one of the schemes.
The invention also provides a preparation method of the pixel structure, wherein the preparation method can be any one of the preparation methods of the pixel structure in the scheme, and of course, any one of the preparation methods of the pixel structure in the scheme can also be prepared by other methods. The preparation method of the pixel structure comprises the following steps:
providing the semiconductor substrate having the first and second opposite sides;
forming the first transmission control gate and the second transmission control gate on a first surface of the semiconductor substrate;
the photoelectric conversion region and the floating diffusion region are prepared in the semiconductor substrate from the first face.
Optionally, when the first transmission control gate includes the first gate dielectric layer and the first transmission control gate electrode, the second transmission control gate includes the second gate dielectric layer and the second transmission control gate electrode, and the control gate overlapping region formed by the control gate overlapping portion and the spacer is formed, the spacer and the first gate dielectric layer or the second gate dielectric layer are formed simultaneously.
Optionally, the forming of the overlapping area of the first transmission control gate, the second transmission control gate and the control gate includes the following steps:
forming a second transmission control gate on the first surface of the semiconductor substrate;
forming a first gate dielectric material layer on the exposed surface of the second transmission control gate and the surrounding first surface;
forming a first transmission control gate electrode material layer on the first gate dielectric material layer;
etching the first transmission control gate electrode material layer to form the first transmission control gate electrode and the control gate overlapping part;
etching the first gate dielectric material layer to form the first gate dielectric layer and the spacer;
or,
forming the first transmission control gate on the first surface of the semiconductor substrate;
forming a second gate dielectric material layer on the exposed surface of the first transmission control gate and the surrounding first surface;
forming a second transmission control gate electrode material layer on the second gate dielectric material layer;
etching the second transmission control gate electrode material layer to form the second transmission control gate electrode and the control gate overlapping part;
and etching the second gate dielectric material layer to form the second gate dielectric layer and the spacer.
Optionally, forming the first transmission control gate includes forming the first gate dielectric layer based on a first oxidation process, wherein a temperature of the first oxidation process is greater than 600 ℃; and/or forming the second gate dielectric material layer based on a second oxidation process, wherein the temperature of the second oxidation process is greater than 600 ℃; and/or forming the second transmission control gate includes forming the second gate dielectric layer based on a third oxidation process, the third oxidation process having a temperature greater than 600 ℃; and/or forming the first gate dielectric material layer based on a fourth oxidation process, wherein the temperature of the fourth oxidation process is greater than 600 ℃.
As described above, in the pixel structure, the manufacturing method, the image sensor and the electronic device of the present invention, two transmission control gates, namely, the first transmission control gate and the second transmission control gate, are formed in the pixel structure design of the present invention, so that the switching on/off of the device and the electric field between the transmission control gate and other parts (such as the floating diffusion region) can be flexibly regulated and controlled based on the voltage applied to the two transmission control gates, so as to meet the actual requirements of the device, and improve the flexibility of the device control. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on the two transfer control gate electrodes. When a high potential difference is formed between the gate electrode (such as the first transfer control gate) of the charge transfer transistor and the drain electrode (floating diffusion active region) thereof, the high potential difference can be reduced through the second transfer control gate, thereby reducing gate induced leakage (GIDL), improving the problem of white dot and bad pixels of the CIS image, and improving the image quality of the CIS.
Drawings
Fig. 1 shows a pixel circuit of an image sensor commonly used in the prior art.
Fig. 2 is a cross-sectional view of a corresponding device structure in the dashed box of the pixel circuit shown in fig. 1.
FIG. 3 is a graph of TCAD simulation data of highest electric field strength versus gate polysilicon layer voltage for the structure of FIG. 2.
Fig. 4 is a schematic diagram of a pixel circuit corresponding to the pixel structure provided by the present invention.
Fig. 5 shows a process flow diagram of the preparation of the pixel structure according to the present invention.
Fig. 6 to 19 are schematic views of a pixel structure and a structure obtained in each step in the manufacturing process according to the first embodiment of the present invention.
Fig. 20 is a schematic diagram of a pixel structure according to a second embodiment of the invention.
Description of element reference numerals
201. Photodiode having a high-k-value transistor
202. First transmission control gate
203. Second transmission control gate
204. Reset transistor
205. Source follower transistor
206. Pixel selection transistor
300. Semiconductor substrate
300a first side
300b second side
301. Second gate dielectric material layer
302. Second transmission control gate material layer
303. First patterned mask layer
304. Second transmission gate control gate
305. Second gate dielectric layer
306. Second transmission control gate
307. First gate dielectric material layer
308. First transmission control gate material layer
309. Second patterned mask layer
310. First transmission control gate
311. Control door overlapping
312. First gate dielectric layer
313. First transmission control gate
314. Spacing part
315. Control door overlap
316. Photoelectric conversion region
317. Floating diffusion region
S1 to S3 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In addition, "between … …" as used in the present application includes two end points.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
In the image sensor pixel of the prior art, a circuit schematic structure as shown in fig. 1 is mostly used, and the image sensor pixel includes a photodiode 101, a charge transfer transistor 102, a reset transistor 103, a source follower transistor 104, a pixel selection transistor 105, and a floating diffusion active region FD. In addition, along with the promotion of the mobile market of the mobile phone on the miniaturization requirement of the image sensor product, a sharing layout mode is often adopted among pixels; in the image sensor product with small-area pixels, a sharing structure mode is often adopted between pixels, and a plurality of photodiodes 101 and charge transfer transistors 102 are connected in parallel and are commonly connected to the FD end of a floating diffusion active area, for example, a four-pixel sharing structure mode published by application publication number CN110336953a and a two-pixel sharing structure mode published by application publication number CN110061026 a.
Along with the miniaturization trend of the production process, the gate oxide layer and the side wall process of the nMOS charge transfer transistor are thinner and shorter, the electric field between the charge transfer transistor and the drain end (i.e. the floating diffusion active region) of the charge transfer transistor is difficult to effectively regulate, the problem of gate induced leakage (GIDL) is more obvious, and the white point bad pixels are difficult to effectively solve. The image sensor collects white point bad pixels of an image, and the white point bad pixels mainly comprise two sources: a photodiode 101 and a floating diffusion active region FD. Specifically, the photodiode 101 generates a white dot bad pixel due to pixel signal aberration caused by leakage of the channel of the charge transfer transistor 102, and in order to suppress the white dot factor, the gate of the charge transfer transistor 102 is usually set to be biased at a negative voltage in the prior art; however, the negative bias charge transfer transistor 102 is more prone to gate induced leakage (GIDL) drawbacks, which can cause signal aberrations in the floating diffusion active region FD, which can cause the image pixel to appear white and bright. Particularly, the pixels in the sharing structure mode and the pixels in the sharing layout mode are more prone to suffering from the defects of white point bad pixels, wherein one pixel has the problem of GIDL, and then the image signals of all the pixels in the sharing structure are in abnormal conditions of white and shiny.
Fig. 2 shows a schematic cross-sectional view of the device of dashed box 100 shown in fig. 1. In fig. 2, a schematic cross-sectional view includes a photodiode 101, a gate oxide layer 201 of a charge transfer transistor 102, a gate polysilicon layer 202 of the charge transfer transistor 102, a floating diffusion active region FD (n+ region in fig. 2) which is a high concentration N-type impurity ion region, and a P-epi (P-type semiconductor silicon substrate). During normal operation of the image sensor pixel, the n+ region of FD is set to a high voltage state, e.g., 2.5V, and the gate polysilicon layer 202 is set to a negative voltage, e.g., -2V; the gate polysilicon layer 202 and the N+ region of the FD are in a high-voltage bias state, the gate oxide layer 201 region and the N+ region silicon surface between the overlapped region are in a high-electric field intensity state, and the high-electric field intensity state easily causes charge tunneling phenomenon between the gate polysilicon layer 202 and the N+ region of the FD, thereby causing the defects of GIDL; the existence of silicon dangling bonds and defects on the silicon surface of the N+ region between the overlapped regions can capture and release charges tunneled from the grid polycrystalline silicon layer 202, and the strength of GIDL is further boosted under the action of a high electric field; an exponentially increasing relationship is present between the strength of GIDL and the highest electric field strength. In addition, fig. 3 is a TCAD (process computer aided design) simulation data diagram of the highest electric field strength and the voltage of the gate polysilicon layer 202 in the device of the structure of fig. 2, and it is known from fig. 3 that the more negative the voltage of the gate polysilicon layer 202 is, the higher the highest electric field strength is, and the more obvious GIDL problem is caused by the higher highest electric field strength.
In view of the above problems, the present invention provides a pixel structure, a manufacturing method thereof, an image sensor, and an electronic device, where the pixel structure includes: the semiconductor device comprises a semiconductor substrate, a photoelectric conversion region, a floating diffusion region, a first transmission control gate and a second transmission control gate. In the pixel structure design, two transmission control gates, namely a first transmission control gate and a second transmission control gate, are formed, and the switching-on and switching-off of the device and the electric field between the transmission control gate and other parts (such as a floating diffusion region) can be flexibly regulated and controlled based on the voltage applied to the two transmission control gates, so that the actual requirements of the device are met, and the flexibility of the device control is improved. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on the two transfer control gate electrodes. When a high potential difference is formed between the gate electrode (such as the first transfer control gate) of the charge transfer transistor and the drain electrode (floating diffusion active region) thereof, the high potential difference can be reduced through the second transfer control gate, thereby reducing gate induced leakage (GIDL), improving the problem of white dot and bad pixels of the CIS image, and improving the image quality of the CIS.
Fig. 4 is a pixel circuit diagram corresponding to the pixel structure provided by the invention. Fig. 5 shows a process flow diagram of the fabrication of a pixel structure according to the present invention. Fig. 6-19 are schematic views showing a pixel structure and a structure obtained by each step in the preparation process of the pixel structure. Fig. 20 is a schematic view of another pixel structure according to the present invention.
The pixel structure and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
Embodiment one:
as shown in fig. 4, a pixel circuit diagram corresponding to the pixel structure provided by the invention is shown. The pixel circuit in fig. 4 includes a photodiode 201, a first transfer control gate 202, a second transfer control gate 203, a reset transistor 204, a source follower transistor 205, and a pixel select transistor 206, fd is a floating diffusion active region, and a dashed box 200 marks the location of the device. In the pixel circuit of this embodiment, two transfer transistors are disposed between the photoelectric conversion region (e.g., photodiode 201) and the floating diffusion FD, so as to perform charge transfer in the floating diffusion region, and the two transfer control gates can flexibly modulate the electric field.
As shown in fig. 5, the present invention provides a method for manufacturing a pixel structure, where the pixel structure provided by the present invention is preferably manufactured by using the manufacturing method provided by the present embodiment, and of course, other methods may also be used for manufacturing the pixel structure. As shown in fig. 5, the method for manufacturing the pixel structure provided in this embodiment includes the following steps:
s1: providing the semiconductor substrate having the first and second opposite sides;
S2: forming the first transmission control gate and the second transmission control gate on a first surface of the semiconductor substrate;
s3: the photoelectric conversion region and the floating diffusion region are prepared in the semiconductor substrate from the first face.
The method for fabricating a pixel structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein fig. 6-19 represent schematic structural diagrams obtained by each step in the fabrication of the pixel structure according to the present embodiment. In addition, it should be noted that the above sequence does not strictly represent the preparation sequence of the pixel structure protected by the present invention, and those skilled in the art may vary depending on the actual process steps. Fig. 4 shows only the sequence of steps for preparing a pixel structure in one example provided by the present invention.
First, as shown in S1 in fig. 5 and fig. 6, a semiconductor substrate 300 having a first face 300a and a second face 300b opposite to each other is provided.
Specifically, the semiconductor substrate 300 may be any structure used for preparing each functional area of the image sensor in the field of image sensors, such as preparing a photosensitive element and each control transistor of a CMOS image sensor based on the semiconductor substrate 300. The semiconductor substrate 300 may be a structure formed of a single material layer, including but not limited to a silicon substrate, in which elements in each region are formed, and may be single crystal silicon, single crystal germanium, polycrystalline silicon, amorphous silicon, a silicon germanium compound, or the like.
In addition, the semiconductor substrate 300 may be a stacked structure of two or more material layers, and each region may be prepared in any desired layer. For example, the semiconductor substrate 300 includes a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate in which the photosensitive elements, the respective control transistors, and the like are prepared, as a back-illuminated (BSI) image sensor may be prepared based on the above-described structure. In addition, the semiconductor substrate 300 may be silicon on insulator (Silicon On Insulater, SOI). In addition, the semiconductor substrate 300 may also be a structure with N-type doping or P-type doping to meet the functional requirements of the device.
In this embodiment, the semiconductor substrate 300 is selected to be P-epi single crystal material with the silicon substrate exposed on the surface.
Next, as shown in S2 in fig. 5 and fig. 18, a first transfer control gate 306 and a second transfer control gate 313 are formed on the first surface of the semiconductor substrate 300.
As an example, the first transmission control gate 313 includes a first gate dielectric layer 312 and a first transmission control gate electrode 310, and the second transmission control gate 306 includes a second gate dielectric layer 305 and a second transmission control gate electrode 304.
As an example, as shown in fig. 18, the first transfer control gate 313 is located on the surface of the first face 300a of the semiconductor substrate 300, the second transfer control gate 306 is located on the surface of the first face 300a of the semiconductor substrate 300, and a control gate overlap region 315 is formed between the first transfer control gate 313 and the second transfer control gate 306 to form a channel communicating between the photoelectric conversion region and the floating diffusion region.
In a further example, the first transmission control gate electrode 312 extends beyond the outer edge of the second gate dielectric layer 312 near the second transmission control gate 306 to form a control gate overlapping portion 311, and a spacer portion 314 is further formed between the second transmission control gate electrode 304 and the first transmission control gate electrode 310 corresponding to the control gate overlapping portion 311, and the control gate overlapping portion 311 and the spacer portion 314 form a control gate overlapping region 315.
In an example, when the control gate overlapping region 315 formed by the control gate overlapping portion 311 and the spacer 314 is formed, the spacer 314 is formed simultaneously with the first gate dielectric layer 312.
In this embodiment, the formation of the first transmission control gate 313, the second transmission control gate 306 and the control gate overlap region 315 includes the following steps:
as shown in fig. 7 to 12, a second transfer control gate 306 is formed on the first surface 300a of the semiconductor substrate 300; the specific process can be as follows: as shown in fig. 7, a second gate dielectric material layer 301 is formed on the surface of the first surface 300a, where the material of the second gate dielectric material layer 301 may be an existing gate oxide material, including but not limited to silicon oxide.
In an example, the second gate dielectric material layer 310 is formed through a third oxidation process at a temperature of 600 ℃ or more, for example, 800 ℃, 900 ℃, 1000 ℃. The oxidation time length can be adjusted, and the gate oxide material layer with preset thickness can be manufactured to obtain the gate oxide layer with required thickness, and the thickness can be consistent with the technical parameters of the prior process platform.
Next, as shown in fig. 8, a second transfer control gate electrode material layer 302 is formed on the second gate dielectric material layer 301. The second transmission gate electrode material layer 302 may be formed by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), and the like, and the material may include, but is not limited to, polysilicon, so as to obtain a subsequent second transmission control gate electrode.
Next, as shown in fig. 9-12, the second transmission control gate electrode material layer 302 and the second gate dielectric material layer 310 are etched to form a second transmission control gate 306 including a second gate dielectric layer 305 and a second transmission gate control gate electrode 304 stacked from bottom to top. The specific process steps can be as follows:
first, a first patterned mask layer 303, such as spin-on photoresist, is obtained, and developed, as shown in fig. 9, a layer of photoresist is spin-coated as a photoresist over the polysilicon layer deposited in the previous step, and the photoresist is left only at the position where the second transmission control gate 306 is formed in a preset manner; then, the second transmission control gate electrode material 302 is etched, for example, polysilicon material is etched, as shown in fig. 10, to etch away the unwanted polysilicon layer; then, after etching is completed, removing the first patterned mask layer 303, as shown in fig. 11, and removing the photoresist; finally, the second gate dielectric material layer 301 is etched by a wet method, as shown in fig. 12, for example, the unnecessary oxide layer is etched away, so as to obtain a second gate dielectric layer 305.
Continuing, as shown in fig. 13, a first gate dielectric material layer 307 is formed on the exposed surface of the second transmission control gate 306 and the first surface 300a of the surrounding semiconductor substrate 300.
In an example, the first gate dielectric material layer 307 is formed through a fourth oxidation process at a temperature of 600 ℃ or more, for example, 800 ℃, 900 ℃, 1000 ℃. The oxidation time length can be adjusted, and a material layer with a preset thickness can be manufactured to obtain a subsequent first gate dielectric layer and a spacer.
Next, as shown in fig. 14, a first transfer control gate electrode material layer 308 is formed on the first gate dielectric material layer 307. The first transfer gate electrode material layer 308 may be formed by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD) and the like, including but not limited to polysilicon, to obtain a subsequent first transfer control gate electrode and control gate overlap.
Next, as shown in fig. 15-17, the first transmission control gate electrode material layer 308 is etched to form the first transmission control gate electrode 310 and the control gate overlap 311. The second patterned mask layer 309 may be formed first, as shown in fig. 15, by spin-coating a photoresist layer over the polysilicon layer deposited in the previous step, and developing, and spin-coating a photoresist layer as a photoresist layer, where the photoresist layer is left only at the position where the first transmission control gate and the control gate overlap region are formed in the preset; then, as shown in fig. 16, the first transmission control gate electrode material layer 308 is etched, such as etching polysilicon material, to etch away unwanted polysilicon layers; finally, as shown in fig. 17, the second patterned mask layer 309 is removed, and after etching, the photoresist is removed, so as to obtain the first transmission control gate electrode 310 and the control gate overlapping portion 311, which are formed at the same time, thereby simplifying the process.
Next, as shown in fig. 18, the first gate dielectric material layer 307 is etched to form the first gate dielectric layer 312 and the spacers 314, such as etching oxide on the exposed silicon substrate surface and the polysilicon surface, thereby obtaining a first transmission control gate 313 and a control gate overlap region 315 that is advantageous for forming a continuous channel between the two transmission control gates.
Finally, as shown in S3 in fig. 5 and fig. 19, a photoelectric conversion region (PD) 316 and a floating diffusion region (FD) 317 are prepared in the semiconductor substrate 300 from the first face 300 a.
Specifically, the photoelectric conversion region (PD) 211 and the floating diffusion region (FD) 212 may be formed by an existing ion implantation process, for example, n-type ion doping may be performed by an existing process. In an alternative example, the photoelectric conversion region 211 may form a photodiode. In addition, in other embodiments, the photoelectric conversion element may be manufactured first and then the transmission control gate may be manufactured, and of course, other suitable manufacturing sequences may be used.
It should be noted that, the pixel structure obtained in this embodiment includes: a semiconductor substrate 300, a photoelectric conversion region 316, a floating diffusion region 317, a first transfer control gate 313 and a second transfer control gate 306. The semiconductor substrate 300 has a first surface 300a and a second surface 300b opposite to each other; a photoelectric conversion region 316 extends from the first surface 300a into the semiconductor substrate 300 for receiving an optical signal to generate an electrical signal; floating diffusion 317 extends from the first face 300a into the semiconductor substrate 300 with a spacing from the photoelectric conversion region 316; in addition, a first transmission control gate 313 and a second transmission control gate 306 are disposed on the first surface 300a and are correspondingly and sequentially disposed between the photoelectric conversion region 316 and the floating diffusion region 317, so as to transfer the electric signal of the photoelectric conversion region 316 to the floating diffusion region 317 based on the first transmission control gate 313 and the second transmission control gate 306. It will be appreciated that the edges of the transfer control gate electrode may be aligned with the edges of the corresponding photoelectric conversion region 316 or floating diffusion region 317, or the edges of the transfer control gate electrode may overlap with both sides to form an effective device channel for charge transfer of the image sensor, and in the present invention, the second transfer control gate electrode 306 has an overlapping region with at least the floating diffusion region 317, see the dashed box portion in fig. 19, to transfer the electrical signal of the photoelectric conversion region 316 to the floating diffusion region 317 based on the transfer control gate electrode.
Two transmission control gates, namely a first transmission control gate 313 and a second transmission control gate 306, are formed, and the switching on and off of the device and the electric field between the transmission control gate and other parts (such as a floating diffusion region) can be flexibly regulated and controlled based on the voltage applied to the two transmission control gates, so that the actual requirement of the device is met, and the flexibility of device control is improved. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on the two transfer control gate electrodes. It is also considered that when an electric field is formed between the first transfer control gate 313 and the floating diffusion 317, modulation can be performed based on the introduction of the second transfer control gate 306. When a high potential difference is formed between the gate electrode (e.g., the first transfer control gate) of the charge transfer transistor and the drain electrode (floating diffusion active region) thereof, such as when the gate bias voltage of the charge transfer transistor (the first transfer control gate) is negative during exposure of the CIS pixel, the high potential difference can be reduced by the second transfer control gate 306, thereby reducing gate induced leakage (GIDL), improving the problem of white dot bad pixels of the CIS image, and improving the image quality of the CIS.
As an example, the width d of the control gate overlap region 315 is less than 0.2 μm, which may be, for example, 0.1 μm, 0.15 μm. Thereby facilitating the formation of an effective continuous channel while reducing the impact of the overlapping control region material layer on device performance.
As an example, the thicknesses of the first gate dielectric layer 312 and the second gate dielectric layer 305 are the same or different; both can be designed according to actual requirements. As an example, the thicknesses of the first gate dielectric layer 312 and the spacer 314 are the same, so that the spacer is advantageously prepared simultaneously with other material layers, and no additional process is wasted to form the control gate overlapping region.
As an example, the thickness of the first gate dielectric layer is less than 10nm, and may be 6nm or 8nm; the thickness of the second gate dielectric layer is smaller than 10nm and can be 6nm or 8nm; the thickness of the spacer is less than 10nm, and may be 6nm or 8nm.
As an example, the materials of the first gate dielectric layer 312, the second gate dielectric layer 305, and the spacer 314 are the same or different. As an example, the spacer 314 contacts the corresponding side of the first gate dielectric layer 312 to facilitate isolation of the transmission control gate electrode and prevent electrical connection between the two transmission control gates.
As an example, at least the second transfer control gate 306 and the floating diffusion 317 have an overlapping region therebetween, as shown by a dotted line box in fig. 19, so that an electric field existing in the overlapping region can be effectively adjusted based on the second transfer control gate 306, for example, an electric field in the overlapping region can be improved, GIDL of a device can be effectively improved, white point can be improved, and image quality can be improved.
As an example, the projected area of the first transfer control gate 313 on the first surface is larger than the projected area of the second transfer control gate 306 on the first surface. Thereby facilitating the transfer control of charges between the photoelectric conversion region 316 and the floating diffusion region 317 based on the first transfer control gate 313 and the modulation of the electric field based on the second transfer control gate 306.
As an example, the first transmission control gate 313 and the second transmission control gate 306 have the same operation timing, and the off-state voltage of the second transmission control gate 306 is greater than the off-state voltage of the first transmission control gate 313, and the on-state voltage of the second transmission control gate 306 is greater than or equal to the on-state voltage of the first transmission control gate 313.
Specifically, in one example, during operation of the device, the operating voltage of the first transmission control gate 313 is negative (e.g., typically less than-0.5V), and the operating voltage of the second transmission control gate 306 is greater than the low voltage of the first transmission control gate 313 (e.g., 0V); in another example, during operation of the device, the operating voltage of the first transmission control gate 313 is high (e.g., the on-state voltage of the pipe), and the second transmission control gate 306 is set to be greater than or equal to the on-state voltage of the first transmission control gate 313. In normal operation of the device, for example, when the image sensor pixel is in normal operation, the operation timing of the first transmission control gate 313 and the second transmission control gate 306 are the same, for example, the operation timing of the first transmission control gate and the second transmission control gate may be identical to that of the image sensor pixel in the prior art, and charge formation and charge transmission may be performed. In this example, the off voltage of the second transfer control gate 306 is lower than that of the first transfer control gate 313, and the electric field strength formed by the second transfer control gate 306 and the floating diffusion FD (e.g., n+ region) is out of relationship with the first transfer control gate 313, and the electric field strength can be adjusted by using the set voltage of the second transfer control gate 306 to improve the problem of gate induced leakage caused by the electric field, so that GIDL can be improved, white point of an image can be improved, and image quality can be improved.
Embodiment two:
as shown in fig. 20, the second embodiment provides another pixel structure and a corresponding manufacturing method, and the second embodiment is different from the first embodiment mainly in the position and the forming process of the control gate overlapping region, and the differences between the second embodiment and the first embodiment will be described in detail with reference to the accompanying drawings, and other related structures and manufacturing may be referred to the first embodiment and will not be described herein.
In the second embodiment, the pixel structure includes a semiconductor substrate 400, a photoelectric conversion region 410, a floating diffusion region 411, and a first transfer control gate 404 and a second transfer control gate 401; in this embodiment, the second transmission control gate 404 extends onto the first transmission control gate 401 to form the control gate overlap region 409.
As an example, the first transmission control gate 401 includes a first gate dielectric layer 403 and a first transmission gate 402 that are stacked from bottom to top, the second transmission control gate 404 includes a second gate dielectric layer 406 and a second transmission gate 405 that are stacked from bottom to top, the second transmission gate 405 extends beyond an outer edge of the second gate dielectric layer 406 near one side of the first transmission control gate 401 to form a control gate overlapping portion 408, and a spacer 407 is further formed between the first transmission gate 402 and the second transmission gate 405 (or the control gate overlapping portion 408) corresponding to the control gate overlapping portion 408, and the control gate overlapping portion 408 and the spacer 407 form the control gate overlapping region 409.
In addition, the device structure of this embodiment may be prepared as in the first embodiment, except that the first transmission control gate 409 is formed first, and then the control gate overlap region 409 is formed during the formation of the second transmission control gate 404.
The specific process can comprise the following steps: forming the first transfer control gate 401 on a first surface of the semiconductor substrate 400; the process of forming the first transmission gate 401 may refer to the process of forming the second transmission control gate 306 in the first embodiment, and in the forming process, the step of forming the first gate dielectric layer 403 based on a first oxidation process, where the temperature of the first oxidation process is greater than 600 ℃, and the specific process may refer to a process and a condition for forming the second gate dielectric layer in the first embodiment. Next, after the first transmission control gate 401 is formed, a second gate dielectric material layer (not shown in the figure) is formed on the exposed surface of the first transmission control gate 401 and the surrounding first surface; the second gate dielectric material layer (not shown) is formed based on a second oxidation process, the temperature of the second oxidation process is greater than 600 ℃, and the specific process can be referred to as a process and a condition for forming the first gate dielectric material layer in an embodiment. Next, a second transmission control gate electrode material layer (not shown) is formed on the second gate dielectric material layer; finally, etching the second transmission control gate electrode material layer to form the second transmission control gate electrode 405 and the control gate overlap 408; the second gate dielectric material layer is etched to form the second gate dielectric layer 406 and the spacer 407, thereby forming a second transmission control gate 404 and a control gate overlap region 409.
Embodiment III:
the third embodiment provides an image sensor, which includes the pixel structure according to any one of the aspects of the present invention, for example, it may include the pixel structure according to any one of the first embodiment or the second embodiment. The image sensor of the present invention may be a CMOS image sensor. In addition, the embodiment also provides electronic equipment, which comprises the image sensor according to any one of the schemes of the invention. The electronic equipment can be security camera equipment, automobile electronic camera equipment, mobile phone camera equipment, unmanned aerial vehicle, machine vision, existing cameras and other equipment.
In summary, the present invention provides a pixel structure, a manufacturing method, an image sensor, and an electronic device, in which two transmission control gates, namely a first transmission control gate and a second transmission control gate, are formed in the design of the pixel structure, so that the switching on/off of a device and the electric field between the transmission control gate and other parts (such as a floating diffusion region) can be flexibly regulated and controlled based on the voltage applied to the two transmission control gates, so as to meet the actual requirements of the device, and improve the flexibility of device control. When an electric field is formed between the transfer control gate electrode and the floating diffusion region, the electric field may be modulated based on the two transfer control gate electrodes. When a high potential difference is formed between the gate electrode (such as the first transfer control gate) of the charge transfer transistor and the drain electrode (floating diffusion active region) thereof, the high potential difference can be reduced through the second transfer control gate, thereby reducing gate induced leakage (GIDL), improving the problem of white dot and bad pixels of the CIS image, and improving the image quality of the CIS. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (15)
1. A pixel structure, the pixel structure comprising:
a semiconductor substrate having a first surface and a second surface opposite to each other;
a photoelectric conversion region extending from the first face into the semiconductor substrate for receiving an optical signal to generate an electrical signal;
a floating diffusion region extending from the first face into the semiconductor substrate and having a pitch from the photoelectric conversion region; the first transmission control gate and the second transmission control gate are arranged on the first surface and correspondingly and sequentially arranged between the photoelectric conversion region and the floating diffusion region, so that the electric signals of the photoelectric conversion region are transferred to the floating diffusion region based on the first transmission control gate and the second transmission control gate.
2. The pixel structure of claim 1, wherein the first transfer control gate is located on the first surface, the second transfer control gate is located on the first surface, and a control gate overlap region is further formed between the first transfer control gate and the second transfer control gate to form a channel communicating between the photoelectric conversion region and the floating diffusion region.
3. A pixel structure according to claim 2, wherein the width of the control gate overlap region is less than 0.2 μm.
4. The pixel structure of claim 2, wherein the second transfer control gate extends onto the first transfer control gate or the first transfer control gate extends onto the second transfer control gate to form the control gate overlap region.
5. The pixel structure of claim 4, wherein the first transmission control gate comprises a first gate dielectric layer and a first transmission control gate electrode stacked from bottom to top, the second transmission control gate comprises a second gate dielectric layer and a second transmission control gate electrode stacked from bottom to top, the first transmission control gate electrode extends beyond the outer edge of the first gate dielectric layer near the second transmission control gate or the second transmission control gate electrode extends beyond the outer edge of the second gate dielectric layer near the first transmission control gate to form a control gate overlap portion, and a spacer is further formed between the first transmission control gate electrode and the second transmission control gate electrode corresponding to the control gate overlap portion, and the control gate overlap portion and the spacer form the control gate overlap region.
6. The pixel structure of claim 5, wherein the thicknesses of the first gate dielectric layer and the second gate dielectric layer are the same or different; and/or the thickness of the first gate dielectric layer or the second gate dielectric layer corresponding to the side part of the spacer is the same; and/or the materials of the first gate dielectric layer, the second gate dielectric layer and the spacer are the same or different; and/or the spacing part is contacted with the side surface of the corresponding first gate dielectric layer or the side surface of the corresponding second gate dielectric layer; and/or the thickness of the first gate dielectric layer is smaller than 10nm, the thickness of the second gate dielectric layer is smaller than 10nm, and the thickness of the spacer is smaller than 10nm.
7. The pixel structure of claim 1, wherein the second transfer control gate has an overlap region with the floating diffusion region.
8. The pixel structure of claim 1, wherein a projected area of the first transfer control gate on the first side is greater than a projected area of the second transfer control gate on the first side.
9. The pixel structure according to any one of claims 1-8, wherein the first transfer control gate and the second transfer control gate have the same operation timing, and the off-state voltage of the second transfer control gate is greater than the off-state voltage of the first transfer control gate, and the on-state voltage is greater than or equal to the on-state voltage of the first transfer control gate.
10. An image sensor comprising a pixel structure according to any one of claims 1-9.
11. An electronic device comprising the image sensor of claim 10.
12. A method of manufacturing a pixel structure according to any one of claims 1 to 9, comprising the steps of:
providing the semiconductor substrate having the first and second opposite sides;
forming the first transmission control gate and the second transmission control gate on a first surface of the semiconductor substrate;
the photoelectric conversion region and the floating diffusion region are prepared in the semiconductor substrate from the first face.
13. The method of claim 12, wherein when the first transmission control gate includes the first gate dielectric layer and the first transmission control gate electrode, the second transmission control gate includes the second gate dielectric layer and the second transmission control gate electrode, and the control gate overlapping region formed by the control gate overlapping portion and the spacer is formed at the same time as the first gate dielectric layer or the second gate dielectric layer.
14. The method of manufacturing a pixel structure according to claim 13, wherein the forming of the first transfer control gate, the second transfer control gate, and the control gate overlap region comprises the steps of:
forming a second transmission control gate on the first surface of the semiconductor substrate;
forming a first gate dielectric material layer on the exposed surface of the second transmission control gate and the surrounding first surface;
forming a first transmission control gate electrode material layer on the first gate dielectric material layer;
etching the first transmission control gate electrode material layer to form the first transmission control gate electrode and the control gate overlapping part;
etching the first gate dielectric material layer to form the first gate dielectric layer and the spacer;
or,
forming the first transmission control gate on the first surface of the semiconductor substrate;
forming a second gate dielectric material layer on the exposed surface of the first transmission control gate and the surrounding first surface;
forming a second transmission control gate electrode material layer on the second gate dielectric material layer;
etching the second transmission control gate electrode material layer to form the second transmission control gate electrode and the control gate overlapping part;
And etching the second gate dielectric material layer to form the second gate dielectric layer and the spacer.
15. The method of claim 14, wherein forming the first transfer control gate comprises forming the first gate dielectric layer based on a first oxidation process at a temperature greater than 600 ℃, and forming the second gate dielectric material layer based on a second oxidation process at a temperature greater than 600 ℃; and/or forming the second transmission control gate comprises the step of forming the second gate dielectric layer based on a third oxidation process, wherein the temperature of the third oxidation process is higher than 600 ℃, and the step of forming the first gate dielectric material layer based on a fourth oxidation process, and the temperature of the fourth oxidation process is higher than 600 ℃.
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