CN217280784U

CN217280784U - Ultra-thin super junction IGBT device

Info

Publication number: CN217280784U
Application number: CN202122767542.XU
Authority: CN
Inventors: 吴玉舟; 禹久赢
Original assignee: Super Semiconductor Shanghai Co ltd
Current assignee: Super Semiconductor Shanghai Co ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-08-23
Anticipated expiration: 2031-11-12

Abstract

The utility model discloses an ultra-thin surpassing knot IGBT device, include: metallizing the collector; a P-type collector region on the metallized collector; the N-type FS layer is positioned above the P-type collector region; an N-type FS spacer located above the N-type FS layer; the first N-type epitaxial layer is positioned above the N-type FS isolation layer, and the second N-type epitaxial layer is positioned above the first N-type epitaxial layer; and the MOS structure is positioned in the second N-type epitaxial layer. According to the utility model discloses, attenuate chip thickness, reduce device forward conduction voltage drop and switching loss, reduce the device thermal resistance simultaneously, promote the conduction current ability.

Description

Ultra-thin super junction IGBT device

Technical Field

The utility model relates to a power semiconductor technical field, in particular to ultra-thin super junction IGBT device.

Background

An Insulated Gate Bipolar Transistor (IGBT) device has the advantages of high input resistance, high breakdown voltage, wide safe working area, easy driving and the like similar to a power MOS device, and has the advantages of low conduction voltage and the like of a Bipolar device, so that the IGBT device is widely applied to the fields of solar inverters, new energy vehicles, high-voltage direct-current transmission systems, high-speed railways and the like, and is a core device of high-power electronic systems in the current. The existing british fly-ash IGBT technology has been developed to the seventh generation, and technologies such as Micro Pattern Trench gate (MPT), Field Stop (FS), Carrier Storage (CS), Injection Enhancement (IE) and the like are adopted to obtain a good compromise between conduction voltage drop, switching loss and a safe working area. But limited by silicon limit, the thickness of the voltage-resistant layer is about 60 μm when the 650V class IGBT bears voltage, as shown in fig. 1, which makes it difficult to further thin the device to reduce on-resistance and switching loss and improve its current capability.

Super junction IGBT device is the hot device of academic world and industry research in recent years, and it is the novel power semiconductor device of PN post that increases the range repeatedly on the epitaxial layer on traditional IGBT device structure basis. The super junction structure formed by the PN column has similar effect on optimizing parameters such as device voltage resistance, forward conduction voltage drop and the like as a super junction MOS device. Due to the introduction of the PN columns, when the super-junction IGBT device is in forward voltage withstanding, besides the longitudinal electric field of the Pbody-N-Drift junction, mutual depletion of the PN columns generates a transverse electric field, triangular electric field distribution of the traditional IGBT device is modulated to be similar to rectangular distribution, and voltage withstanding capability of the super-junction IGBT device is greatly improved. On the premise of ensuring a certain breakdown voltage of the device, the concentration of the N-Drift layer can be obviously increased, so that the forward conduction voltage drop is obviously reduced, and the super-junction IGBT device is helped to obviously reduce conduction loss in application. Under the same current specification, the area of the super-junction IGBT device can be greatly reduced, and the chip cost is reduced. Currently, the deep trench etching and filling process is one of two manufacturing methods for manufacturing a super junction IGBT device. The deep groove etching and filling mode has simpler process flow, but has higher requirement on etching equipment. Due to the etching equipment, when the deep groove is etched, the groove is not a perfect rectangular structure, and the groove width gradually decreases along with the deepening of the reactive ion etching, so that a tapered structure with a wide upper part and a narrow lower part is formed. After the P-type silicon single crystal is filled, the narrow bottom of the P column and the N-Drift region are easy to form electric field concentration during voltage resistance, so that for a 650V conventional SJ-IGBT, as shown in FIG. 2, the length of the whole P column is generally not less than 45 μm to ensure the voltage resistance of the device, and the total thickness is not generally less than 60 μm by adding a front MOS structure and a back collector structure. These limit further reductions in turn-on voltage and switching losses of the IGBT device.

SUMMERY OF THE UTILITY MODEL

To the weak point that exists among the prior art, the utility model aims at providing an ultra-thin super junction IGBT device and preparation method, attenuate chip thickness reduces device forward conduction voltage drop and switching loss, reduces the device thermal resistance simultaneously, promotes the conduction current ability. In order to realize according to the utility model discloses an above-mentioned purpose and other advantages provide an ultra-thin super junction IGBT device, include:

metallizing the collector;

a P-type collector region on the metallized collector electrode;

the N-type FS layer is positioned above the P-type collector region;

an N-type FS spacer located above the N-type FS layer;

the first N-type epitaxial layer is positioned above the N-type FS isolation layer, and the second N-type epitaxial layer is positioned above the first N-type epitaxial layer; and the MOS structure is positioned in the second N-type epitaxial layer.

Preferably, the P-pillar is formed on two opposite sides of the first N-type epitaxial layer by a deep trench etching backfill process.

Preferably, the second N-type epitaxial layer includes a trench formed by reactive ion etching, a thermally grown gate oxide layer disposed in the trench, heavily doped polysilicon deposited in the gate oxide layer, and a P-type body region formed by a self-aligned process, and the P-column is not connected to the P-type body region.

Preferably, the device further comprises mutually independent N-type emitting regions which are positioned on two sides of the groove and positioned in the P-type body region, borophosphosilicate glass deposited above the second N-type epitaxial layer, and a metalized emitter positioned above the borophosphosilicate glass.

Preferably, the IGBT device further comprises a substrate, the substrate is of any N-type doping concentration or any P-type doping concentration, and the IGBT device can also be made of semiconductor materials of P-type channel super-junction IGBT, silicon carbide or gallium nitride.

Preferably, the first N-type epitaxial layer is formed by using a local melting monocrystalline silicon, excluding the substrate.

Preferably, the N-type FS isolation layer on the back of the IGBT device can be implanted or not implanted, and ions in the implantation process are phosphorus, arsenic, hydrogen or helium.

Preferably, the second N-type epitaxial layer is formed by epitaxy or is formed by etching and backfilling a deep groove on the first N-type epitaxial layer structure to form a P-column, and then the P-column part at the top in the first N-type epitaxial layer is compensated to be N-type by N-type high-energy implantation.

Preferably, the back surface of the IGBT device is ground to the bottom end of the P pillar, and then ground for several micrometers, and then the N-type FS layer and the P-type collector region are implanted.

Compared with the prior art, the utility model, its beneficial effect is: a first N-type epitaxial layer is epitaxially formed on a substrate silicon wafer, a super junction structure is formed through deep groove etching and backfilling processes, a surface MOS structure is formed through secondary epitaxy, and a floating P column is formed. And grinding the device to the bottom of the P column by thinning the back, and removing the narrow bottom of the P column by thinning by several micrometers so as to reduce the electric field concentration of the device at the position when the device is resistant to voltage. Injecting N-type impurities into the back surface to form an FS layer, injecting P-type impurities into the back surface to form a collector region, injecting hydrogen ions again to form an FS isolation layer, and compensating the P column to the N type. And sputtering metal on the back to complete the manufacture of the device. The floating P column ensures that the device works in a conductance modulation mode, and reduces the forward conduction voltage drop of the device. The N-type FS isolating layer formed by hydrogen ion implantation can reduce the switching loss when the switch is turned off. The thinning to remove the bottom area of the P column part can reduce electric field aggregation when the device is in voltage resistance, ensure enough breakdown voltage of the device, reduce the thickness of the N-Drift area, reduce forward conduction voltage drop of the device and reduce switching loss. The thinner chip thickness reduces the thermal resistance of the device and improves the current capability of the device. The utility model provides a pair of but 650V level ultra-thin surpasses knot IGBT chip thickness attenuate to 45 mu m, breakdown voltage is greater than 700V, and the forward conduction voltage drop ratio is conventional surpassed the knot IGBT of the same type and is reduced 0.1V at least, and switching loss and thermal resistance all reduce more than 10%, are showing the electric current ability that has promoted super knot IGBT device.

Drawings

FIG. 1 is a schematic structural diagram of a conventional Trench FS-IGBT device;

FIG. 2 is a schematic structural diagram of a conventional super junction IGBT device;

fig. 3 is a schematic structural diagram of an ultra-thin super junction IGBT device according to the present invention;

fig. 4 is a schematic structural diagram of an embodiment of the ultra-thin super junction IGBT device according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-4, an ultra-thin superjunction IGBT device includes: a metallized collector electrode 1;

a P-type collector region 2 located on the metallized collector 1;

the N-type FS layer 3 is positioned above the P-type collector region 2;

an N-type FS spacer 4 located above the N-type FS layer 3;

the first N-type epitaxial layer 5 positioned above the N-type FS isolation layer 4, the second N-type epitaxial layer 6 positioned above the first N-type epitaxial layer 5 and the MOS structure positioned in the second N-type epitaxial layer can reduce switching loss when the N-type FS isolation layer formed by hydrogen ion injection is turned off.

Furthermore, a P column 101 is formed on two opposite sides of the first N-type epitaxial layer 5 through a deep trench etching backfill process, and the P column ensures that the device works in a conductance modulation mode, so that the forward conduction voltage drop of the device is reduced.

Further, the second N-type epitaxial layer 6 includes a trench 7 formed by reactive ion etching, a thermally grown gate oxide layer 8 disposed in the trench 7, a heavily doped polysilicon 9 deposited in the gate oxide layer 8, and a P-type body region 10 formed by a self-aligned process, and the P-pillar 101 is not connected to the P-type body region 10.

Furthermore, the epitaxial wafer further comprises N-type emitting regions 11 which are positioned on two sides of the trench 7 and are arranged in the P-type body region 10 and are independent of each other, borophosphosilicate glass 12 deposited above the second N-type epitaxial layer 6, and a metalized emitting electrode 13 positioned above the borophosphosilicate glass 12.

Furthermore, the IGBT device further comprises a substrate, wherein the substrate is of any N-type doping concentration or any P-type doping concentration, and the IGBT device can also be made of semiconductor materials of P-type channel super-junction IGBT, silicon carbide or gallium nitride.

Further, the first N-type epitaxial layer 5 is formed by using a local melting single crystal silicon without including a substrate.

Furthermore, the N-type FS isolation layer 4 on the back of the IGBT device can be implanted or not implanted, ions during implantation are phosphorus, arsenic, hydrogen or helium, and the back of the IGBT device is the surface provided with the N-type FS isolation layer 4.

Further, the second N-type epitaxial layer 6 is formed by epitaxy or is formed by deep trench etching and backfilling on the first N-type epitaxial layer 5 structure to form a P-column 101, and then the P-column part at the top in the first N-type epitaxial layer 5 is compensated to be N-type by N-type high-energy implantation.

Furthermore, the back of the IGBT device is ground to the bottom end of the P column 101 and then ground for several micrometers, then the N-type FS layer 3 and the P-type collector region 2 are injected, after the back of the IGBT device is thinned, the P-type collector region 2 and the P column 101 can be isolated by injecting the N-type FS layer once, the thinning is carried out until the bottom region of the P column part is removed, electric field aggregation when the device is resistant to voltage can be reduced, the thickness of the N-Drift region is reduced while the sufficient breakdown voltage of the device is ensured, the forward conduction voltage drop of the device can be reduced, and the switching loss is reduced. The thinner chip thickness reduces the thermal resistance of the device and improves the current capability of the device.

The number of devices and the scale of the processes described herein are intended to simplify the description of the present invention, and applications, modifications and variations of the present invention will be apparent to those skilled in the art.

While the embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments, which are fully applicable in all kinds of fields of application suitable for this invention, and further modifications may be readily made by those skilled in the art, and the invention is therefore not limited to the specific details and illustrations shown and described herein, without departing from the general concept defined by the claims and their equivalents.

Claims

1. An ultra-thin super junction IGBT device, comprising:

a metallized collector electrode (1);

a P-type collector region (2) located on the metallized collector (1);

an N-type FS layer (3) positioned above the P-type collector region (2);

an N-type FS spacer (4) located above the N-type FS layer (3);

a first N-type epitaxial layer (5) positioned above the N-type FS isolation layer (4) and a second N-type epitaxial layer (6) positioned above the first N-type epitaxial layer (5); and the MOS structure is positioned in the second N-type epitaxial layer.

2. The ultra-thin super junction IGBT device according to claim 1, characterized in that P-pillars (101) are formed on two opposite sides of the first N-type epitaxial layer (5) by a deep trench etch backfill process.

3. The ultra-thin super junction IGBT device according to claim 2, characterized in that the second N-type epitaxial layer (6) comprises trenches (7) formed by reactive ion etching, a thermally grown gate oxide (8) disposed in the trenches (7), a heavily doped polysilicon (9) deposited in the gate oxide (8) and a P-type body region (10) formed by a self-aligned process, the P-pillars (101) being unconnected with the P-type body region (10).

4. The ultra-thin super-junction IGBT device according to claim 3, further comprising mutually independent N-type emitter regions (11) located on both sides of said trench (7) and located within the P-type body region (10), borophosphosilicate glass (12) deposited over said second N-type epitaxial layer (6), and a metalized emitter (13) located over said borophosphosilicate glass (12).

5. The ultra-thin super-junction IGBT device according to claim 4, further comprising a substrate with arbitrary doping concentration of N-type or arbitrary doping concentration of P-type, and the IGBT device is further applicable to semiconductor materials of P-type channel super-junction IGBT, silicon carbide or gallium nitride.

6. The ultra-thin superjunction IGBT device according to claim 1, wherein the first N-type epitaxial layer (5) is made by using a fused-area single crystal silicon, excluding a substrate.

7. The ultra-thin super junction IGBT device according to claim 6, characterized in that the N-type FS spacer (4) on the back side of the IGBT device may or may not be implanted, and the ions are phosphorus, arsenic, hydrogen or helium.

8. The ultra-thin super junction IGBT device according to claim 7, characterized in that the second N-type epitaxial layer (6) is formed by epitaxy or by forming P-pillars (101) on the first N-type epitaxial layer (5) structure by deep trench etching and backfilling, and then the top P-pillar portion in the first N-type epitaxial layer (5) is compensated to be N-type by N-type high energy implantation.

9. The ultra-thin super junction IGBT device according to claim 8, wherein the back side of the IGBT device is ground to the bottom end of the P pillar (101) and then ground for several microns, and then the N-type FS layer (3) and the P-type collector region (2) are implanted.