CN217239484U - Novel double-sided microcrystal heterojunction battery - Google Patents
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- CN217239484U CN217239484U CN202220959123.8U CN202220959123U CN217239484U CN 217239484 U CN217239484 U CN 217239484U CN 202220959123 U CN202220959123 U CN 202220959123U CN 217239484 U CN217239484 U CN 217239484U
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Abstract
The utility model relates to a novel two-sided micrite heterojunction battery belongs to solar cell and makes technical field. The optical performance of the heterojunction cell is enhanced by introducing microcrystalline silicon, doped microcrystalline silicon is deposited on the front surface and the back surface of an N-type monocrystalline silicon piece respectively, shallow doping is carried out on the front surface of the cell close to the N-type monocrystalline silicon piece and the intrinsic amorphous silicon layer region on the front surface, so that the passivation effect is better, heavy doping is adopted on the metal grid line region on the front surface, so that the contact resistance between the N-type monocrystalline silicon piece and the metal grid line layer on the front surface can be reduced by the heavy doping, and higher current can be obtained. The first microcrystalline silicon layer on the front surface is inserted between the intrinsic amorphous silicon layer on the front surface and the lightly doped N-type microcrystalline silicon layer, so that the conductivity is improved, and the passivation effect of the amorphous silicon is not influenced. The second microcrystalline silicon layer is inserted between the heavily-doped N-type microcrystalline silicon layer and the lightly-doped N-type microcrystalline silicon layer, so that the optical absorption is improved. And then depositing a front TCO film layer and a back TCO film layer to further improve the optical performance.
Description
Technical Field
The utility model relates to a solar cell makes technical field, especially relates to a novel two-sided micrite heterojunction battery.
Background
Heterojunction batteries are one of the highly efficient batteries with great prospects. The heterojunction battery has the advantages of simple preparation process flow, high conversion efficiency, large size, flaking, low attenuation, good double-sided performance and the like, and is researched and produced by a plurality of manufacturers.
The heterojunction cell is prepared by taking an N-type monocrystalline silicon wafer as a substrate 100, depositing intrinsic amorphous silicon 101 and N-type doped amorphous silicon 102 on the front surface respectively to form a front surface field after texturing and cleaning, depositing intrinsic amorphous silicon 103 and p-type doped amorphous silicon 104 on the back surface in sequence to form a PN junction, depositing TCO film layers 105 and 106 on the front surface and the back surface respectively, and then printing metal grid lines 107 and 108 on the front surface and the back surface respectively, as shown in FIG. 1.
The heterojunction battery has higher open-circuit voltage due to excellent passivation effect, but the optical utilization rate of the amorphous silicon is lower due to the narrow band gap of the amorphous silicon, so that the short-circuit current is lower, the optical performance of the heterojunction battery needs to be solved, and various problems also exist in grid line distribution, for example, more grid lines can reduce optical absorption, fewer grid lines can increase contact resistance, the conversion efficiency can be reduced, and the electrical performance of the heterojunction battery needs to be solved.
Disclosure of Invention
In order to solve the technical problem, the utility model provides a novel two-sided micrite heterojunction battery. The technical scheme of the utility model as follows:
a novel double-sided microcrystalline heterojunction cell comprises an N-type monocrystalline silicon wafer, wherein a front intrinsic amorphous silicon layer, a front first microcrystalline silicon layer, a lightly doped N-type microcrystalline silicon layer, a front second microcrystalline silicon layer, a heavily doped N-type microcrystalline silicon layer, a front TCO film layer and a front metal grid line layer are sequentially deposited on the front of the N-type monocrystalline silicon wafer, and a back intrinsic amorphous silicon layer, a back microcrystalline silicon layer, a P-type doped microcrystalline silicon layer, a back TCO film layer and a back metal grid line layer are sequentially deposited on the back of the N-type monocrystalline silicon wafer.
Optionally, the thickness of the front intrinsic amorphous silicon layer is 3-8 nm.
Optionally, the front-side first microcrystalline silicon layer has a thickness of 3-5 nm.
Optionally, the thickness of the lightly N-doped microcrystalline silicon layer is 3-5 nm.
Optionally, the front second microcrystalline silicon layer has a thickness of 2-3 nm.
Optionally, the heavily N-doped microcrystalline silicon layer has a thickness of 4-6 nm.
Optionally, the thickness of the back intrinsic amorphous silicon layer is 5-10 nm.
Optionally, the back side microcrystalline silicon layer has a thickness of 3-5 nm.
Optionally, the thickness of the P-type doped microcrystalline silicon layer is 5-9 nm.
Optionally, the thickness of each of the front and back TCO film layers is 50-150 nm.
All above-mentioned optional technical scheme all can make up wantonly, the utility model discloses do not carry out the detailed description to the structure after the one-by-one combination.
Borrow by above-mentioned scheme, the utility model discloses an introduce the optical property that the microcrystalline silicon strengthens the heterojunction battery, deposit respectively at the positive back of N type monocrystalline silicon piece and dope the microcrystalline silicon, and will dope the microcrystalline silicon and carry out the selectivity according to different functions respectively and dope, be close to N type monocrystalline silicon piece and the intrinsic amorphous silicon layer region in the battery front surface and carry out shallow doping, make the passivation effect more excellent, then adopt the heavy doping at positive metal grid line layer region, make the heavy doping can reduce the contact resistance between N type monocrystalline silicon piece and the positive metal grid line layer, obtain higher electric current. The first microcrystalline silicon layer on the front surface is inserted between the intrinsic amorphous silicon layer on the front surface and the lightly doped N-type microcrystalline silicon layer, so that the conductivity is improved, and the passivation effect of the amorphous silicon is not influenced. The front second microcrystalline silicon layer is inserted between the heavily N-doped microcrystalline silicon layer and the lightly N-doped microcrystalline silicon layer, so that the optical absorption is improved. And then depositing a front TCO film layer and a back TCO film layer to further improve the optical performance.
The above description is only an overview of the technical solution of the present invention, and in order to make the technical means of the present invention clearer and can be implemented according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present invention and accompanying drawings.
Drawings
Fig. 1 is a schematic structural view of a conventional heterojunction cell.
Fig. 2 is a schematic structural diagram of the novel double-sided microcrystalline heterojunction battery provided by the present invention.
Fig. 3 is a schematic diagram of another heterojunction cell.
Fig. 4 is a schematic diagram of yet another heterojunction cell.
Detailed Description
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.
As shown in fig. 2, the utility model provides a novel two-sided micrite heterojunction battery, it includes N type monocrystalline silicon piece 1, N type monocrystalline silicon piece 1 openly deposits in proper order has positive intrinsic amorphous silicon layer 2, positive first microcrystalline silicon layer 3, lightly mixes N type microcrystalline silicon layer 4, positive second microcrystalline silicon layer 5, heavily mixes N type microcrystalline silicon layer 6, positive TCO rete 7 and front metal grid line layer 8, N type monocrystalline silicon piece 1 back deposits in proper order has back intrinsic amorphous silicon layer 9, back microcrystalline silicon layer 10, P type to mix microcrystalline silicon layer 11, back TCO rete 12 and back metal grid line layer 13.
Optionally, the thickness of the front intrinsic amorphous silicon layer 2 is 3-8 nm.
Optionally, the front-side first microcrystalline silicon layer 3 has a thickness of 3-5 nm.
Optionally, the thickness of the shallow N-doped microcrystalline silicon layer 4 is 3-5 nm.
Optionally, the front second microcrystalline silicon layer 5 has a thickness of 2-3 nm.
Optionally, the heavily N-doped microcrystalline silicon layer 6 has a thickness of 4-6 nm.
Optionally, the thickness of the back intrinsic amorphous silicon layer 9 is 5-10 nm.
Optionally, the back side microcrystalline silicon layer 10 has a thickness of 3-5 nm.
Optionally, the thickness of the P-type doped microcrystalline silicon layer 11 is 5-9 nm.
Optionally, the thickness of both the front TCO film layer 7 and the back TCO film layer 12 is 50-150 nm.
The novel double-sided microcrystal heterojunction battery is prepared by the following main steps:
And 2, coating the silicon wafer subjected to texturing in the step 1, selecting a plate type PECVD (plasma enhanced chemical vapor deposition) device for deposition equipment, and depositing the front intrinsic amorphous silicon layer 2 on the silicon wafer subjected to texturing in the step 1 to obtain the deposition thickness of 3-8 nm.
And 3, depositing the first microcrystalline silicon layer 3 on the front surface of the silicon wafer obtained in the step 2, introducing hydrogen and silane, and increasing the dilution ratio of the hydrogen to obtain the first microcrystalline silicon layer 3 on the front surface, wherein the dilution ratio is about 100-150 times, and the deposition thickness is 3-5 nm.
And 4, depositing the shallow doped N-type microcrystalline silicon layer 4 on the silicon wafer obtained in the step 3, wherein shallow doping is carried out, the doping concentration is controlled to be 1.5-3%, and the deposition thickness is 3-5 nm.
And 5, depositing the undoped front second microcrystalline silicon layer 5 on the silicon wafer obtained in the step 4 again, wherein the dilution ratio of hydrogen and silane is about 100-150 times, and the deposition thickness is 2-3 nm.
And 6, depositing a heavily doped N-type microcrystalline silicon layer 6 on the silicon wafer obtained in the step 5, wherein the heavily doped N-type microcrystalline silicon layer is heavily doped, the doping concentration is about 5-7%, and the deposition thickness is 4-6 nm.
And 7, turning over the silicon wafer obtained in the step 6, and depositing a back intrinsic amorphous silicon layer 9 on the back, wherein the deposition thickness is 5-10 nm.
And 8, depositing the back microcrystalline silicon layer 10 on the silicon wafer obtained in the step 7, introducing hydrogen and silane, and increasing the dilution ratio of the hydrogen to obtain the back microcrystalline silicon layer 10, wherein the dilution ratio is about 100-150 times, and the deposition thickness is 3-5 nm.
And 9, depositing a P-type doping microcrystalline silicon layer 11 on the silicon wafer obtained in the step 8, wherein the doping concentration is controlled to be 3-7%, and the deposition thickness is 5-9 nm.
And step 10, performing double-sided TCO film deposition on the silicon wafer obtained in the step 9, respectively depositing a front TCO film layer 7 and a back front TCO film layer 12 on the front and the back, wherein PVD is adopted as equipment, and the deposition thickness is 50-150nm, preferably 110 nm.
And 11, performing double-sided metal grid line printing on the silicon wafer obtained in the step 10 to form a front metal grid line layer 8 and a back metal grid line layer 13, and thus obtaining a finished product battery piece.
To illustrate the beneficial effects of the novel double-sided microcrystalline heterojunction cell provided by the embodiments of the present invention, two types of heterojunction cells are listed below.
As shown in fig. 3, it is a schematic structural diagram of another heterojunction cell, the front structure of this heterojunction cell is the same as the front structure of the novel double-sided microcrystalline heterojunction cell provided by the present invention, and the back structure is the same as the back structure of the conventional heterojunction cell shown in fig. 1. The heterojunction cell comprises an N-type monocrystalline silicon wafer 300, front intrinsic amorphous silicon 301, a first microcrystalline silicon film 302, lightly doped N-type microcrystalline silicon 303, a second microcrystalline silicon film 304, heavily doped N-type microcrystalline silicon 305, a front TCO film 306 and a front metal gate 307 which are sequentially deposited on the front side of the N-type monocrystalline silicon wafer 300, and back intrinsic amorphous silicon 308, P-type doped amorphous silicon 309, a back TCO film 310 and a back metal gate 311 which are sequentially deposited on the back side of the N-type monocrystalline silicon wafer 300.
The preparation process of the heterojunction battery comprises the following steps:
step 31, performing texturing and cleaning on the N-type monocrystalline silicon wafer 300 to obtain a pyramid interface with two light trapping surfaces;
step 32, depositing the front intrinsic amorphous silicon 301 on the silicon wafer obtained in the step 31 by plate type PECVD deposition equipment, wherein the deposition thickness is 5 nm; depositing a first microcrystalline silicon film 302 on the front intrinsic amorphous silicon 301, wherein the dilution ratio of hydrogen and silane is 100 times, and the deposition thickness is 3 nm; then, the lightly doped N-type microcrystalline silicon 303 (doping concentration is 3 percent and deposition thickness is 4nm), the second microcrystalline silicon film 304 (deposition thickness is 2nm) and the heavily doped N-type microcrystalline silicon 305 (doping concentration is 7 percent and deposition thickness is 4nm) are sequentially deposited;
step 33, turning over the silicon wafer obtained in the step 32, and depositing a back intrinsic amorphous silicon film 308 on the back surface, wherein the deposition thickness is 8 nm; growing P-type doped amorphous silicon 309 on the back intrinsic amorphous silicon thin film 308, wherein the doping concentration is 2%, and the deposition thickness is 10 nm;
and step 34, performing double-sided TCO film deposition on the silicon wafer after the step 33 by using PVD equipment to obtain a front TCO film 306 and a back TCO film 310, and then printing metal grid lines to form a front metal grid 307 and a back metal grid 311 to obtain a finished product of the cell.
As shown in fig. 4, it is a schematic structural diagram of another heterojunction cell, the back structure of which is the same as the back structure of the novel double-sided microcrystalline heterojunction cell provided by the present invention, and the front structure of which is the same as the front structure of the conventional heterojunction cell shown in fig. 1. The heterojunction cell comprises an N-type monocrystalline silicon wafer 400, front intrinsic amorphous silicon 401, N-type doped amorphous silicon 402, a front TCO film 403 and a front metal grid 404 which are sequentially deposited on the front surface of the N-type monocrystalline silicon wafer 400, and back intrinsic amorphous silicon 405, a microcrystalline silicon film 406, a doped P-type microcrystalline silicon 407, a back TCO film 408 and a back metal grid 409 which are sequentially deposited on the back surface of the N-type monocrystalline silicon wafer 400.
The preparation process of the heterojunction battery comprises the following steps:
41, performing texturing and cleaning on the N-type monocrystalline silicon wafer 400 to obtain a pyramid interface with double-sided light trapping;
step 42, depositing the front intrinsic amorphous silicon 401 on the silicon wafer obtained in the step 41 by using a plate-type PECVD deposition device, wherein the deposition thickness is 7 nm; growing N-type doped amorphous silicon 402 on the front intrinsic amorphous silicon 401, wherein the doping concentration is 3%, and the deposition thickness is 6 nm;
step 43, turning over the silicon wafer obtained in the step 42, and depositing back intrinsic amorphous silicon 405 (deposition thickness 6nm), a microcrystalline silicon film 406 (deposition thickness 3nm) and doped P-type microcrystalline silicon 407 (doping concentration 5% and deposition thickness 9nm) on the back in sequence;
and 44, depositing double-sided TCO films on the silicon wafer obtained in the step 43 by using PVD equipment to obtain a front TCO film 404 and a back TCO film 408, and then printing metal grid lines to form a front metal grid 404 and a back metal grid 409 to obtain a finished product of the cell.
Will the utility model provides a novel two-sided micrite heterojunction battery (the heterojunction battery that fig. 2 corresponds) and the heterojunction battery that fig. 1, fig. 3 and fig. 4 correspond experiment, obtain as shown in the following table one experimental result:
| Grouping | Eff | Voc | Isc | FF |
| FIG. 1 shows a schematic view of a | 0.00 | 0.0000 | 0.000 | 0.00 |
| FIG. 3 | 0.07 | 0.0001 | 0.033 | 0.01 |
| FIG. 4 | 0.03 | 0.0004 | 0.008 | 0.08 |
| FIG. 2 | 0.15 | 0.0006 | 0.021 | 0.28 |
Battery parameters in table one: eff is the conversion efficiency (%) of the cell, Voc is the open-circuit voltage (V) of the cell, Isc is the short-circuit current (a), FF is the fill factor (%) of the cell, and in the experiment, the experimental results of the heterojunction cell corresponding to fig. 1 were taken as a reference. As can be seen from table one, the heterojunction cell corresponding to fig. 3 has an Eff increased by 0.07%, and mainly an Isc increased by 33mA, compared with the heterojunction cell corresponding to fig. 1, so that the optical utilization rate is mainly improved by adopting the heterojunction cell with the front structure of the present invention; figure 2 corresponds heterojunction battery compares in figure 1 corresponds heterojunction battery, and Eff improves 0.15%, mainly has improved 0.6mV for Voc, and Isc improves 21mA, and FF improves 0.28%, can obtain from this, the utility model provides a novel two-sided micrite heterojunction battery had both promoted the optical absorption effectively, has increased the illumination utilization ratio, has reduced the series resistance between basement and the metal grid line simultaneously, has improved the fill factor, has optimized passivation ability moreover, has promoted open circuit voltage, and then has improved the conversion efficiency of battery.
In order to solve the problem that heterojunction battery short-circuit current is low, the utility model discloses introduce the micrite silicon structure, because the micrite silicon has great optical band gap, compare in the adjustable window increase of traditional amorphous silicon, can improve optical absorption, increase electric conductivity. Furthermore, in order to obtain better electrical and optical properties, the utility model discloses carry out the selectivity doping mode in N type doped layer region, adopt shallow doping in approaching silicon chip area and amorphous silicon area with the help of the field passivation effect of N type doping microcrystalline silicon, increase surface field effect, reduce interface recombination rate more effectively, and then make the passivation performance more excellent; and carrying out heavy doping on the metal grid line contact region so as to reduce the contact resistance between the substrate and the metal grid line. In the P surface, boron can influence the Fermi level, and therefore, partition doping is not carried out, so that the short-circuit current of the battery can be improved, the filling factor of the battery can be improved, and the conversion efficiency is improved.
According to the novel double-sided microcrystalline heterojunction battery provided by the invention, the optical performance of the novel double-sided microcrystalline heterojunction battery is enhanced by introducing microcrystalline silicon, doped microcrystalline silicon is respectively deposited on the front surface and the back surface of an N-type monocrystalline silicon wafer 1, the doped microcrystalline silicon is respectively subjected to selective doping according to different functions, a selective doping scheme is applied to the front surface (N surface) of the battery, shallow doping is carried out in the regions close to the N-type monocrystalline silicon wafer 1 and a front intrinsic amorphous silicon layer 2, so that the passivation effect is better, heavy doping is adopted in a front metal grid line layer 8 region, so that the contact resistance between the N-type monocrystalline silicon wafer 1 and the front metal grid line layer 8 can be reduced due to the heavy doping, and higher current can be obtained. A layer of non-doped microcrystalline silicon (the first microcrystalline silicon layer 3 on the front side) is inserted between the intrinsic amorphous silicon layer 2 on the front side and the lightly doped N type microcrystalline silicon layer 4, so that the conductivity is improved, and the passivation effect of the amorphous silicon is not influenced. An undoped microcrystalline silicon layer (a front second microcrystalline silicon layer 5) is interposed between the heavily-doped N-type microcrystalline silicon layer 6 and the lightly-doped N-type microcrystalline silicon layer 4, improving optical absorption. And then TCO films (a front TCO film layer 7 and a back TCO film layer 12) are deposited on two sides, so that the optical performance is further improved. The utility model discloses promoted solar cell's conversion efficiency effectively, and can not increase the preparation cost, be one kind and solve the effective scheme that heterojunction battery short-circuit current is low.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A novel double-sided microcrystalline heterojunction cell is characterized by comprising an N-type monocrystalline silicon wafer (1), wherein a front intrinsic amorphous silicon layer (2), a front first microcrystalline silicon layer (3), a lightly doped N-type microcrystalline silicon layer (4), a front second microcrystalline silicon layer (5), a heavily doped N-type microcrystalline silicon layer (6), a front TCO film layer (7) and a front metal grid wire layer (8) are sequentially deposited on the front of the N-type monocrystalline silicon wafer (1), and a back intrinsic amorphous silicon layer (9), a back microcrystalline silicon layer (10), a P-type doped microcrystalline silicon layer (11), a back TCO film layer (12) and a back metal grid wire layer (13) are sequentially deposited on the back of the N-type monocrystalline silicon wafer (1).
2. A novel double sided microcrystalline heterojunction cell as claimed in claim 1, wherein said front intrinsic amorphous silicon layer (2) has a thickness of 3-8 nm.
3. A novel double-sided microcrystalline heterojunction cell according to claim 1, wherein said front-side first microcrystalline silicon layer (3) has a thickness of 3-5 nm.
4. The novel double-sided microcrystalline heterojunction cell according to claim 1, wherein the thickness of the shallow N-doped microcrystalline silicon layer (4) is 3-5 nm.
5. A novel double sided microcrystalline heterojunction cell as claimed in claim 1 wherein said front side second microcrystalline silicon layer (5) has a thickness of 2-3 nm.
6. The novel double-sided microcrystalline heterojunction cell according to claim 1, wherein the thickness of the heavily N-doped microcrystalline silicon layer (6) is 4-6 nm.
7. A novel double sided microcrystalline heterojunction cell as claimed in claim 1 wherein said back intrinsic amorphous silicon layer (9) has a thickness of 5-10 nm.
8. A novel double-sided microcrystalline heterojunction cell according to claim 1, wherein said back microcrystalline silicon layer (10) has a thickness of 3-5 nm.
9. A novel double-sided microcrystalline heterojunction cell according to claim 1, wherein said P-type doped microcrystalline silicon layer (11) has a thickness of 5-9 nm.
10. The novel double-sided microcrystalline heterojunction cell according to claim 1, wherein the thickness of both the front TCO film layer (7) and the back TCO film layer (12) is 50-150 nm.
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