CN217134372U

CN217134372U - Packaging structure of switching power supply

Info

Publication number: CN217134372U
Application number: CN202123308189.5U
Authority: CN
Inventors: 郑凌波; 张�杰; 林新春
Original assignee: Lii Semiconductor Co ltd
Current assignee: Lii Semiconductor Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-08-05
Anticipated expiration: 2031-12-27

Abstract

The utility model relates to a switching power supply's packaging structure belongs to semiconductor integrated circuit and makes the field, and it includes the lead frame, first chip, second chip and third chip through connecting conductor encapsulate in the lead frame, first chip sets up to semiconductor material gallium nitride (GaN) chip, and the second chip sets up to silicon-based metal oxide semiconductor field effect transistor, and the third chip sets up to switching power supply control chip, and first chip sets up with the second chip is established ties, and the second chip is folded and is sealed on first chip, and this application has the bad contact of first chip and second chip and reduces parasitic inductance scheduling problem, improves the life of whole chip.

Description

Packaging structure of switching power supply

Technical Field

The present disclosure relates to semiconductor integrated circuit manufacturing, and more particularly, to a package structure of a switching power supply control chip.

Background

The power supply is a necessary device of an electronic product, the power supply needs to provide stable working voltage for a load, the switching power supply control chip is widely applied, and the switching power supply control chip and a silicon-based metal oxide semiconductor field effect transistor (MOS tube) are designed in a sealing mode for simplifying an application circuit. However, when the switching power supply control chip needs to work in a high-power or high-frequency environment, the switching loss of the MOS transistor is large, thereby reducing the efficiency of the power supply. The problem needs to be solved, a semiconductor material gallium nitride (GaN) transistor can be introduced, the GaN transistor has the advantages of large forbidden bandwidth, high electron mobility, strong breakdown electric field and the like, can be applied to working environments of high temperature, high voltage, high frequency and the like, and has wide application prospects in the field of switching power supplies.

The semiconductor material gallium nitride transistor heterostructure has strong two-dimensional electron gas, belongs to a depletion mode device when gate voltage is not applied, and can be switched off only by applying negative pressure, which brings inconvenience to the design of a driving circuit. Silicon-based metal oxide semiconductor field effect transistors (MOS transistors) and semiconductor material gallium nitride transistors (GaN) are typically connected in series so that conventional MOS drivers can turn on the gallium nitride devices.

When the device is packaged, the switching power supply control chip, the MOS and the GaN are generally sealed together, but the series connection of the wires between the MOS and the GaN also increases the parasitic inductance of the device, so that the switching performance of the device is reduced. In addition, if the MOS and the GaN are arranged in parallel, the package area cannot be effectively reduced, and if the MOS and the GaN are stacked, the S end of the GaN is recessed in a plane, which makes the stacking and packaging difficult.

Disclosure of Invention

The application provides a structure of switching power supply's encapsulation, switching power supply control chip promptly, semiconductor field effect transistor (MOS pipe) and semiconductor material gallium nitride transistor (GaN)'s packaging structure can solve MOS pipe among the prior art and the problem of GaN overlapping seal design difficulty.

The application provides the following technical scheme:

a packaging structure of a switching power supply comprises a lead frame (400), wherein a first chip (100), a second chip (200) and a third chip (300) are packaged in the lead frame through connecting conductors, the first chip (100) is set to be a semiconductor material gallium nitride (GaN) transistor, a first grid (101), a first source electrode (102) and a first drain electrode (103) are arranged on the front surface of the first chip (100), and the first source electrode (102) is recessed in a plane; the second chip (200) is arranged as a silicon-based metal oxide semiconductor field effect transistor; the third chip (300) is set as a switching power supply control chip; the first chip (100) has a first source (102) area larger than an area of the second chip (200).

Optionally, the front surface of the second chip (200) is provided with a second gate (201) and a second source (202), and the back surface of the second chip is provided with a second drain (203).

Optionally, the front surface of the third chip (300) is at least provided with a power supply control pin VCC PAD (301), a chip ground pin VSS PAD (302), a sampling feedback pin VS PAD (303), a switch control pin gpad (304), and a detection pin CS PAD (305), and the back surface of the third chip (300) is provided for grounding of a chip substrate.

Optionally, the connection conductor is a wire, a conductive adhesive or a conductive film having an electrical connection property.

Optionally, the first chip (100) and the second chip (200) are arranged in series.

Optionally, the first gate (101) and the first source (102) of the first chip (100) are electrically connected to the second source (202) and the second drain (203) of the second chip (200) through connection conductors, the second gate (201) of the second chip (200) is electrically connected to the switch control PIN gpad (304) of the third chip (300) through connection conductors, and the power supply control PIN VCC PAD (301), the chip ground PIN VSS PAD (302), the sampling feedback PIN VS PAD (303), the first drain (103) of the first chip (100), and the second source (202) of the second chip (200) are electrically connected to the package frame PIN through connection conductors.

The increase the first grid area of first chip makes the area of second chip is less than the first grid area of first chip, adopts the form of directly folding the encapsulation this moment, and the second chip just in time is in the first grid of first chip sunken department, can not cause contact failure, forms good electrical contact, improves the life of whole chip, folds the design of sealing and can not only reduce the encapsulation area, still can reduce the wire that goes out with semiconductor material gallium nitride transistor grid and be connected to reduce parasitic inductance, optimized the interference of system.

The foregoing description is only an overview of the technical solutions of the present application, and in order to make the technical solutions of the present application more clear and clear, and to implement the technical solutions according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present application and the accompanying drawings.

Drawings

FIG. 1 is a top view of a gallium nitride (GaN) transistor, a semiconductor material of the present application;

FIG. 2 is a top view of a silicon-based metal oxide semiconductor field effect transistor (MOS transistor) according to the present application;

FIG. 3 is a top view of the switching power supply control chip of the present application

Fig. 4 is a top view of the wire bonding package of the present application including fig. 1, fig. 2, and fig. 3;

Detailed Description

The following detailed description of embodiments of the present application will be described in conjunction with the accompanying drawings and examples. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.

Referring to fig. 1 to 3, fig. 1 is a top view of a semiconductor material gallium nitride (GaN) transistor of a first chip 100, the semiconductor material gallium nitride transistor includes a first gate 101, a first source 102 and a first drain 103, the first gate 101, the first source 102 and the first drain 103 are located on a front surface of the semiconductor material gallium nitride transistor, wherein the first source 102 is recessed into a plane; fig. 2 is a top view of a second chip 200 of a silicon-based metal oxide semiconductor field effect transistor (MOS) device, where the silicon-based metal oxide semiconductor field effect transistor (MOS)200 includes a second gate 201, a second source 202, and a second drain 203 (not shown in the figure), the second gate 201 and the second source 202 are located on a front surface of the silicon-based metal oxide semiconductor field effect transistor (MOS), and the second drain 203 is located on a back surface of the silicon-based metal oxide semiconductor field effect transistor (MOS); fig. 3 is a top view of a switching power supply control chip of a third chip 300, where the switching power supply control chip 300 at least includes a power supply control pin VCC PAD 301, a chip ground VSS PAD302, a sampling feedback pin VS PAD303, a switching control pin gpad 304, and a detection pin CS PAD 305, the power supply control pin VCC PAD 301, the chip ground VSS PAD302, the sampling feedback pin VS PAD303, the detection pin CS PAD 305, and the switching control pin gpad 304 are all located on a front surface of the switching power supply control chip 300, and a back surface of the switching power supply control chip is a chip ground.

As an example, as shown in fig. 4, a lead frame 400 of SOP8 is adopted, in the lead frame 400 of SOP8, the first chip silicon-based metal oxide semiconductor field effect transistor 100, the second chip silicon-based metal oxide semiconductor field effect transistor 200 and the third chip switching power supply control chip 300 are sequentially placed, wherein the area of the second chip silicon-based metal oxide semiconductor field effect transistor 200 is smaller than the opening area of the first source 102 of the first chip semiconductor material gallium nitride transistor 100; the first chip semiconductor material gallium nitride transistor 100 and the second chip silicon-based metal oxide semiconductor field effect transistor 200 are stacked and sealed, that is, the second chip silicon-based metal oxide semiconductor field effect transistor 200 is just positioned in the recess of the first source 102 of the first chip semiconductor material gallium nitride transistor 100 to ensure good electrical connection, and the third chip switching power supply control chip 300 is flat-sealed with the first chip semiconductor material gallium nitride transistor 100 and the second chip silicon-based metal oxide semiconductor field effect transistor 200; the first chip semiconductor material gallium nitride transistor 100, the second chip silicon-based metal oxide semiconductor field effect transistor 200, and the third chip switching power supply control chip 300 are electrically connected through a connecting conductor, wherein the connecting conductor includes a wire, an optional copper wire, a gold wire, a palladium copper wire, a silver wire, a conductive adhesive, a conductive film, and the like, and may be any other possible electrical connection means, and the connecting conductor is not limited herein.

Specifically, in this embodiment, the first chip gan transistor 100 and the second chip soi mosfet 200 are arranged in series, the first gate 101 of the first chip gan transistor 100 is connected to the second source 202 of the second chip soi mosfet 200 through a wire 401, the switch control pin gpad 304 of the third chip switching power control chip 300 is connected to the second gate 201 of the second chip soi mosfet 200 through a wire 402, the second drain 203 of the second chip soi mosfet 200 is electrically connected to the first source 102 of the first chip gan transistor 100 through a conductive adhesive or a conductive film, and since the recess area of the first source S of the first chip gan transistor 100 is larger than that of the second source S of the first chip gan transistor 100 The area of the chip silicon-based mosfet 200 is such that the first source 101 of the first chip and the second drain 203 of the second chip can be electrically connected through a conductive adhesive film or a conductive adhesive, if the chip silicon-based mosfet 200 is connected through a conductive adhesive, it should be noted that the conductive adhesive can not overflow to other PADs and can not overflow to the edge of the first chip, which may cause a short circuit risk, the first gate 101 of the first chip semiconductor material gan transistor 100 and the detection PAD CS 305 of the third chip switch power control chip 300 are connected to the pin 415 of the lead frame 400 through wires, the first drain 103 of the first chip semiconductor material gan transistor 100 is connected to the

pins

411, 412, 413, 414 of the lead frame 400, the power control pin VCC PAD 301 of the third chip switch power control chip, the ground pin VSS PAD302, the ground pin PAD302 of the ground pin, The sampling feedback pin VS PAD303 is respectively connected with

pins

418, 417 and 416 of the lead frame 400, the

pins

411, 412, 413 and 414 of the lead frame 400 are connected, or an unconnected lead frame is selected, the substrate of the lead frame 400 is a silver-plated structure, the back surface of the first chip semiconductor material gallium nitride transistor 100 and the back surface of the third chip switching power supply control chip 300 are connected with the substrate of the lead frame 400 through conductive adhesive, so that the heat dissipation capability of the semiconductor material gallium nitride transistor 100 can be increased, and the pin positions can be freely adjusted according to practical application.

To sum up, because the surface of the first grid of the first chip semiconductor material gallium nitride transistor is recessed in a plane, and the area of the second chip is larger than that of the first grid of the first chip, the difficulty of sealing is greatly increased, the invention provides a packaging structure of a switching power supply, which specifically comprises a lead frame, the first chip semiconductor material gallium nitride transistor packaged in the lead frame, the second chip silicon-based metal oxide semiconductor field effect transistor, and a third chip switching power supply control chip, wherein the first grid area of the first chip is increased, the area of the second chip is smaller than that of the first grid of the first chip, at the moment, the first chip and the second chip are directly overlapped, the second chip is just in the recess of the first grid of the first chip, so that poor contact can not be caused, good electrical contact can be formed, and the service life of the whole chip can be prolonged, the third chip is in planar packaging with the first chip and the second chip, and the flat packaging and overlapping design can reduce the packaging area and the connection with a lead wire from a grid electrode of a semiconductor material gallium nitride transistor, thereby reducing parasitic inductance and optimizing the interference of a system.

The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. A packaging structure of a switching power supply is characterized in that: the chip packaging structure comprises a lead frame (400), wherein a first chip (100), a second chip (200) and a third chip (300) are packaged in the lead frame through connecting conductors;

the first chip (100) is provided with a semiconductor material gallium nitride (GaN) transistor, a first grid electrode (101), a first source electrode (102) and a first drain electrode (103) are arranged on the front surface of the first chip (100), and the first source electrode (102) is sunken in a plane;

the second chip (200) is arranged as a silicon-based metal oxide semiconductor field effect transistor;

the third chip (300) is set as a switching power supply control chip;

the first chip (100) has a first source (102) area larger than an area of the second chip (200).

2. The package structure of the switching power supply according to claim 1, wherein:

the front surface of the second chip (200) is provided with a second grid electrode (201) and a second source electrode (202), and the back surface of the second chip is provided with a second drain electrode (203).

3. The package structure of the switching power supply according to claim 2, wherein:

the front surface of the third chip (300) is at least provided with a power supply control pin VCC PAD (301), a chip ground pin VSSPAD (302), a sampling feedback pin VS PAD (303), a switch control pin GPAD (304) and a detection pin CS PAD (305), and the back surface of the third chip (300) is arranged for grounding of a chip substrate.

4. The package structure of the switching power supply according to claim 1, wherein: the connecting conductor is a wire, conductive adhesive or conductive film with electric connection performance.

5. The package structure of the switching power supply according to claim 1, wherein: the first chip (100) is arranged in series with the second chip (200).

6. The package structure of the switching power supply according to claim 3, wherein:

the first grid (101) and the first source (102) of the first chip (100) are respectively electrically connected with the second source (202) and the second drain (203) of the second chip (200) through connecting conductors, the second grid (201) of the second chip (200) is electrically connected with a switch control PIN GAPD (304) of a third chip (300) through connecting conductors, and a power supply control PIN VCC PAD (301), a chip ground PIN VSS (PAD) (302), a sampling feedback PIN VS PAD (303), the first drain (103) of the first chip (100) and the second source (202) of the second chip (200) are electrically connected with a package frame PIN through connecting conductors.