CN116230714A - Gallium nitride integrated power chip and manufacturing method thereof - Google Patents

Gallium nitride integrated power chip and manufacturing method thereof Download PDF

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Publication number
CN116230714A
CN116230714A CN202310232589.7A CN202310232589A CN116230714A CN 116230714 A CN116230714 A CN 116230714A CN 202310232589 A CN202310232589 A CN 202310232589A CN 116230714 A CN116230714 A CN 116230714A
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Prior art keywords
gallium nitride
transistor
metal sheet
integrated power
power chip
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CN202310232589.7A
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Chinese (zh)
Inventor
黎杰
庞振江
洪海敏
温雷
卜小松
葛俊雄
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China Gridcom Co Ltd
Shenzhen Zhixin Microelectronics Technology Co Ltd
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China Gridcom Co Ltd
Shenzhen Zhixin Microelectronics Technology Co Ltd
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Priority to CN202310232589.7A priority Critical patent/CN116230714A/en
Publication of CN116230714A publication Critical patent/CN116230714A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a gallium nitride integrated power chip and a manufacturing method thereof. The gallium nitride integrated power chip comprises a substrate, a cascade structure of a cascade source and a cascade gate, a metal sheet and a plastic package material, wherein the cascade structure of the cascade source and the cascade gate is arranged on the substrate. The cascode structure comprises a gallium nitride transistor and a silicon transistor, wherein the source electrode of the gallium nitride transistor is connected with the drain electrode of the silicon transistor, and the grid electrode of the gallium nitride transistor is connected with the source electrode of the silicon transistor. The metal sheet is connected with gallium nitride transistors and/or silicon transistors. The plastic package material encapsulates the cascade structure of the cascade, and the metal sheet is exposed out of the plastic package material for heat dissipation. According to the technical scheme, the metal sheet is connected with the gallium nitride transistor and/or the silicon transistor, and the metal sheet is exposed out of the plastic packaging material to dissipate heat, so that a heat transfer path is reduced, the heat dissipation capacity of the gallium nitride integrated power chip is greatly improved, and the reliability of the gallium nitride integrated power chip is enhanced.

Description

Gallium nitride integrated power chip and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a gallium nitride integrated power chip and a manufacturing method thereof.
Background
In the related art, the packaging form of the gallium nitride cascade structure (cascoded) mainly is bottom heat dissipation, the heat transfer path of the heat generated by the chip is long, the heat dissipation efficiency is low, and the current packaging cannot meet the rapid and efficient heat dissipation requirement under high heat flux density.
Disclosure of Invention
The embodiment of the invention provides a gallium nitride integrated power chip and a manufacturing method thereof.
The embodiment of the invention provides a gallium nitride integrated power chip, which comprises a substrate, a common-source common-gate cascade structure, a metal sheet and a plastic package material, wherein the common-source common-gate cascade structure is arranged on the substrate and comprises a gallium nitride transistor and a silicon transistor, a source electrode of the gallium nitride transistor is connected with a drain electrode of the silicon transistor, and a grid electrode of the gallium nitride transistor is connected with a source electrode of the silicon transistor. The metal sheet is connected with the gallium nitride transistor and/or the silicon transistor. The plastic package material encapsulates the cascade structure, and the metal sheet is exposed out of the plastic package material for heat dissipation.
In certain embodiments, the substrate is a copper-clad ceramic substrate, and the gallium nitride transistor and the silicon transistor are connected to the copper-clad ceramic substrate by conductive silver paste.
In some embodiments, the gallium nitride integrated power chip further comprises a frame, and the substrate is connected to the frame through conductive silver paste.
In some embodiments, the metal sheet comprises a first metal sheet connected to the drain of the gallium nitride transistor as a drain lead.
In some embodiments, the metal sheet comprises a second metal sheet that is connected to the source of the silicon transistor to act as a source lead.
In some embodiments, the second metal sheet is further used to connect the source of the silicon transistor and the gate of the gallium nitride transistor.
In some embodiments, the second metal sheet is exposed outside the molding compound for heat dissipation.
In some embodiments, the metal sheet comprises a third metal sheet connected to the gate of the silicon transistor as a gate lead.
In some embodiments, the metal sheet comprises a fourth metal sheet for connecting the drain of the silicon transistor and the source of the gallium nitride transistor.
The embodiment of the invention provides a manufacturing method of a gallium nitride integrated power chip, which comprises the following steps: forming a cascode structure on a substrate, wherein the cascode structure comprises a gallium nitride transistor and a silicon transistor, a source electrode of the gallium nitride transistor is connected with a drain electrode of the silicon transistor, and a grid electrode of the gallium nitride transistor is connected with a source electrode of the silicon transistor; connecting the gallium nitride transistor and/or the silicon transistor by adopting a metal sheet; and encapsulating the cascade structure by using a plastic package material, wherein the metal sheet is exposed out of the plastic package material for heat dissipation.
According to the gallium nitride integrated power chip and the manufacturing method thereof, the metal sheet is connected with the gallium nitride transistor and/or the silicon transistor, and the metal sheet is exposed out of the plastic packaging material to dissipate heat, so that the heat transfer path is reduced, the heat dissipation capacity of the gallium nitride integrated power chip is greatly improved, and the reliability of the gallium nitride integrated power chip is enhanced.
Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a gallium nitride integrated power chip according to some embodiments of the invention;
FIG. 2 is a schematic diagram of a gallium nitride integrated power chip according to some embodiments of the invention;
FIG. 3 is a schematic circuit diagram of a gallium nitride integrated power chip according to some embodiments of the invention;
FIG. 4 is a flow chart of a method of manufacturing according to certain embodiments of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the embodiments of the present invention and are not to be construed as limiting the embodiments of the present invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "thickness", "upper", "top", "bottom", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. And the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may be fixedly connected, detachably connected, or integrally connected in one example; may be mechanically or electrically connected, or may be in communication with each other; either directly or indirectly through intermediaries, may be in communication with each other between two elements or in an interaction relationship between the two elements.
Gallium nitride high electron mobility transistor (GaN HEMT) has the characteristics of high mobility, high breakdown field strength and wide band gap, and is mainly divided into: enhancement mode devices and depletion mode devices. The high-voltage depletion type GaN HEMT and the low-voltage enhancement type Si MOSFET are packaged together in a common-gate and common-source mode, so that a normally-off type Cascade type GaN HEMT is formed, a driving power supply can be compatible with the driving of the Si MOSFET device, the driving circuit design can be simplified, the cost is greatly saved, the design difficulty is reduced, and the application requirement of higher high voltage and high power is met. Common cathode type GaN HEMT devices mainly adopt TO (Transistor Outline ) packaging modes and the like, and basically adopt a bottom heat dissipation packaging scheme.
Specifically, a TO220 copper frame can be used as a packaging frame, a copper-clad ceramic substrate is firstly adhered TO a frame base island through conductive silver paste, then a Si MOSFET and a GaN HEMT are adhered TO the copper-clad ceramic substrate through conductive silver paste, finally, an electric connection between two chips and a G pole, an S pole and a D pole of a mixed tube are formed through a lead (copper wire or aluminum wire), and finally, the chips are encapsulated through plastic packaging materials.
TO220 packaging form is mainly single-sided bottom heat dissipation, and at present GaN chips are mostly of planar structures, so that heat generated by the dies can be dissipated only through paths such as a chip substrate, a ceramic substrate, a frame and the like, a heat transfer path is long, heat dissipation efficiency is low, and the current packaging cannot meet the requirements of rapid and efficient heat dissipation under high heat flux density.
Referring to fig. 1 to 3, an embodiment of the present invention provides a gan integrated power chip 100, where the gan integrated power chip 100 includes a substrate 10, a cascode structure 20 disposed on the substrate 10, a metal sheet 30, and a molding compound 40. The cascode structure 20 includes a gallium nitride transistor 22 and a silicon transistor 24, with the source of the gallium nitride transistor 22 being connected to the drain of the silicon transistor 24 and the gate of the gallium nitride transistor 22 being connected to the source of the silicon transistor 24. The metal sheet 30 is connected to the gallium nitride transistor 22 and/or the silicon transistor 24. The molding compound 40 encapsulates the cascode structure 20, and the metal sheet 30 is exposed outside the molding compound 40 for heat dissipation.
Referring to fig. 4, an embodiment of the present invention provides a manufacturing method of a gan integrated power chip 100, which can be used to manufacture the gan integrated power chip 100 according to any of the embodiments of the present invention. The manufacturing method comprises the following steps:
01: forming a cascode structure 20 on the substrate 10, the cascode structure 20 including a gallium nitride transistor 22 and a silicon transistor 24, a source of the gallium nitride transistor 22 being connected to a drain of the silicon transistor 24, a gate of the gallium nitride transistor 22 being connected to a source of the silicon transistor 24;
02: the gallium nitride transistor 22 and/or the silicon transistor 24 are connected by a metal sheet 30;
03: the plastic package material 40 is used for encapsulating the cascade structure 20, and the metal sheet 30 is exposed out of the plastic package material 40 for heat dissipation.
The gallium nitride integrated power chip 100 can be a GaN HEMT cascade power device, the gallium nitride integrated power chip 100 is suitable for a Cascade type high-voltage GaN HEMT device packaging design with breakdown voltage of 650V and above, is suitable for high-voltage high-power electronic devices, and can realize better heat dissipation.
In the gallium nitride integrated power chip 100 and the manufacturing method thereof, the metal sheet 30 is connected with the gallium nitride transistor 22 and/or the silicon transistor 24, and the metal sheet 30 is exposed out of the plastic package material 40 to dissipate heat, so that a heat transfer path is reduced, the heat dissipation capacity of the gallium nitride integrated power chip 100 is greatly improved, and the reliability of the gallium nitride integrated power chip 100 is enhanced. In addition, the cascode configuration 20 may achieve a higher and stable threshold voltage, gate operating voltage.
The molding compound 40 may include a heat dissipation area, the metal sheet 30 is exposed out of the molding compound 40 through the heat dissipation area, and the cascode structure 20 is located between the substrate 10 and the heat dissipation area, that is, the heat dissipation area may be located at the top of the gan integrated power chip 100, so as to implement a top heat dissipation package design.
The gallium nitride transistor 22 may be a GaN hemt chip, which is a high withstand voltage, depletion type GaN-based power chip of a lateral structure. The silicon transistor 24 may be a Si MOSFET chip. The Si MOSFET chip is a low-voltage, enhanced silicon-based power MOS chip of vertical structure. Referring to fig. 3, a schematic diagram of the cascode structure 20 may be shown, where the cascode structure 20 has a forward turn-on voltage enhancement mode of operation through cascading, in which the silicon transistor 24 controls the turn-on and turn-off of the entire device, and the gan transistor 22 acts to withstand high voltages when the device is turned off.
The metal sheet 30 may be a copper sheet, and the invention can utilize the copper sheet clip process to replace the bonding wire bonding process to realize the electrical connection of the gallium nitride transistor 22 and/or the silicon transistor 24, so that the gallium nitride integrated power chip 100 can realize top heat dissipation through the metal sheet 30, and the defects of the wire bonding process and bottom heat dissipation of the GaN HEMT cathode cascade structure in the related art are overcome.
Referring to fig. 1, in some embodiments, the substrate 10 is a copper-clad ceramic substrate 10, and the gallium nitride transistor 22 and the silicon transistor 24 are connected to the copper-clad ceramic substrate 10 by a conductive silver paste 50.
In certain embodiments, step 01 (forming a cascode structure 20 on the substrate 10) comprises:
012: gallium nitride transistor 22 and copper-clad ceramic substrate 10 are connected by conductive silver paste 50, and silicon transistor 24 and copper-clad ceramic substrate 10 are connected by conductive silver paste 50.
In this manner, gallium nitride transistor 22 and silicon transistor 24 may be secured and electrically connected by conductive silver paste 50.
Referring to fig. 1 and 2, in some embodiments, the gan integrated power chip 100 further includes a frame 60, and the substrate 10 is connected to the frame 60 through the conductive silver paste 50.
In certain embodiments, the method of manufacturing further comprises:
04: the substrate 10 and the frame 60 are connected by the conductive silver paste 50.
In this manner, the gallium nitride integrated power chip 100 may be packaged and protected by the frame 60. Specifically, the substrate 10 may be connected to the islands of the frame 60 through the conductive silver paste 50.
In some embodiments, the frame 60 may be an SOT (Small Outline Transistor, low profile transistor) frame 60, and heat in the gallium nitride integrated power chip 100 may be dissipated through the bottom of the cascode structure 20, the substrate 10, and the frame 60.
Referring to fig. 1 and 2, in some embodiments, the metal sheet 30 includes a first metal sheet 32, and the first metal sheet 32 is connected to the drain of the gan transistor 22 to serve as a drain lead.
In certain embodiments, step 02 (using metal sheet 30 to connect gallium nitride transistor 22 and/or silicon transistor 24) comprises:
021: the first metal sheet 32 is used to connect the drain of the gan transistor 22 as a drain lead.
In this manner, the drain of gallium nitride transistor 22 may be pulled out to serve as the drain lead for cascode structure 20.
In some embodiments, the first metal sheet 32 is exposed outside the molding compound 40 for heat dissipation. In this way, heat dissipation can be achieved by the first metal sheet 32.
Referring to fig. 1 and 2, in some embodiments, the metal sheet 30 includes a second metal sheet 34, and the second metal sheet 34 is connected to the source of the silicon transistor 24 to serve as a source lead.
In certain embodiments, step 02 (using metal sheet 30 to connect gallium nitride transistor 22 and/or silicon transistor 24) comprises:
023: the second metal plate 34 is used to connect the source of the silicon transistor 24 as a source lead.
In this manner, the source of silicon transistor 24 may be tapped as a source pin for cascode structure 20.
Referring to fig. 2, in some embodiments, the second metal plate 34 is also used to connect the source of the silicon transistor 24 and the gate of the gallium nitride transistor 22.
In certain embodiments, step 02 (using metal sheet 30 to connect gallium nitride transistor 22 and/or silicon transistor 24) comprises:
025: a second metal plate 34 is used to connect the source of silicon transistor 24 and the gate of gallium nitride transistor 22.
As such, the cascode structure 20 may be formed by connecting the source of the silicon transistor 24 and the gate of the gallium nitride transistor 22.
In some embodiments, the second metal sheet 34 is exposed outside the molding compound 40 for heat dissipation. In this way, heat dissipation can be achieved by the second metal sheet 34. Specifically, referring to fig. 1, the second metal sheet 34 exposes the molding compound 40 from the top, so as to realize top heat dissipation.
Referring to fig. 2, in some embodiments, the metal sheet 30 includes a third metal sheet 36, and the third metal sheet 36 is connected to the gate of the silicon transistor 24 to serve as a gate lead.
In certain embodiments, step 02 (using metal sheet 30 to connect gallium nitride transistor 22 and/or silicon transistor 24) comprises:
027: a third metal sheet 36 is used to connect the gate of the silicon transistor 24 as a gate lead.
In this manner, the gate of silicon transistor 24 may be tapped as a gate pin of cascode structure 20.
Referring to fig. 2, in some embodiments, the metal sheet 30 includes a fourth metal sheet 38, the fourth metal sheet 38 being used to connect the drain of the silicon transistor 24 and the source of the gallium nitride transistor 22.
In certain embodiments, step 02 (using metal sheet 30 to connect gallium nitride transistor 22 and/or silicon transistor 24) comprises:
029: a fourth metal plate 38 is used to connect the drain of silicon transistor 24 and the source of gallium nitride transistor 22.
As such, the cascode structure 20 may be formed by connecting the drain of the silicon transistor 24 and the source of the gallium nitride transistor 22.
In the description of the present specification, reference to the terms "certain embodiments," "in one example," "illustratively," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiments or examples is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. A gallium nitride integrated power chip, the gallium nitride integrated power chip comprising:
a substrate;
the structure comprises a substrate, a cascode cascade structure arranged on the substrate, wherein the cascode cascade structure comprises a gallium nitride transistor and a silicon transistor, a source electrode of the gallium nitride transistor is connected with a drain electrode of the silicon transistor, and a grid electrode of the gallium nitride transistor is connected with a source electrode of the silicon transistor;
a metal sheet connected to the gallium nitride transistor and/or the silicon transistor;
and the plastic packaging material encapsulates the cascade structure, and the metal sheet is exposed out of the plastic packaging material for heat dissipation.
2. The integrated power chip of claim 1, wherein the substrate is a copper-clad ceramic substrate, and the gallium nitride transistor and the silicon transistor are connected to the copper-clad ceramic substrate by conductive silver paste.
3. The gallium nitride integrated power chip of claim 1, further comprising:
and the substrate is connected with the frame through conductive silver paste.
4. The gallium nitride integrated power chip of claim 1, wherein the metal sheet comprises a first metal sheet connected to a drain of the gallium nitride transistor as a drain lead.
5. The gallium nitride integrated power chip of claim 1, wherein the metal sheet comprises a second metal sheet connected to a source of the silicon transistor as a source lead.
6. The gallium nitride integrated power chip of claim 5, wherein the second metal sheet is further used to connect a source of the silicon transistor and a gate of the gallium nitride transistor.
7. The integrated power chip of claim 5, wherein the second metal sheet is exposed outside the molding compound for heat dissipation.
8. The gallium nitride integrated power chip of claim 1, wherein the metal sheet comprises a third metal sheet connected to the gate of the silicon transistor as a gate pin.
9. The gallium nitride integrated power chip of claim 1, wherein the metal sheet comprises a fourth metal sheet for connecting a drain of the silicon transistor and a source of the gallium nitride transistor.
10. A method of manufacturing a gallium nitride integrated power chip, the method comprising:
forming a cascode structure on a substrate, wherein the cascode structure comprises a gallium nitride transistor and a silicon transistor, a source electrode of the gallium nitride transistor is connected with a drain electrode of the silicon transistor, and a grid electrode of the gallium nitride transistor is connected with a source electrode of the silicon transistor;
connecting the gallium nitride transistor and/or the silicon transistor by adopting a metal sheet;
and encapsulating the cascade structure by using a plastic package material, wherein the metal sheet is exposed out of the plastic package material for heat dissipation.
CN202310232589.7A 2023-02-28 2023-02-28 Gallium nitride integrated power chip and manufacturing method thereof Pending CN116230714A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116884932A (en) * 2023-09-06 2023-10-13 深圳智芯微电子科技有限公司 Chip packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116884932A (en) * 2023-09-06 2023-10-13 深圳智芯微电子科技有限公司 Chip packaging structure

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