CN116190370B - Cascade type GaN power device packaging structure - Google Patents

Cascade type GaN power device packaging structure Download PDF

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Publication number
CN116190370B
CN116190370B CN202310348421.2A CN202310348421A CN116190370B CN 116190370 B CN116190370 B CN 116190370B CN 202310348421 A CN202310348421 A CN 202310348421A CN 116190370 B CN116190370 B CN 116190370B
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chip
frame
lead
hemt
mosfet
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CN116190370A (en
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冯延晖
岳春晓
邱颖宁
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application discloses a cascading GaN power device packaging structure, wherein a cavity is formed in an AIN layer, an HEMT chip is positioned in the cavity of the AIN layer and is arranged on the upper surface of a frame base island, an MOSFET chip is positioned on the upper surface of an AlN layer, and the grid electrode of the HEMT chip and the drain electrode of the MOSFET chip form an area stack; the frame lead comprises a frame grid lead, a frame source lead and a frame drain lead, wherein the frame grid lead, the frame source lead and the frame drain lead are arranged in parallel and are vertically positioned on the same side of the frame base island; the drain of the HEMT chip is electrically interconnected with the frame drain lead, the source of the MOSFET chip is electrically interconnected with the frame source lead, and the gate of the MOSFET chip is electrically interconnected with the frame gate lead. The application reduces parasitic inductance of the cascade gallium nitride device and simultaneously maximally realizes high-efficiency heat dissipation.

Description

Cascade type GaN power device packaging structure
Technical Field
The application relates to a semiconductor technology, in particular to a packaging structure of a cascade GaN-based power device.
Background
As typical representation of wide forbidden band semiconductor materials, gaN materials have the characteristics of wide forbidden band, high electron mobility, high breakdown electric field, high thermal conductivity and the like, and have wide prospects in the application fields of photoelectrons, high-voltage high-power devices and high-frequency microwave devices.
GaN-based HEMTs can be divided into enhancement and depletion types. The preparation process of the enhanced high-voltage GaN-based HEMT is not mature, for example, the threshold voltage is small, the driving voltage required by complete conduction is very close to the gate breakdown voltage, the requirements on the packaging and driving circuits of the device are very high, and hidden danger exists in reliability. The depletion type GaN-based HEMT has the advantages of better stability, more mature preparation process, lower on-resistance, smaller parasitic junction capacitance, capability of realizing high voltage with breakdown voltage higher than 900V and the like. But the depletion type GaN-based HEMT is a normally-on device, which is unfavorable for the use of a switching power supply. To overcome this disadvantage, a low-voltage silicon (Si) -based MOSFET chip can be employed with a high-voltage GaN-based HEMT cascode configuration that is depleted.
Fig. 1 is a device schematic diagram of a typical cascaded gallium nitride power device package structure, in which a MOSFET chip controls the turn-on and turn-off of the entire device. Fig. 2 is a schematic diagram of a conventional package structure of the cascade GaN device shown in fig. 1, in which a TO-220 copper frame is used as a package frame base island, a MOSFET chip and a HEMT chip are adhered TO the left and right sides of the frame base island surface through insulating glue, and a gate G2 of the HEMT chip and a source S1 of the silicon-based MOSFET chip are electrically interconnected with a lead directly through copper wires, respectively. The drain D1 of the low voltage MOSFET chip of the vertical structure is at the bottom of the chip, so according to the circuit connection of fig. 1, the drain D1 of the silicon-based MOSFET chip cannot be directly bonded to the frame base island, and the drain D1 thereof needs to be led out in a certain way. The technology adopts a conductive silver paste process TO bond a silicon-based MOSFET chip on a small copper substrate, and then adopts insulating glue TO connect the small copper substrate with a TO-220 frame base island so as TO lead out a drain electrode D1 of the silicon-based MOSFET chip.
The above package structure has the following disadvantages: the silicon-based MOSFET chip adopts a two-dimensional plane placement mode, the source S1 is electrically connected with the frame base island through the lead wire, the lead wire distance is larger, the bonding lead wire is longer, the parasitic inductance is larger, the voltage signal oscillation is overlarge, even overshoot is easy to occur in the high-frequency switching process of the GaN-based HEMT chip, and the switching loss is larger.
In summary, the existing cascaded GaN device packaging structure introduces extra leads, which causes larger parasitic inductance, larger switching loss and device stacking heat accumulation caused by different structural layout. The prior art has limited solutions, and provides a novel packaging structure of a cascade GaN device, which adopts a combination of high heat conduction material and a cavity structure to strengthen heat dissipation, thereby realizing low-cost packaging.
Disclosure of Invention
The application aims to provide a high-efficiency heat dissipation packaging structure for a cascode gallium nitride device, which can reduce parasitic inductance of the cascode gallium nitride device and simultaneously realize high-efficiency heat dissipation to the greatest extent.
The technical solution for realizing the purpose of the application is as follows: the utility model provides a cascaded GaN power device packaging structure which characterized in that includes: plastic package shell, HEMT chip, MOSFET chip, alN layer, frame base island and frame pin, wherein:
the AlN layer is provided with a cavity, the HEMT chip is positioned in the cavity of the AlN layer and is arranged on the upper surface of the frame base island, the MOSFET chip is positioned on the upper surface of the AlN layer, and the source electrode of the HEMT chip and the drain electrode of the MOSFET chip form an area stack;
the frame lead comprises a frame grid lead, a frame source lead and a frame drain lead, wherein the frame grid lead, the frame source lead and the frame drain lead are arranged in parallel and are vertically positioned on the same side of the frame base island; the drain of the HEMT chip is electrically interconnected with the frame drain lead, the source of the MOSFET chip is electrically interconnected with the frame source lead, and the gate of the MOSFET chip is electrically interconnected with the frame gate lead.
Further, the HEMT chip is a high-voltage depletion type n-channel GaN-based HEMT chip with a horizontal structure, and the MOSFET chip is a low-voltage enhancement type n-channel silicon-based MOSFET chip with a vertical structure.
Further, let the width of the source of the HEMT chip be W, the distance between the edge of the source of the HEMT chip and the edge of the HEMT chip be L, the length of the MOSFET chip be L2, the length of the overlapping area of the HEMT chip and the MOSFET chip be L3, and the width be W3, then l3=l2, and the range of W3 is [ L, l+w ].
Further, the size of the AlN layer is determined by the size and the positional relationship of the HEMT chip and the MOSFET chip, and if the length of the HEMT chip is L1, the width of the HEMT chip is W2, the width of the overlapping area of the HEMT chip and the MOSFET chip is W3, the length of the AlN layer is L4, and the width of the AlN layer is W4, l4=l1, w4=w1+w2-W3.
Further, the AlN layer is positioned at the central position of the frame base island, and the thickness of the AlN layer is equal to that of the MOSFET chip; the cavity of the AlN layer is positioned at the center of the AlN layer, and the peripheral edges of the cavity are respectively parallel to the peripheral edges of the AlN layer.
Further, the cavity size of the AlN layer depends on the size of the HEMT chip, and it is required to ensure that the HEMT chip can be disposed in the cavity, and the cavity thickness is equal to the HEMT chip thickness.
Further, the drain electrode of the MOSFET chip is located at the source electrode position of the HEMT chip and is overlapped in area to achieve interconnection of the source electrode and the source electrode, the source electrode of the MOSFET chip is located at one side close to the frame pin and is electrically connected with the grid electrode of the HEMT chip and the frame source pin through the lead wire, the grid electrode of the MOSFET chip is located at one side far away from the frame pin and is electrically connected with the grid electrode pin of the frame through the lead wire.
Further, the gate, source and drain of the HEMT chip are all located on the side near the frame leads.
Further, the bottom of the HEMT chip is bonded with the frame base island through conductive silver paste, the cavity of the AlN layer is located at the center of the AlN layer, and the peripheral edges of the cavity are parallel to the peripheral edges of the AlN layer respectively.
Further, the source of the HEMT chip and the drain of the MOSFET chip are electrically interconnected by soldering.
Compared with the prior art, the application has the remarkable advantages that: 1) Compared with the packaging structure of a small copper plate, the structure reduces the number of additional leads introduced and reduces parasitic inductance. 2) Compared with a stacked packaging structure, the structure realizes effective heat dissipation of the chip and avoids heat accumulation effect. 3) The cavity size of the AlN layer in the structure can be flexibly set according to the size of the GaN HEMT chip.
Drawings
FIG. 1 is a device schematic diagram of a typical cascaded GaN device package structure;
fig. 2 is a perspective view of a conventional package structure (structure 1) of the cascade GaN device of fig. 1;
FIG. 3 is a structural layout of another prior art package structure (Structure 2);
fig. 4 is a device schematic diagram of a package structure (structure 3) of the cascaded GaN power device of the application;
fig. 5 is a layout of the package structure (structure 3) of the cascaded GaN power device of the application;
FIG. 6 is a view showing the structure of AlN layer with cavity of the structure 3 of the application;
fig. 7 is a three-dimensional perspective view of the package structure 3 of the present application;
fig. 8 is a top view of the package structure 3 of the present application;
in the figure: 1. a HEMT chip; 2. a MOSFET chip; 3. a frame base island; 4. a chip connection layer; 5. an AlN layer; 6. a lead wire; 7. a package housing; 8. a frame source lead; 9. a frame drain lead; 10. frame gate pins; 11. a small copper plate; 12. a source S2 of the HEMT chip; 13. a drain electrode D2 of the HEMT chip; 14. a gate G2 of the HEMT chip; 15. a source S1 of the MOSFET chip; 16. a gate G1 of the MOSFET chip; 17. copper blocks; 18. drain D1 of the MOSFET chip.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The application provides a novel cascading gallium nitride power device packaging structure, fig. 5 is a structural layout diagram of the efficient heat dissipation packaging structure of the cascading gallium nitride device, and referring to fig. 4 and 7, the packaging structure comprises a MOSFET chip 2, a HEMT chip 1, a frame base island 3, an AlN layer 5 and a plastic package (not shown in the figure), wherein the MOSFET chip 2, the HEMT chip 1, the frame base island 3 and the AlN layer 5 are packaged in the plastic package.
The AlN layer is just arranged on the upper surface of the frame base island 3, the frame base island 3 plays a supporting role on the whole cascaded GaN power device, and a complete packaging structure is formed with the plastic package shell.
The AlN layer 5 is provided with a cavity, the HEMT chip 1 is arranged in the cavity of the AlN layer, the MOSFET chip 2 is arranged on the upper surface of the AlN layer, and the HEMT chip 1 and the MOSFET chip 2 are in an area overlapping structure; the source electrode S2 of the HEMT chip and the drain electrode D1 of the MOSFET chip are electrically interconnected in a solder welding mode; the grid electrode of the HEMT chip is electrically interconnected with the source electrode of the MOSFET chip through a lead wire; the drain electrode of the HEMT chip is electrically interconnected with the frame base island through a lead;
on the basis of the area overlapping packaging structure, the AlN layer with the cavity accelerates the transverse heat dissipation of the device, simultaneously provides the function of supporting the device for the MOSFET chip, and improves the heat dissipation performance and the reliability of the chip. Compared with fig. 2, parasitic inductance is reduced, and switching characteristics are improved; meanwhile, a good heat dissipation effect is achieved.
The core part of the application is an AlN layer structure with a cavity. The thickness of the AlN layer can be adjusted according to the thickness of the HEMT chip; the size of the AlN layer can be adjusted according to the size and the position relation of the HEMT chip and the MOSFET chip; the cavity size of the AlN layer may be adjusted according to the size of the HEMT chip. And the introduction of extra leads is effectively reduced through a stacked structure by combining the characteristics of the cascaded GaN device.
Examples
To demonstrate the effectiveness of the present protocol, the following experimental design was performed.
In this embodiment, the structure corresponding parameters are: the HEMT chip has the width of 2mm, the length of 5mm and the thickness of 0.5055mm; the MOSFET chip is 1mm in width, 2mm in length and 0.5mm in thickness; the width of the cavity is 2.1mm, the length is 5.1mm, and the thickness is 0.7055mm; the AlN layer had a length of 6mm, a width of 4mm and a thickness of 0.7055mm. Under the same conditions, the building of a model of a typical cascade GaN device packaging structure layout (structure 1), a stacking cascade GaN device packaging structure layout (structure 2) and a cascade GaN device packaging structure layout (structure 3) is carried out.
Under the condition that the frequency is set to be 100MHz, three different package structure layouts are used for extracting parasitic parameters of leads at different positions, the extraction results are shown in table 1, and the extraction results can be shown as follows: the parasitic inductance Lint1 of the structure 1 is 0.85629nH, and Lint3 is 3.3334nH; the parasitic inductance Lint1 of the structure 2 is 0nH, and Lint3 is 0nH; the parasitic inductance Lint1 of the structure 3 (the application) is 0nH, and Lint3 is 0nH. From this it can be seen that: compared with the structure 1, the stacked cascade GaN device packaging structure layout (structure 2) and the stacked cascade GaN device packaging structure layout (structure 3) effectively reduce parasitic inductance.
Table 1 comparison of parasitic inductance results for three structures
The temperature distribution of the three structures under the same external conditions under the different power (8W, 12W and 16W) loss is carried out, and the highest temperature analysis results are shown in table 2, and can be seen from the results: in the case of dissipated power of 8W, 12W, 16W respectively, the maximum temperature of structure 1 is 82.5341 ℃, 88.8704 ℃ and 95.2088 ℃, respectively; the highest temperatures of structure 2 were 89.3563 ℃, 99.1738 ℃ and 108.934 ℃, respectively. From this it can be seen that: structure 2 may cause heat accumulation problems with increased power loss compared to structure 1. In the case of dissipated powers of 8W, 12W, 16W, respectively, the maximum temperatures of structure 3 (application) are 75.8691 ℃, 78.0027 ℃ and 81.7459 ℃, respectively; compared with the structure 2, the heat accumulation problem caused by the layout of the stacked structure is effectively relieved.
Table 2 comparison of the highest junction temperature results for the three structures
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1. The utility model provides a cascaded GaN power device packaging structure which characterized in that includes: plastic package shell, HEMT chip, MOSFET chip, alN layer, frame base island and frame pin, wherein:
the AlN layer is provided with a cavity, the HEMT chip is positioned in the cavity of the AlN layer and is arranged on the upper surface of the frame base island, the MOSFET chip is positioned on the upper surface of the AlN layer, and the source electrode of the HEMT chip and the drain electrode of the MOSFET chip form an area stack;
the frame lead comprises a frame grid lead, a frame source lead and a frame drain lead, wherein the frame grid lead, the frame source lead and the frame drain lead are arranged in parallel and are vertically positioned on the same side of the frame base island; the drain of the HEMT chip is electrically interconnected with the frame drain lead, the source of the MOSFET chip is electrically interconnected with the frame source lead, and the gate of the MOSFET chip is electrically interconnected with the frame gate lead.
2. The cascaded GaN power device package of claim 1, wherein the HEMT chip is a high voltage depletion mode n-channel GaN-based HEMT chip of horizontal structure and the MOSFET chip is a low voltage enhancement mode n-channel silicon-based MOSFET chip of vertical structure.
3. The package structure of claim 1, wherein, assuming that the width of the source of the HEMT chip is W, the distance between the edge of the source of the HEMT chip and the edge of the HEMT chip is L, the length of the MOSFET chip is L2, the length of the overlapping area of the HEMT chip and the MOSFET chip is L3, and the width is W3, the range of l3=l2, W3 is [ L, l+w ].
4. The package structure of claim 1, wherein the dimensions of the AlN layer are determined by the dimensions and positional relationship of the HEMT chip and the MOSFET chip, and let the HEMT chip be L1 long, the HEMT chip be W1 wide, the HEMT chip be W2 wide, the overlap area of the HEMT chip and the MOSFET chip be W3 wide, the length of the AlN layer be L4, and the width of the AlN layer be W4, l4=l1, w4=w1+w2-W3.
5. The cascaded GaN power device package structure of claim 1, wherein the AlN layer is located at the center of the frame base island and has a thickness equal to the thickness of the MOSFET chip; the cavity of the AlN layer is positioned at the center of the AlN layer, and the peripheral edges of the cavity are respectively parallel to the peripheral edges of the AlN layer.
6. The cascaded GaN power device packaging structure of claim 1, wherein the cavity size of the AlN layer depends on the size of the HEMT chip, the HEMT chip is required to be disposed in the cavity, and the cavity thickness is equal to the HEMT chip thickness.
7. The cascaded GaN power device package of claim 1, wherein the drain electrode of the MOSFET die is located at the source electrode of the HEMT die and has an overlapping area to achieve interconnection, the source electrode of the MOSFET die is located at a side close to the frame lead, and is electrically connected to the gate electrode of the HEMT die and the frame source lead through the lead, and the gate electrode of the MOSFET die is located at a side far from the frame lead, and is electrically connected to the frame gate lead through the lead.
8. The cascaded GaN power device package of claim 1, wherein the gate, source and drain of the HEMT chip are all located on a side near the frame leads.
9. The cascaded GaN power device packaging structure of claim 1, wherein the bottom of the HEMT chip and the frame base island are bonded by conductive silver paste, a space exists between the side wall of the AlN layer cavity structure and the side wall of the HEMT chip, and insulating materials are filled in the space.
10. The cascaded GaN power device package structure of claim 1, wherein the source of the HEMT chip and the drain of the MOSFET chip are electrically interconnected by soldering.
CN202310348421.2A 2023-04-04 2023-04-04 Cascade type GaN power device packaging structure Active CN116190370B (en)

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Publication number Priority date Publication date Assignee Title
CN116913911B (en) * 2023-09-05 2023-12-22 深圳智芯微电子科技有限公司 Cascade GaN HEMT packaging device and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1596473A (en) * 2001-11-27 2005-03-16 皇家飞利浦电子股份有限公司 Multi-chip module semiconductor devices
CN111164751A (en) * 2017-12-29 2020-05-15 英特尔公司 Microelectronic assembly
CN111430335A (en) * 2020-03-22 2020-07-17 华南理工大学 Laminated structure cascade GaN-based power device and packaging method thereof
CN114284231A (en) * 2021-12-27 2022-04-05 珠海镓未来科技有限公司 Packaging structure and packaging method of cascaded GaN-based power device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1596473A (en) * 2001-11-27 2005-03-16 皇家飞利浦电子股份有限公司 Multi-chip module semiconductor devices
CN111164751A (en) * 2017-12-29 2020-05-15 英特尔公司 Microelectronic assembly
CN111430335A (en) * 2020-03-22 2020-07-17 华南理工大学 Laminated structure cascade GaN-based power device and packaging method thereof
CN114284231A (en) * 2021-12-27 2022-04-05 珠海镓未来科技有限公司 Packaging structure and packaging method of cascaded GaN-based power device

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