CN217134362U - 一种具有防分层结构的塑封功率器件 - Google Patents

一种具有防分层结构的塑封功率器件 Download PDF

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CN217134362U
CN217134362U CN202220832817.5U CN202220832817U CN217134362U CN 217134362 U CN217134362 U CN 217134362U CN 202220832817 U CN202220832817 U CN 202220832817U CN 217134362 U CN217134362 U CN 217134362U
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power device
chip
plastic package
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王维
孙娅男
李新安
李树森
张超
肖彦
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HUBEI TECH SEMICONDUCTORS CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型的名称是一种具有防分层结构的塑封功率器件，属于塑封功率器件制造技术领域。它主要是解决现有塑封功率器件在封装及使用过程中容易产生塑封体与框架分层现象的问题。它的主要特征是：包括框架及与框架连接的框架引脚，设置在框架上的芯片，芯片与框架引脚电连接，以及将框架、芯片和部分框架引脚包封的塑封体；所述框架上设有导流槽。本实用新型具有可使框架与塑封体紧密结合而不会产生分层现象的特点，主要用于塑封功率器件的生产、设计和封装。

Description

一种具有防分层结构的塑封功率器件
技术领域
本实用新型属于塑封功率器件制造技术领域，具体涉及一种具有防分层结构的塑封功率器件。
背景技术
目前，塑封功率器件大都由框架、芯片、塑封体、铝丝、焊料构成，框架采用KFC材质制作，主要是考虑通大电流以及散热的需要，塑封体采用环氧树脂注塑成型；但环氧树脂与框架的热膨胀系数差别很大，导致器件在封装及使用过程中经过热胀冷缩过程后，塑封体与框架容易产生分层现象。随着功率半导体技术的迅速发展，功率器件的广泛应用对封装可靠性提出了更高的要求，因此就需要解决塑封器件的分层问题。
发明内容
本实用新型的目的就是针对上述不足之处而提供一种简单操作但又可靠实用的塑封功率器件封装。
本实用新型的技术解决方案是：一种具有防分层结构的塑封功率器件，包括框架及与框架连接的框架引脚，设置在框架上的芯片，芯片与框架引脚电连接，以及将框架、芯片和部分框架引脚包封的塑封体，其特征在于：所述框架上设有导流槽。
本实用新型的技术解决方案中所述的导流槽为上端面开放的凹槽。
本实用新型的技术解决方案中所述的导流槽为与框架引脚平行的纵向导流槽。
本实用新型的技术解决方案中所述的导流槽为与框架引脚垂直的横向导流槽。
本实用新型的技术解决方案中所述的导流槽为包括与框架引脚平行的纵向导流槽和与框架引脚垂直的横向导流槽。
本实用新型的技术解决方案中所述的纵向导流槽沿芯片的两侧设置。
本实用新型的技术解决方案中所述的横向导流槽沿芯片的两侧间隔设置。
本实用新型的技术解决方案中所述的纵向导流槽沿芯片的两侧设置；所述横向导流槽沿芯片的两侧间隔设置，并与纵向导流槽相通。
本实用新型的技术解决方案中所述的框架与芯片是用焊料通过焊接方式连接的；所述芯片与框架引脚是用铝丝通过Wire Bonding方式连接的。
本实用新型的技术解决方案中所述的凹槽横断面为矩形、燕尾槽形、梯形、弧形或上部矩形加下部弧形。
本实用新型的优点在于：框架上设有导流槽，在注塑过程中环氧树脂可以流入导流槽内并最终固化成型，使得框架与塑封体紧密结合，不会产生分层现象。
本实用新型主要用于塑封功率器件的生产、设计和封装。
附图说明
图1是本实用新型的构造主视图；
图2是本实用新型内部的构造左视图。
图中：1. 框架；2. 芯片；3.铝丝；4. 塑封体；5. 焊料；6. 框架引脚；7. 导流槽。
具体实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例进行完整地描述。显然，所描述的实施例仅仅是本实用新型的一部分实施例，而不是全部的实施例。任何基于本实用新型的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本实用新型保护的范围。
以下结合实例说明本实用新型的实施方式。
如图1、图2所示，本实用新型一种具有防分层结构的塑封功率器件的一个实施例，由框架1、框架引脚6、芯片2、铝丝3、塑封体4和焊料5构成。
框架1除导流槽7外，均与现有框架相同。框架引脚6与现有框架引脚相同，包括并排设置的三根引脚，与框架1的纵向一端固定连接。导流槽7包括与框架引脚6平行的纵向导流槽和与框架引脚6垂直的横向导流槽，纵向导流槽和横向导流槽均为上端面开放的凹槽。纵向导流槽沿芯片2的两侧设置，一端延伸至远离框架引脚6的框架1的横向端面，另一端延伸至近框架引脚6的框架1的横向端面。横向导流槽沿芯片2的两侧间隔设置，一端延伸至框架1的纵向端面，另一端与纵向导流槽相通。纵向导流槽和横向导流槽的凹槽横断面均为矩形，也可为燕尾槽形、梯形、弧形或上部矩形加下部弧形。
芯片2与框架1是通过焊接连接的。芯片2与框架引脚6中两侧的引脚是通过铝丝3电连接的。塑封体4将框架1、芯片2和部分框架引脚6包封。
本实用新型中的器件是先将框架1按照设计要求加工成型，芯片2焊接于框架1上，通过铝丝3将芯片2与框架引脚6进行内部连线，最后进行塑封，固化成型后完成封装。
框架1是通过机加工的方式加工成型。
框架1与芯片2是用焊料5通过焊接方式连接的，在框架1与芯片2的焊接过程中，需要有氮氢气体保护，防止芯片2或框架1氧化。
实施过程中如果芯片2或框架1部分有粘污，则塑封之前需要进行等离子清洗。
塑封体4采用环氧树脂材料，主要是用于保护芯片等重要部件不受外界环境侵蚀，以及实现各引脚之间的绝缘。
在注塑过程中环氧树脂可以流入导流槽内并最终固化成型，使得框架1与塑封体4紧密结合。
以上所述，仅是本实用新型的较佳实施例，并非对本实用新型作任何形式上的限制。因此凡是未脱离本实用新型的内容，依据本实用新型的技术实质对以上实施例所做的任何修改、等同替换、等效变化及修饰，均仍属于本实用新型技术方案保护的范围。

Claims (10)

1.一种具有防分层结构的塑封功率器件，包括框架（1）及与框架（1）连接的框架引脚（6），设置在框架（1）上的芯片（2），芯片（2）与框架引脚（6）电连接，以及将框架（1）、芯片（2）和部分框架引脚（6）包封的塑封体（4），其特征在于：所述框架（1）上设有导流槽（7）。
2.根据权利要求1所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的导流槽（7）为上端面开放的凹槽。
3.根据权利要求2所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的导流槽（7）为与框架引脚（6）平行的纵向导流槽。
4.根据权利要求2所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的导流槽（7）为与框架引脚（6）垂直的横向导流槽。
5.根据权利要求2所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的导流槽（7）为包括与框架引脚（6）平行的纵向导流槽和与框架引脚（6）垂直的横向导流槽。
6.根据权利要求3所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的纵向导流槽沿芯片（2）的两侧设置。
7.根据权利要求4所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的横向导流槽沿芯片（2）的两侧间隔设置。
8.根据权利要求5所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的纵向导流槽沿芯片（2）的两侧设置；所述横向导流槽沿芯片（2）的两侧间隔设置，并与纵向导流槽相通。
9.根据权利要求1-8中任一项所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的框架（1）与芯片（2）是用焊料（5）通过焊接方式连接的；所述芯片（2）与框架引脚（6）是用铝丝（3）通过Wire Bonding方式连接的。
10.根据权利要求2-8中任一项所述的一种具有防分层结构的塑封功率器件，其特征在于：所述的凹槽横断面为矩形、燕尾槽形、梯形、弧形或上部矩形加下部弧形。
CN202220832817.5U 2022-04-12 2022-04-12 一种具有防分层结构的塑封功率器件 Active CN217134362U (zh)

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