CN217112651U - Power strip card monitoring circuit - Google Patents
Power strip card monitoring circuit Download PDFInfo
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- CN217112651U CN217112651U CN202220305970.2U CN202220305970U CN217112651U CN 217112651 U CN217112651 U CN 217112651U CN 202220305970 U CN202220305970 U CN 202220305970U CN 217112651 U CN217112651 U CN 217112651U
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Abstract
The utility model discloses a power supply board card monitoring circuit, belonging to the technical field of power supply board card monitoring, which adopts CPLD as power supply management main control and designs an external circuit thereof, comprising a power supply power-on time sequence control circuit and a power supply output feedback normal circuit; the power-on time sequence control circuit of the power supply comprises an optocoupler device, an N-type triode, an N-type MOS (metal oxide semiconductor) tube and a divider resistor; the power output feedback normal circuit comprises a comparator and a divider resistor, and reference comparison voltage enters the negative end of the comparator after being divided by the resistor; the output voltage of the power supply module enters the positive end of the comparator after being subjected to voltage division by the resistor; the comparator outputs a high level when the voltage component of the output voltage of the power module is greater than the voltage component of the comparison voltage, and outputs a low level when the voltage component of the output voltage of the power module is less than the voltage component of the comparison voltage. The utility model discloses a CPLD is as power management's master control to adopt simple peripheral circuit just to realize power management.
Description
Technical Field
The utility model belongs to the technical field of the power integrated circuit board monitoring technology and specifically relates to a power integrated circuit board monitoring circuitry.
Background
With the continuous progress of technology, the number of functions, contents and devices included in all electronic systems is increasing, and the design of power supply systems is becoming more and more complex. In the current Power system Architecture, a Distributed Power Architecture (DPA) is widely used, but the DPA also has a disadvantage that strict Power management is required. Power management refers to how to efficiently distribute power to different components of a system, configure the power-on timing sequence of each system module, detect the output state of each power module, and the like.
Disclosure of Invention
The technical task of the utility model is to above weak point, provide a power strip card monitoring circuit, adopt CPLD as power management's master control to adopt simple peripheral circuit just to realize power management, simple structure can use in the field that possesses complicated electrical power generating system.
The utility model provides a technical scheme that its technical problem adopted is:
a power panel card monitoring circuit adopts a CPLD as power management master control, and an external circuit of the power panel card monitoring circuit is designed, wherein the external circuit comprises a power supply power-on time sequence control circuit and a power supply output feedback normal circuit;
the power supply power-on time sequence control circuit comprises an optocoupler device, an N-type triode, an N-type MOS (metal oxide semiconductor) tube and a divider resistor, wherein the optocoupler device is arranged at the CPLD control signal input end, the output end of the optocoupler device is connected with the N-type triode and is connected with the N-type MOS tube through the N-type triode, and the output of the MOS tube is the output voltage of the power supply module;
when the CPLD control signal is at a high level, the light emitting diode inside the optocoupler is conducted, so that the optocoupler is conducted, and further, the N-type triode is conducted. The conduction of the N-type triode causes the grid voltage of the N-type MOS tube to be pulled down to GND, the N-type MOS tube is cut off, and the output voltage of the power supply module is normally output; when the CPLD control signal is at a low level, the grid voltage of the N-type MOS tube is pulled up to a control voltage VCC, the N-type MOS tube is conducted, and the output voltage of the power supply module cannot be effectively output;
the power output feedback normal circuit comprises a comparator and a voltage division resistor, and reference comparison voltage enters the negative end of the comparator after being divided by the resistor; the output voltage of the power supply module enters the positive end of the comparator after being subjected to voltage division by the resistor; the comparator outputs a high level when the voltage component of the output voltage of the power module is greater than the voltage component of the comparison voltage, and outputs a low level when the voltage component of the output voltage of the power module is less than the voltage component of the comparison voltage.
As the density of system integration increases, higher demands are placed on the management of power supplies, where power-up timing and monitoring of power supplies are important. The power-up sequence of the power supply is very important and there is little chance of finding a problem in debugging. Therefore, the power supply of the system must be uniformly managed.
The Complex Programmable Logic Device (CPLD) is developed from PAL and GAL devices, and is relatively large in scale and complex in structure, belonging to the field of large scale integrated circuit. The digital integrated circuit is a digital integrated circuit which is used by a user to construct logic functions according to respective needs. Therefore, in an ultra-large-scale power supply system, the CPLD can play a role.
Preferably, the CPLD adopts an EPM1270T144I5N chip.
Further, the high and low levels output by the comparator are further input into the CPLD for the next logic operation.
Furthermore, a voltage dividing resistor R1 is arranged between the control voltage end and the N-type MOS tube, and a voltage dividing resistor R2 is arranged between the CPLD control signal input end and the optocoupler; and a divider resistor is arranged between the optocoupler and the N-type triode.
Preferably, the resistance values of R1 and R2 are both 1K omega;
a resistor R3 is connected between the emission set of the optocoupler device and the base set of the N-type triode, and R4 is connected between the emission set and the base set of the N-type triode; the resistance values of R3 and R4 are both 2K omega.
Preferably, the output voltage of the power supply module is divided by a resistor R15 and then enters the positive terminal of the comparator, and the resistance value of R15 is 1K Ω;
the output voltage of the power supply module is grounded after being divided by the resistor R16, and the resistance value of R16 is 4.7K omega.
Furthermore, the output end of the comparator is connected with a resistor R14, and the resistance value of R14 is 100 omega.
Preferably, when the power chip itself has a power Enable pin (Enable), a power normal pin (PowerGood) and a power Feedback pin (Feedback), the three pins are directly connected to the I/O of the CPLD, and then software programming configuration is performed.
The utility model discloses a power strip card monitoring circuitry compares with prior art, has following beneficial effect:
the monitoring circuit adopts the CPLD as the main control of power management, and realizes the power management by combining the CPLD with a simple peripheral circuit through the design of a power supply power-on time sequence control circuit and a power supply output feedback normal circuit.
The circuit is simple in structure and can be applied to the field with a complex power supply system.
Drawings
Fig. 1 is a circuit diagram of power-on timing control of a power supply according to an embodiment of the present invention;
fig. 2 is a normal circuit diagram of power output feedback provided by the embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the following specific examples.
The embodiment of the utility model provides a power strip card monitoring circuit, adopt CPLD as power management master control to design its external circuit, including power supply power-on sequence control circuit and power output feedback normal circuit;
the power supply power-on time sequence control circuit comprises an optocoupler device, an N-type triode, an N-type MOS (metal oxide semiconductor) tube and a divider resistor, wherein the optocoupler device is arranged at the CPLD control signal input end, the output end of the optocoupler device is connected with the N-type triode and is connected with the N-type MOS tube through the N-type triode, and the output of the MOS tube is the output voltage of the power supply module;
the power output feedback normal circuit comprises a comparator and a voltage division resistor, and reference comparison voltage enters the negative end of the comparator after being divided by the resistor; the output voltage of the power supply module enters the positive end of the comparator after being subjected to voltage division by the resistor; the comparator outputs a high level when the voltage component of the output voltage of the power module is greater than the voltage component of the comparison voltage, and outputs a low level when the voltage component of the output voltage of the power module is less than the voltage component of the comparison voltage. The high and low levels output by the comparator are further input into the CPLD for the next logic operation.
As the density of system integration increases, higher demands are made on the management of power supplies, of which power-up timing and monitoring are important. The power-up sequence of the power supply is very important and there is little chance of finding a problem in debugging. Therefore, the power supply of the system must be uniformly managed.
The Complex Programmable Logic Device (CPLD) is developed from PAL and GAL devices, and is relatively large in scale and complex in structure, belonging to the field of large scale integrated circuit. The digital integrated circuit is a digital integrated circuit which is used by a user to construct logic functions according to respective needs. Therefore, in an ultra-large-scale power supply system, the CPLD can play a role.
In this embodiment, the CPLD employs an EPM1270T144I5N chip.
As shown in fig. 1, the power-on timing control circuit provided in this embodiment:
j1 is an optical coupler, R1, R2, R3 and R4 are resistors, Q1 is an N-type MOS tube, and Q2 is an N-type triode.
Control is a CPLD Control signal, VCC is a Control voltage, and VOUT is an output voltage of the power module.
When the Control signal is at a high level, the light emitting diode in the J1 optocoupler is switched on, so that the optocoupler is switched on, and further, the Q2 is switched on. The Q2 is turned on, so that the grid voltage of the Q1 is pulled down to GND, the Q1 is turned off, and VOUT outputs normally; when the Control signal is low, the gate voltage of Q1 is pulled up to VCC, Q1 is turned on, and VOUT is not effectively output.
As shown in fig. 2, the power output feedback normal circuit provided for this embodiment,
u2 is a comparator, VREF is a reference comparison voltage, VOUT is a power module output voltage, and Signal2 is a feedback Signal after comparison between VREF and VOUT.
The reference voltage of VREF enters the negative end of the comparator after being divided by R12 and R13, VOUT enters the positive end of the comparator after being divided by R15 and R16, when the voltage component of VOUT is greater than the voltage component of VREF, the comparator outputs high level, when the voltage component of VOUT is less than the voltage component of VREF, the comparator outputs low level, and the output high level and the output low level can be further input into the CPLD to be subjected to the next logic operation.
The power chip is provided with a power Enable pin (Enable), a power normal pin (PowerGood) and a power Feedback pin (Feedback), and the three pins are directly connected to the I/O of the CPLD and then configured by software programming.
Through the above detailed description, the person skilled in the art can easily realize the present invention. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the basis of the disclosed embodiments, a person skilled in the art can combine different technical features at will, thereby implementing different technical solutions.
In addition to the technical features described in the specification, the technology is known to those skilled in the art.
Claims (8)
1. A power panel card monitoring circuit is characterized in that a CPLD is adopted as a power management master control, and an external circuit of the power panel card monitoring circuit is designed, wherein the external circuit comprises a power supply power-on time sequence control circuit and a power supply output feedback normal circuit;
the power supply power-on time sequence control circuit comprises an optocoupler device, an N-type triode, an N-type MOS (metal oxide semiconductor) tube and a divider resistor, wherein the optocoupler device is arranged at the CPLD control signal input end, the output end of the optocoupler device is connected with the N-type triode and is connected with the N-type MOS tube through the N-type triode, and the output of the MOS tube is the output voltage of the power supply module;
the power output feedback normal circuit comprises a comparator and a voltage division resistor, and reference comparison voltage enters the negative end of the comparator after being divided by the resistor; the output voltage of the power supply module enters the positive end of the comparator after being subjected to voltage division by the resistor; the comparator outputs a high level when the voltage component of the output voltage of the power module is greater than the voltage component of the comparison voltage, and outputs a low level when the voltage component of the output voltage of the power module is less than the voltage component of the comparison voltage.
2. The power board card monitoring circuit of claim 1, wherein the CPLD employs an EPM1270T144I5N chip.
3. The power board card monitoring circuit according to claim 1 or 2, wherein the high and low levels of the comparator output are further inputted to the CPLD.
4. The power panel card monitoring circuit according to claim 1 or 2, wherein a voltage dividing resistor R1 is arranged between the control voltage end and the N-type MOS transistor, and a voltage dividing resistor R2 is arranged between the CPLD control signal input end and the optocoupler; and a divider resistor is arranged between the optocoupler and the N-type triode.
5. The power strip card monitoring circuit of claim 4, wherein the resistances of R1 and R2 are both 1K Ω;
a resistor R3 is connected between the emission set of the optocoupler device and the base set of the N-type triode, and R4 is connected between the emission set and the base set of the N-type triode; the resistance values of R3 and R4 are both 2K omega.
6. The power strip card monitoring circuit according to claim 1 or 2, wherein the output voltage of the power module is divided by a resistor R15 and enters the positive terminal of the comparator, and the R15 resistance is 1K Ω;
the output voltage of the power supply module is grounded after being divided by the resistor R16, and the resistance value of R16 is 4.7K omega.
7. The power strip card monitoring circuit of claim 6, wherein the output of the comparator is connected to a resistor R14, and the resistance of R14 is 100 Ω.
8. The power board card monitoring circuit of claim 1, wherein the power chip itself has a power enable pin, a power normal pin, and a power feedback pin, which are directly connected to the I/O of the CPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220305970.2U CN217112651U (en) | 2022-02-15 | 2022-02-15 | Power strip card monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220305970.2U CN217112651U (en) | 2022-02-15 | 2022-02-15 | Power strip card monitoring circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217112651U true CN217112651U (en) | 2022-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220305970.2U Active CN217112651U (en) | 2022-02-15 | 2022-02-15 | Power strip card monitoring circuit |
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|---|---|
| CN (1) | CN217112651U (en) |
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- 2022-02-15 CN CN202220305970.2U patent/CN217112651U/en active Active
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Effective date of registration: 20230821 Address after: 250100 West District, North First Floor, S06 Building, 1036 Langchao Road, Jinan High-tech Zone, Shandong Province Patentee after: Shandong Inspur Ultra HD Video Industry Co.,Ltd. Address before: 11-12 / F, building 3, future venture Plaza, north section of Gangxing Third Road, high tech Zone, Jinan City, Shandong Province, 250100 Patentee before: Shandong new generation Information Industry Technology Research Institute Co.,Ltd. |