CN217088141U - Converter for realizing stereo asynchronous sampling based on FPGA - Google Patents
Converter for realizing stereo asynchronous sampling based on FPGA Download PDFInfo
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Abstract
The utility model aims at providing a compact structure, be convenient for remodel and adaptation wide range realize stereo asynchronous sampling converter based on FPGA. The utility model discloses a set up audio input port, audio output port, proportion estimator, interpolation filter, resampler and the extraction wave filter on the FPGA module, audio input port interpolation filter resampler extract the wave filter and audio output port connects gradually, audio input port interpolation filter resampler the resampler extract the wave filter and audio output port all with the communication of proportion estimator. The utility model discloses be applied to the technical field of sampling converter.
Description
Technical Field
The utility model discloses be applied to sampling converter's technical field, in particular to realize stereo asynchronous sampling converter based on FPGA.
Background
Asynchronous sampling converters are commonly used for the conversion of Audio signals of many different interfaces and frequencies, such as the CD music disc sampling rate 44.1kHz 16bit, while sony defined high-Resolution Audio, also known as high-Resolution Audio, has a sampling frequency up to 96kHz 24 bit. Audio data of different samples and different bit widths often need to be converted by an asynchronous sampler to be transmitted and processed in different devices. The currently common asynchronous sampling converter (ASRC) is usually realized by using an Application Specific Integrated Circuit (ASIC), the ASRC chip is required to be purchased independently, a corresponding peripheral circuit of the ASIC is required to be designed, the material cost development cost, the power consumption and the hardware debugging cost are increased, the whole area of a circuit is increased, and meanwhile, the ASIC can only convert signals in certain specific frequency ranges and port forms and can only be used in specific application scenes.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that overcome prior art not enough, provide a compact structure, be convenient for remodel and wide realization stereo asynchronous sampling converter based on FPGA of adaptation scope.
The utility model adopts the technical proposal that: the utility model discloses an audio input port, audio output port, proportion estimator, interpolation filter, resampler and the extraction filter of setting on the FPGA module, audio input port, interpolation filter, resampler, extraction filter and audio output port connect gradually, audio input port, interpolation filter, resampler, extraction filter and audio output port all with the communication of proportion estimator;
the audio input port is connected with external audio input equipment, receives audio data and outputs the audio data to the interpolation filter, and simultaneously sends an audio input clock signal to the proportion estimator;
the audio output port is connected with external audio output equipment, receives the audio data processed by the decimation filter, outputs the audio data to an external circuit and equipment in a configured interface mode, and simultaneously sends an audio output clock signal to the proportion estimator;
the ratio estimator receives a reference clock of an external controller, counts the periods of an audio input clock signal and an audio output clock signal according to the reference clock, processes the audio input clock signal and the audio output clock signal, outputs a frequency conversion coefficient to the interpolation filter, and sends a corresponding set sampling rate to the resampler and the decimation filter;
the interpolation filter carries out interpolation operation and low-pass filtering on the input audio data, and the processed audio data are output to the resampler;
the resampler synchronizes the audio data and outputs the audio data to the decimation filter;
and the decimation filter performs data decimation on the audio data and then transmits the decimated data to the audio output port for output.
According to the scheme, the audio input port, the audio output port, the proportion estimator, the interpolation filter, the resampler and the decimation filter are modules carried in an FPGA device, the proportion estimator is used for counting the periods of an audio input clock signal and an audio output clock signal by using a reference clock, calculating the frequency proportion relation of the input clock and the output clock, calculating the multiple frequency conversion coefficient according to a faster clock in the input and output clock, and calculating and transmitting the sampling rates of the interpolation filter and the decimation filter, so that the operations such as interpolation, decimation and filtering can be completed according to the corresponding sampling rates. The interpolation filter uses the frequency conversion coefficient output by the proportion estimator to perform interpolation operation on input data, performs low-pass filtering on the data, improves the digital sampling rate, and simultaneously uses the low-pass filter to filter the image frequency spectrum and reduce high-frequency noise. The decimation filter completes data decimation by using the sampling frequency given by the estimator, so that the decimation filter outputs data meeting the frequency requirement of an output port, and meanwhile, the frequency spectrum aliasing of the acquired signals is avoided, and high-frequency noise and the like are filtered.
Preferably, the audio input port and the audio output port are both connected with a set of audio interface modules, and the audio interface modules are I2S interface modules, PCM interface modules or PDM interface modules.
According to the scheme, the modular connection is adopted to connect different audio interface modules, so that the butt joint adaptation of different types of input signals is realized, and the compatibility of various audio interface forms is realized.
Preferably, the ratio estimator includes an input clock period counter, an output clock period counter and a counting divider, the input clock period counter, the output clock period counter and the counting divider all receive a reference clock, the input clock period counter is connected to the audio input port and receives an audio input clock signal, the output clock period counter is connected to the audio output port and receives an audio output clock signal, and the counting divider is connected to the output of the input clock period counter and the output of the output clock period counter.
According to the scheme, the period counting is carried out through the input clock period counter and the output clock period counter, then the counting result is provided to the counting divider, and the counting divider outputs the proportion calculation result according to the reference clock.
Drawings
Fig. 1 is a connection block diagram of the present invention;
FIG. 2 is a schematic diagram of the ratio estimator counting the input clock and the output clock;
fig. 3 is a connection block diagram of the scale estimator.
Detailed Description
As shown in fig. 1, in this embodiment, the present invention includes an audio input port 1, an audio output port 2, a ratio estimator 3, an interpolation filter 4, a resampler 5 and an extraction filter 6, which are disposed on the FPGA module, wherein the audio input port 1, the interpolation filter 4, the resampler 5, the extraction filter 6 and the audio output port 2 are connected in sequence, and the audio input port 1, the interpolation filter 4, the resampler 5, the extraction filter 6 and the audio output port 2 are all in communication with the ratio estimator 3;
the audio input port 1 is connected with an external audio input device, receives audio data and outputs the audio data to the interpolation filter 4, and simultaneously sends an audio input clock signal to the proportion estimator 3;
the audio output port 2 is connected with external audio output equipment, receives the audio data processed by the decimation filter 6, outputs the audio data to an external circuit and equipment in a configured interface mode, and simultaneously sends an audio output clock signal to the proportion estimator 3;
the ratio estimator 3 receives a reference clock of an external controller, counts the periods of an audio input clock signal and an audio output clock signal according to the reference clock, processes the audio input clock signal and the audio output clock signal, outputs a frequency conversion coefficient to the interpolation filter 4, and sends a corresponding set sampling rate to the resampler 5 and the decimation filter 6;
the interpolation filter 4 performs interpolation operation and low-pass filtering on the input audio data, and outputs the processed audio data to the resampler 5;
the resampler 5 synchronizes the audio data and outputs the audio data to the decimation filter 6;
the decimation filter 6 performs data decimation on the audio data and then transmits the decimated data to the audio output port 2 for output.
In this embodiment, the FPGA module is a Xilinx FPGA device, and the interpolation filter 4 is a CIC Compiler module in the Xilinx FPGA device, so as to implement a single-channel CIC interpolation and filter function of 3 th order, 4 th order, or 5 th order; the resampler 5 is an FIFO Generator module in an Xilinx FPGA device, realizes 1024 depths and 24bit or 32bit widths, is asynchronous FIFO, writes data through an input clock, outputs the clock to read the data, and completes asynchronous resampling; the decimation filter 6 is a CIC Compiler module in the Xilinx FPGA device, and realizes the functions of single-channel CIC decimation and filters of 3-order, 4-order or 5-order.
The audio input port 1 and the audio output port 2 are both connected with a group of audio interface modules, and the audio interface modules are I2S interface modules, PCM interface modules or PDM interface modules.
As shown in fig. 3, the ratio estimator 3 includes an input clock period counter 3a, an output clock period counter 3b, and a count divider 3c, where the input clock period counter 3a, the output clock period counter 3b, and the count divider 3c all receive a reference clock, the input clock period counter 3a is connected to the audio input port 1 and receives an audio input clock signal, the output clock period counter 3b is connected to the audio output port 2 and receives an audio output clock signal, and the count divider 3c is connected to an output end of the input clock period counter 3a and an output end of the output clock period counter 3 b.
The utility model discloses a theory of operation:
as shown in fig. 2, the audio input port 1 is connected to an external audio input device through an audio interface module, and the audio interface module is replaced according to the external audio input device. The audio input port 1 transmits the collected audio input data to the interpolation filter 4 in a specific form for post-processing, and simultaneously transmits a clock signal of the input data to the scale estimator 3.
The audio output port 2 is connected with external audio output equipment through an audio interface module, and the audio interface module is replaced according to the external audio input equipment. The audio output port 2 outputs the audio data processed by the decimation filter 6 to an external circuit and equipment in a set interface form. At the same time, the audio output port 2 transmits a clock signal of the output data to the scale estimator 3.
The ratio estimator 3 counts cycles of the audio input clock signal and the audio output clock signal using a reference clock, calculates a proportional relationship between the input clock frequency and the output clock frequency, performs frequency conversion by n times of a faster clock of the input clock frequency and the output clock frequency, where a frequency conversion coefficient is, for example, 2, 3, 4, 8, 16, and calculates a sampling rate required by the interpolation filter 4 and the decimation filter 6, and transmits the sampling rate to the interpolation filter 4 and the decimation filter 6, so that the interpolation, decimation, filtering, and other operations can be completed at the corresponding sampling rate. And the resampler 5 calculates the proportional relation according to the proportional estimator 3 to complete the data resampling operation.
The interpolation filter 4 performs interpolation operation on the input audio data by using the frequency conversion coefficient output by the proportion estimator 3, performs low-pass filtering on the audio data, improves the digital sampling rate, and simultaneously filters the image spectrum by using the low-pass filter and reduces high-frequency noise. The resampler 5 synchronizes the audio data at a sampling rate given by the scale estimator 3 and outputs the data to the decimation filter 6.
The decimation filter 6 completes data decimation by using the sampling frequency given by the proportion estimator 3, so that the decimation filter 6 outputs data meeting the frequency requirement of an output port, and meanwhile, the frequency spectrum aliasing of the acquired signals is avoided, and high-frequency noise and the like are filtered.
Claims (3)
1. Realize stereo asynchronous sampling converter based on FPGA, its characterized in that: the FPGA-based voice frequency detection device comprises an audio frequency input port (1), an audio frequency output port (2), a proportion estimator (3), an interpolation filter (4), a resampler (5) and a decimation filter (6) which are arranged on an FPGA module, wherein the audio frequency input port (1), the interpolation filter (4), the resampler (5), the decimation filter (6) and the audio frequency output port (2) are sequentially connected, and the audio frequency input port (1), the interpolation filter (4), the resampler (5), the decimation filter (6) and the audio frequency output port (2) are all communicated with the proportion estimator (3);
the audio input port (1) is connected with external audio input equipment, receives audio data and outputs the audio data to the interpolation filter (4), and simultaneously sends an audio input clock signal to the proportion estimator (3);
the audio output port (2) is connected with external audio output equipment, receives the audio data processed by the decimation filter (6), outputs the audio data to external circuits and equipment in a configured interface mode, and simultaneously sends an audio output clock signal to the proportion estimator (3);
the ratio estimator (3) receives a reference clock of an external controller, counts the periods of an audio input clock signal and an audio output clock signal according to the reference clock, processes the audio input clock signal and the audio output clock signal, outputs a frequency conversion coefficient to the interpolation filter (4) by the ratio estimator (3), and sends a corresponding set sampling rate to the resampler (5) and the decimation filter (6) by the ratio estimator (3);
the interpolation filter (4) carries out interpolation operation and low-pass filtering on the input audio data, and outputs the processed audio data to the resampler (5);
the resampler (5) synchronizes the audio data and outputs the audio data to the decimation filter (6);
and the decimation filter (6) performs data decimation on the audio data and then transmits the decimated data to the audio output port (2) for output.
2. The FPGA-based stereo asynchronous sampling converter of claim 1, wherein: the audio input port (1) and the audio output port (2) are both connected with a group of audio interface modules, and the audio interface modules are I2S interface modules, PCM interface modules or PDM interface modules.
3. The FPGA-based stereo asynchronous sampling converter of claim 1, wherein: the ratio estimator (3) comprises an input clock cycle counter (3 a), an output clock cycle counter (3 b) and a counting divider (3 c), the input clock cycle counter (3 a), the output clock cycle counter (3 b) and the counting divider (3 c) all receive a reference clock, the input clock cycle counter (3 a) is connected with the audio input port (1) and receives an audio input clock signal, the output clock cycle counter (3 b) is connected with the audio output port (2) and receives an audio output clock signal, and the counting divider (3 c) is connected with the output end of the input clock cycle counter (3 a) and the output end of the output clock cycle counter (3 b).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115223578A (en) * | 2022-09-21 | 2022-10-21 | 浙江地芯引力科技有限公司 | Audio signal synchronization method, device, equipment and storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115223578A (en) * | 2022-09-21 | 2022-10-21 | 浙江地芯引力科技有限公司 | Audio signal synchronization method, device, equipment and storage medium |
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