CN102192765A

CN102192765A - Multi-channel parallel isolation analog/digital (A/D) acquisition and processing method

Info

Publication number: CN102192765A
Application number: CN 201010121167
Authority: CN
Inventors: 程蜀炜; 韩彬; 寇志强
Original assignee: Lianyungang Jierui Electronics Co Ltd
Current assignee: Lianyungang Jierui Electronics Co Ltd
Priority date: 2010-03-10
Filing date: 2010-03-10
Publication date: 2011-09-21
Anticipated expiration: 2030-03-10
Also published as: CN102192765B

Abstract

The invention relates to a multi-channel parallel isolation analog/digital (A/D) acquisition and processing method and is characterized in that: a circuit in the method consists of an input isolation circuit, a signal conditioning circuit, a digital isolator and a field programmable gate array (FPGA); parallel input, isolation and acquisition is performed on analog voltage signals output from multi-channel sensors in different types; and the analog voltage signal input by each channel is transmitted to the FPGA through the input isolation circuit, the signal conditioning circuit and the digital isolator successively. In the method, two-end isolation of a conversion circuit is adopted, so the reliability is high; moreover, the influence of a destructive noise source can be avoided effectively. By the method, parallel and synchronous acquisition can be realized, and the instantaneity is strong; furthermore, multi-channel synchronous acquisition can be realized, and the method is applicable to situations in which the frequencies of tested physical values are different; and the application scope is wider.

Description

A kind of multi-channel parallel is isolated the A/D acquiring and processing method

Technical field

The present invention belongs to technical field of sensor measurement, and particularly a kind of multi-channel parallel is isolated the A/D acquiring and processing method.

Background technology

In Industry Control and fields of measurement, in especially process control, fault diagnosis system and the test macro, need to detect in real time a plurality of different physical quantities (as pressure, temperature etc.) of some equipment, system or process.Each physical quantity is provided by the sensor or the transducer of particular type, and the analog voltage signal of its output needs different signal conditioning circuit parameters, as gain, sampling rate and impedance buffering etc.Present existing multichannel data acquisition system mainly contains two kinds of implementations: the one, adopt hyperchannel timesharing switching mode, only finish multi-channel data acquisition with a single channel A/D converter, the real-time of this mode is poor, can't realize that hyperchannel samples simultaneously; The 2nd, adopt the multiple input path A/D converter to catch a plurality of measurands, this mode can realize gathering simultaneously, but the sampling rate of each passage is the same, can not regulate, and only is fit to the situation of all measurand frequency characteristic unanimities.

Summary of the invention

Technical matters to be solved by this invention is at the deficiencies in the prior art, propose a kind of reliability height, real-time, be fit to the different multi-channel parallel of measurand frequency characteristic and isolate the A/D acquiring and processing method.

Technical matters to be solved by this invention is to realize by following technical scheme.The present invention is that a kind of multi-channel parallel is isolated the A/D acquiring and processing method, be characterized in, the circuit of this method is made up of input isolation circuit, signal conditioning circuit, digital isolator and FPGA, the input that walk abreast is isolated and is gathered to the analog voltage signal of hyperchannel, dissimilar sensor output, and the analog voltage signal that each passage is imported is sent to FPGA by input isolation circuit, signal conditioning circuit and digital isolator successively; The earth potential of the end that the input isolation circuit of each passage is connected with signal conditioning circuit is different, does not have the interconnection of ground loop between the passage; Signal conditioning circuit is made of gain adjusting circuit and high-precision ∑-Δ A/D converter, analog voltage signal is sent into gain adjusting circuit behind input isolation circuit, again through ∑-Δ A/D converter, the conversion back generates serial digital amount SDO, exports a serial-shift clock sclk simultaneously and converts marking signal READY; Serial digital amount SDO exports through digital isolator, goes here and there and conversion process by FPGA again, realizes multi-channel parallel isolation A/D acquisition process.

Technical matters to be solved by this invention can also further realize by following technical scheme.Above-described acquiring and processing method is characterized in, the internal circuit of described FPGA comprises input block, output unit, Clock dividers, driver, synchronizing signal steering logic, shift register, latch and storer; Outside input clock CLOCK enters Clock dividers through input block, through driver major clock MCLK signal is sent to output unit again, and simultaneously outside input clock CLOCK generates control signal CONV through the synchronizing signal steering logic and is sent to output unit; Serial digital amount SDO, the serial-shift clock sclk of each passage and convert marking signal READY and be sent to output unit by shift register, latch and storer successively; Input block and output unit are finished the interface processing capacity; Clock dividers and the driver major clock MCLK that generates each passage ∑-Δ A/D converter, thereby the sampling rate of control ∑-Δ A/D converter; The synchronizing signal steering logic is exported the control signal CONV of each passage, is used for being provided with the sampling instant of ∑-Δ A/D converter; Shift register and latch are finished string and conversion process jointly; Place the parallel data after all passages are changed in the storer, realization is communicated by letter with host computer.

FPGA of the present invention (field programmable gate array) can select in the prior art disclosed any FPGA for use and by the field requirement configuration, preferably by FPGA configuration mode of the present invention.The abbreviation of all device name, circuit name, signal definition is all adopted conventional definition of the prior art and is explained if no special instructions among the present invention.

The circuit general function of the inventive method is collection and the processing that realizes a kind of multi-channel parallel isolation A/D, its principle of work is the analog voltage signal at hyperchannel, dissimilar sensor output, the signal conditioning circuit that parameter such as designing gain, sampling rate is different is applicable to the situation that the sensor frequency characteristic is different.In order to improve reliability, the change-over circuit of each passage is implemented both-end and is isolated.Input end at each passage is provided with buffer circuit, and the earth potential difference of each signal conditioning circuit does not have the interconnection of ground loop between the passage, thereby realizes the isolation between the passage.Output terminal uses digital isolator, compares with traditional optocoupler isolator, and power consumption is lower, and volume is littler, and has bidirectional interface, and translation data and serial clock signal that can transmitting high speed can transmit the control signal of low speed again.Each signal conditioning circuit comprises a ∑-Δ A/D converter, the analog voltage signal of sensor output is sent into ∑-Δ A/D converter after isolating, the conversion back generates serial digital amount SDO, exports a serial-shift clock sclk simultaneously and converts marking signal READY.

The present invention at the specific sequential control circuit of FPGA indoor design, sends major clock MCLK and synchronous control signal CONV to each passage according to the principle of work of ∑-Δ A/D converter, finishes the setting to ∑-Δ A/D converter sampling rate and sampling instant.If the frequency characteristic unanimity of each channel sensor is then transmitted control signal by FPGA, realize the real-time parallel synchronous acquisition process of multi-channel data; If the frequency characteristic of each channel sensor is inconsistent, then at each passage suitable sampling rate is set by FPGA, and convert marking signal READY according to what each passage returned, read the serial digital amount SDO after the conversion, go here and there and conversion process, deposit storer in, in order to communicate by letter with host computer, according to the external interface bus difference, design distinct interface circuit realizes that the parallel acquisition of multiple channels data is handled.

Compared with prior art, the present invention has the following advantages:

1, the inventive method adopts the change-over circuit both-end to isolate the reliability height; Can effectively avoid the influence of destructive noise source.

2, the inventive method can realize the parallel synchronous collection, and is real-time; Can realize multichannel synchronousing collection, can be applicable to the inconsistent situation of measurand frequency again, the scope of application is wider.

Description of drawings

Fig. 1 is a theory diagram of the present invention.

Fig. 2 is the signal conditioning circuit block diagram.

Fig. 3 is a FPGA internal circuit block diagram.

Embodiment

Below further describe concrete technical scheme of the present invention,, and do not constitute restriction its right so that those skilled in the art understands the present invention further.

Embodiment 1.With reference to Fig. 1-2.A kind of multi-channel parallel is isolated the A/D acquiring and processing method, the circuit of this method is made up of input isolation circuit, signal conditioning circuit, digital isolator and FPGA, the input that walk abreast is isolated and is gathered to the analog voltage signal of hyperchannel, dissimilar sensor output, and the analog voltage signal that each passage is imported is sent to FPGA by input isolation circuit, signal conditioning circuit and digital isolator successively; The earth potential of the end that the input isolation circuit of each passage is connected with signal conditioning circuit is different, does not have the interconnection of ground loop between the passage; Signal conditioning circuit is made of gain adjusting circuit and high-precision ∑-Δ A/D converter, analog voltage signal is sent into gain adjusting circuit behind input isolation circuit, again through ∑-Δ A/D converter, the conversion back generates serial digital amount SDO, exports a serial-shift clock sclk simultaneously and converts marking signal READY; Serial digital amount SDO exports through digital isolator, goes here and there and conversion process by FPGA again, realizes multi-channel parallel isolation A/D acquisition process.

Embodiment 2.With reference to Fig. 3.In embodiment 1 described acquiring and processing method, the internal circuit of described FPGA comprises input block, output unit, Clock dividers, driver, synchronizing signal steering logic, shift register, latch and storer; Outside input clock CLOCK enters Clock dividers through input block, through driver major clock MCLK signal is sent to output unit again, and simultaneously outside input clock CLOCK generates control signal CONV through the synchronizing signal steering logic and is sent to output unit; Serial digital amount SDO, the serial-shift clock sclk of each passage and convert marking signal READY and be sent to output unit by shift register, latch and storer successively; Input block and output unit are finished the interface processing capacity; Clock dividers and the driver major clock MCLK that generates each passage ∑-Δ A/D converter, thereby the sampling rate of control ∑-Δ A/D converter; The synchronizing signal steering logic is exported the control signal CONV of each passage, is used for being provided with the sampling instant of ∑-Δ A/D converter; Shift register and latch are finished string and conversion process jointly; Place the parallel data after all passages are changed in the storer, realization is communicated by letter with host computer.

Claims

1. a multi-channel parallel is isolated the A/D acquiring and processing method, it is characterized in that, the circuit of this method is made up of input isolation circuit, signal conditioning circuit, digital isolator and FPGA, the input that walk abreast is isolated and is gathered to the analog voltage signal of hyperchannel, dissimilar sensor output, and the analog voltage signal that each passage is imported is sent to FPGA by input isolation circuit, signal conditioning circuit and digital isolator successively; The earth potential of the end that the input isolation circuit of each passage is connected with signal conditioning circuit is different, does not have the interconnection of ground loop between the passage; Signal conditioning circuit is made of gain adjusting circuit and high-precision ∑-Δ A/D converter, analog voltage signal is sent into gain adjusting circuit behind input isolation circuit, again through ∑-Δ A/D converter, the conversion back generates serial digital amount SDO, exports a serial-shift clock sclk simultaneously and converts marking signal READY; Serial digital amount SDO exports through digital isolator, goes here and there and conversion process by FPGA again, realizes multi-channel parallel isolation A/D acquisition process.

2. acquiring and processing method according to claim 1 is characterized in that, the internal circuit of described FPGA comprises input block, output unit, Clock dividers, driver, synchronizing signal steering logic, shift register, latch and storer; Outside input clock CLOCK enters Clock dividers through input block, through driver major clock MCLK signal is sent to output unit again, and simultaneously outside input clock CLOCK generates control signal CONV through the synchronizing signal steering logic and is sent to output unit; Serial digital amount SDO, the serial-shift clock sclk of each passage and convert marking signal READY and be sent to output unit by shift register, latch and storer successively; Input block and output unit are finished the interface processing capacity; Clock dividers and the driver major clock MCLK that generates each passage ∑-Δ A/D converter, thereby the sampling rate of control ∑-Δ A/D converter; The synchronizing signal steering logic is exported the control signal CONV of each passage, is used for being provided with the sampling instant of ∑-Δ A/D converter; Shift register and latch are finished string and conversion process jointly; Place the parallel data after all passages are changed in the storer, realization is communicated by letter with host computer.