CN202510111U - Multi-channel data acquisition circuit applied to array induction logging instrument - Google Patents
Multi-channel data acquisition circuit applied to array induction logging instrument Download PDFInfo
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- CN202510111U CN202510111U CN2012200180759U CN201220018075U CN202510111U CN 202510111 U CN202510111 U CN 202510111U CN 2012200180759 U CN2012200180759 U CN 2012200180759U CN 201220018075 U CN201220018075 U CN 201220018075U CN 202510111 U CN202510111 U CN 202510111U
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Abstract
The utility model discloses a multi-channel data acquisition circuit applied to an array induction logging instrument. The shortcoming of low efficiency caused by capability of acquiring and processing signals of only one channel at one time by the conventional multi-channel data acquisition circuit is overcome. According to the multi-channel data acquisition circuit, for each channel, a signal conditioning circuit is used for receiving an analogue induction signal, and performs low-noise amplification; each signal conditioning circuit is connected with an analogue-to-digital conversion circuit, and converts the analogue signal amplified by the signal conditioning circuit into a digital signal; signal superposition circuits connected with the analogue-to-digital conversion circuits superpose the digital signals output by the analogue-to-digital conversion circuits to obtain superposition signals; a control circuit connected with the analogue-to-digital conversion circuits and the signal superposition circuits controls the conversion and the superposition, and receives the superposition results in series; and a storage circuit connected with the control circuit stores the superposition results. Stratum induction signals received by a plurality of channels can be acquired and processed at the same time.
Description
Technical field
The utility model relates to the induction logging technology of petroleum exploration field, relates in particular to a kind of multi-channel data acquisition circuit that is applied to array induction logging tool.
Background technology
Induction logging be in the petroleum exploration field based on the low frequency logging technique of electromagnetic induction principle, it has encouraged the induced signal on stratum through the alternating current on the transmitting coil, this signal is relevant with the electrical conductivity size on stratum.The receiving coil that array induction logging will be organized different spacing more is arranged on the borehole axis, receives the secondary induced signal of same transmitting coil excitation, is a kind of logging technique of multi-source distance, and the formation conductivity information that obtains is also abundant more and accurate.
Because logging instrument works long hours in the down-hole of circumstance complication, signal receives the interference that receives surrounding environment easily, often has a large amount of noises attached to receiving on the signal, therefore need take certain measure to extract useful signal, suppresses noise and interference.Data acquisition circuit is the key that instrument correctly obtains formation information as the front end and the core of induction log tool receiver module, need carry out at a high speed, accurately gather and handle multichannel, large-capacity data.
The multi-channel circuit method for designing of induction log tool is to all analog-to-digital conversion passages at present; The analog-digital converter (ADC) of the single passage of timesharing gating carries out sample conversion; The transformation result that obtains this passage again send microprocessor or microcontroller further to handle, and then handles rest channels in the same way.Be characterized in once can only gathering and handle the signal after one tunnel analog-to-digital conversion; Rest channels just is in idle state during this period; Can't gather and handle all passages simultaneously, cause the efficient of system very low like this, can not reflect formation conductivity information timely and accurately.
In addition, existing more induction log tool, its each acquisition channel adds that by DSP ADC constitutes, complex structure, it is difficult to safeguard, and cost is higher.
The utility model content
The utility model technical problem to be solved is that the signal of a paths gathered and handled to the multi-channel data acquisition circuit that overcomes existing array induction logging tool once can only and the defective of the inefficiency that causes.
In order to solve the problems of the technologies described above, the utility model provides a kind of multi-channel data acquisition circuit that is applied to array induction logging tool, all adopts signal conditioning circuit reception analogue inductive signal and carries out the low noise amplification for every paths; Each signal conditioning circuit connects an analog to digital conversion circuit separately, converts this signal conditioning circuit amplified analog signal into data signal; The superimposed signal circuit that links to each other with each analog to digital conversion circuit, the data signal of each analog to digital conversion circuit output superposeed obtains stack result; The control circuit that links to each other with this analog to digital conversion circuit and superimposed signal circuit is controlled, this stack result of parallel series reception is controlled in this stack this conversion; With the memory circuit that this control circuit links to each other, store this stack result.
Preferably, this circuit comprises:
Power supply stabilization circuit; Link to each other with those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit, for those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit provide operating voltage.
Preferably, each signal conditioning circuit comprises difference amplifier.
Preferably, each self-contained outer meeting resistance that is connected adjustable voltage gain on the difference amplifier of each signal conditioning circuit.
Preferably; Each analog to digital conversion circuit includes analog-digital converter; And connect a voltage reference circuit jointly, analog-digital converter converts the signal conditioning circuit amplified analog signal into data signal, and this voltage reference circuit provides reference voltage for those analog-digital converters.
Preferably, this control circuit comprises the circuit structure that this stack result is carried out processed compressed, and this memory circuitry stores is through this stack result of processed compressed.
Compared with prior art, the embodiment of the utility model can gather the formation induction signal that receives with the process multi-channel passage simultaneously, handles more efficiently with quick, and result is also more accurate.The multi-channel data acquisition circuit of the embodiment of the utility model adopts DSP digital signal processor and FPGA field programmable gate array structure combining; The formation induction signal of a plurality of passages is gathered and is handled in control simultaneously, has improved the performance and the efficient of system.Every passage is more clear, more directly perceived through the useful signal that obtains after superposeing, compressing, and has eliminated interference of noise effectively, has reflected the electrical conductivity information on stratum more truly, exactly.
Description of drawings
Fig. 1 is the structural representation of the utility model embodiment multi-channel data acquisition circuit.
Fig. 2 is the sketch map that is connected of middle signal conditioning circuit embodiment illustrated in fig. 1 and analog to digital conversion circuit.
Fig. 3 is the circuit catenation principle figure of middle FPGA embodiment illustrated in fig. 1 and DSP.
Fig. 4 is the structure chart of middle FPGA embodiment illustrated in fig. 1 and DSP inner function module.
The specific embodiment
For the purpose, technical scheme and the advantage that make the utility model is clearer, hereinafter will combine accompanying drawing that the embodiment of the utility model is elaborated.Need to prove that under the situation of not conflicting, embodiment among the application and the characteristic among the embodiment be combination in any each other.
The Acquisition Circuit of the utility model embodiment mainly comprises signal conditioning circuit, analog to digital conversion circuit, superimposed signal circuit, control circuit and memory circuit.Wherein, all adopt a signal conditioning circuit to receive the analogue inductive signal of this paths for every paths, and this analogue inductive signal is carried out low noise amplify; Each signal conditioning circuit connects an analog to digital conversion circuit separately, converts this signal conditioning circuit amplified analog signal into data signal; The superimposed signal circuit that links to each other with each analog to digital conversion circuit, the data signal of each analog to digital conversion circuit output superposeed obtains stack result; The control circuit that links to each other with this analog to digital conversion circuit and superimposed signal circuit is controlled, this stack result of parallel series reception is controlled in this stack this conversion; With the memory circuit that this control circuit links to each other, store this stack result.
Among the embodiment of the utility model, signal conditioning circuit mainly is made up of low noise amplifier circuit.Select for use the integrated high-performance appearance of three amplifiers to use difference amplifier, the size of its voltage gain is regulated through outer meeting resistance, and the circuit structure of every passage is identical.The effect of signal conditioning circuit mainly is the induced signal that receives to be carried out low noise amplify, and transfers differential input signal to single-ended signal output.
Among the embodiment of the utility model; Each analog to digital conversion circuit includes analog-digital converter; And connect a voltage reference circuit jointly, analog-digital converter converts the signal conditioning circuit amplified analog signal into data signal, and this voltage reference circuit provides reference voltage for those analog-digital converters.
Among the embodiment of the utility model, the change over clock of analog to digital conversion circuit is produced by control circuit.The effect of analog to digital conversion circuit mainly is a sampling prime amplified analog signal, and converts digital signal corresponding output into, the sampling period number and weekly the sampling number of phase determine by control circuit.
Among the embodiment of the utility model, superimposed signal circuit can be made up of multi-disc (such as two) FPGA and peripheral configuration circuit.The effect one of data stack is the signal to noise ratio that improves signal, suppresses random noise; The 2nd, need to reduce storage and data quantity transmitted.The concrete implementation of one of them embodiment; Be by 4 passages of every FPGA management; The parallel 4 tunnel analog-to-digital results that read; The corresponding data signal of same sampled point of each sampling period is carried out the stack summation of certain number of times, the number of times of stack is determined that by control circuit it is consistent with the induced signal periodicity of being sampled again.
Among the embodiment of the utility model, control circuit mainly is made up of DSP and peripheral configuration circuit.The effect of DSP, the one, the instruction of base area plane system produces the analog-to-digital sampling pulse of control, the stacking fold of control data simultaneously; The 2nd, be responsible for the communication between the FPGA the every passage superimposed data of serial received.This control circuit can also comprise the circuit structure that this stack result is carried out processed compressed, and this memory circuitry stores is through this stack result of processed compressed.This control circuit will compress superimposed data, with coupling external data bus width, reduce the redundancy of useful signal.This control circuit also is responsible for the serial communication between the ground system, receives order and sends data.
Among the embodiment of the utility model, memory circuit mainly is made up of SRAM (SRAM), and the total new and control signal of its data/address bus, address can realize seamless link with DSP, the data after the temporary DSP processed compressed.
The multi-channel data acquisition circuit of the utility model embodiment; Can also comprise the power supply stabilization circuit that links to each other with those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit, for those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit provide operating voltage.Power supply stabilization circuit is made up of linear voltage-stabilized power supply circuit; Each module of system needs a plurality of different operating voltages; Adopt a plurality of low-voltage drop linear power supply chips to provide each device required supply voltage, guarantee the normal operation of system with different output voltages.
Fig. 1 is the structural representation of the multi-channel data acquisition circuit of the utility model embodiment.As shown in Figure 1, the Acquisition Circuit of the utility model embodiment mainly comprises some signal conditioning circuits (AMP) (with 30～37 eight signal conditioning circuits being shown among the figure), analog to digital conversion circuit (A/D) (in figure with 40～47 eight analog to digital conversion circuits are shown), voltage reference unit 50, field programmable gate array (FPGA) (in figure with 21,22 two field programmable gate arrays are shown), digital signal processor (DSP) 11, data storage cell 60 and the power supply stabilization circuit 70 identical with signal conditioning circuit quantity.
Each paths is corresponding to a signal conditioning circuit and an analog to digital conversion circuit, and is as shown in Figure 1, and the Acquisition Circuit of the utility model embodiment is gathered 8 paths (illustrating with CH0～CH7 among the figure).Connection and operating principle corresponding to the signal conditioning circuit of each paths and analog to digital conversion circuit are all identical; Therefore present embodiment is that example describes with the circuit structure on the first passage CH0 wherein; The signal conditioning circuit on the rest channels and the situation of analog to digital conversion circuit are identical with first passage CH0, then please refer to the situation of first passage CH0 like no specified otherwise.In addition, the embodiment of the utility model is that example describes with 8 paths, and the embodiment of all the other quantity passages please contrast understanding.
Gather the circuit of first passage CH0; Comprise interconnective first signal conditioning circuit 30 and first analog to digital conversion circuit 40; The analogue inductive signal that this first signal conditioning circuit 30 amplifies on the first passage CH0, this first analog to digital conversion circuit 40 converts the analogue inductive signal into data signal.The data signal that each road analog to digital conversion circuit will be changed gained concurrently separately is transferred to FPGA concurrently; Wherein first to fourth analog to digital conversion circuit 40～43 gives the 2nd FPGA 22 with digital data transmission for a FPGA the 21, the five to the 8th analog to digital conversion circuit 44～47 digital data transmission.The one FPGA 21 and the 2nd FPGA 22 manage the data write and the stack of four passages separately.
DSP 11 links to each other with two FPGA, each analog to digital conversion circuit, data storage cell (like random access memory ram) 60 and power supply stabilization circuit 70, controls whole gatherer process, processing and transmission data.
With reference to Fig. 2, the low noise difference appearance that the utility model embodiment selects for use passes through outer meeting resistance R with difference amplifier 30
GRegulate closed-loop valtage gain.An its IN input and+IN input receive the difference induced signal of prime cycle T=128 μ s (microsecond), select the resistance of certain resistance, set closed-loop valtage gain G ≈ 5, the difference induced signal of input is carried out low noise amplify, again by V
OUTPin is exported single-ended analog signal to ADC 40.
With reference to Fig. 2; The analog signal that the VIN input termination of ADC 40 is amplified back cycle T=128 μ s; Its CONVST conversion begins to import the sampling pulse BURST of the f=1MHz (megahertz) that termination DSP 11 provides; CLK IN clock input pin connects the IO pin of FPGA 21, and REF IN connects the output voltage V of reference voltage source 50 with reference to input pin
REF=2.5V.Whether BUSY signal indication once conversion is accomplished, and its trailing edge is represented the data after the single conversion end can be read conversion.ADC 40 begins conversion at the trailing edge of CONVST signal, to each periodic sampling of input signal 128 times, then through DB0～DB11 data/address bus and 12 (bit) data signal to the FPGA 21 of line output.
Fpga chip has abundant input and output (IO) port and logical resource; And static complementary metal oxide semiconductors (CMOS) (CMOS) technology makes it have high-performance, low in power consumption, is suitable for a large amount of IO of needs expansion and the accurate industrial applications of SECO.The embodiment of the utility model is responsible for reading while write and superposeing of 4 circuit-switched data by every FPGA, helps simplifying circuit structure and improves the speed of service.
With reference to Fig. 3 and Fig. 4; The input clock frequency of the one FPGA 21 and the 2nd FPGA 22 is 48MHz; The START signal is the synchronous enabling signal of sampling pulse BURST, and it is produced by DSP 11, is used to indicate a FPGA 21 and the 2nd FPGA 22 outside analog-to-digital beginnings and stops.At it is that Synchronous Sampling Pulse is effective between high period, and the high level duration is set the induced signal in 1024 cycles of sampling at least to the induced signal periodicity in requisition for sampling, and analog to digital conversion circuit 40～47 is sampled during this period and changed.
With reference to Fig. 3 and Fig. 4, FPGA 21 is written in parallel to 12 position digital signals of first analog to digital conversion circuit 40 when the trailing edge of BUSY signal arrives.Because each periodic sampling 128 times, so the data signal of corresponding 128 sampled points of each analog signal deposit it among RAM 211～214 of FPGA 21 inner 128 * 32bit that define in, high 20 that figure place is not enough expand to zero.The digital addition summation that each sampled point is corresponding then; Stacking fold is consistent with the induced signal periodicity of sampling; The content in the random-access memory (ram) 211～214 is once just upgraded in addition immediately, and the content of last storage is through the result after at least 1024 stacks among the RAM 211～214.
The one FPGA 21 inner multiplexers (MUX) 215 switch the output in turn of 8 passages under the effect of channel selecting signal Channel [2:0], the superposition of data that every passage is corresponding is transferred to DSP 11.Adopt serial communication between the one FPGA 21 and the DSP 11; Therefore realize parallel-to-serial conversion with shift register (Shift Register) 216; Through synchronous serial Peripheral Interface (SPI) 217 data SDO is sent, serial clock (SCLK) and frame synchronizing signal (FSR) are provided by DSP11 again.
The embodiment of the utility model adopts the 32bit fixed-point DSP chip of dominant frequency up to 150MHz, and core voltage is merely 1.8 volts (V), and precision is high, speed is fast, low in energy consumption.Various peripheral functionality modules commonly used that DSP is inner integrated, the involved functional module of the utility model embodiment has task manager 111, multichannel buffer serial port (MCBSP) 112, serial communication interface 114 and external expansion interface 115.
With reference to Fig. 3 and Fig. 4, the embodiment of the utility model adopts EVM task manager 111 to produce Synchronous Sampling Pulse BURST and corresponding synchronous control signal START that frequency equals 1MHz.The input clock frequency of DSP11 is 30MHz, and the value that therefore period register of general purpose timer 1 in the EVM task manager 111 is set is 0x001D, adopts to increase count mode continuously, from the square-wave signal of external pin output frequency f=1MHz.
With reference to Fig. 3 and Fig. 4, because being signal period number according to the needs collection of setting, sampling pulse produces, so need to produce a synchronous enabling signal it is controlled.Method is following: the signal that frequency is equaled 1MHz is received the timer input of general purpose timer 2 in the task manager 111; After DSP 11 receives the order that ground system sends; START is changed to 1 with control signal; 2 pairs of these signals of general timer conter increase counting continuously simultaneously; Reach the requirement of corresponding sampling number when count value after, the zero clearing counter also puts 0 with the START signal, and the signal that consequent START signal equals 1MHz with this frequency again obtains the Synchronous Sampling Pulse BURST of frequency f=1MHz through outside NAND Logic.
With reference to Fig. 3 and Fig. 4, there is 32 FIFOs (FIFO) structure of two 16 grades of degree of depth multichannel buffered serial port 112 inside, are with three grades of bufferings to receive, and are responsible for reading 32 digit wave form data after FPGA 21 superposes by it, can reduce the expense of innernal CPU.The signal that relates to has serial data to receive pin DR, receive clock pin CLKR, the synchronous pin FSR of received frame.At first, MCBSP 112 clock internal and frame maker produce serial received clock signal SCLK and frame synchronizing signal FSR, output to the transmission of FPGA 21 with indication and control waveform data.Secondly, MCBSP 112 mode by minute group of received under SCLK and FSR control writes external signal SDO from the DR pin, and each frame serial word is 32 bit lengths.Once more, utilize the GPIO pattern synchronization of DSP 11 pins to produce channel selecting signal Channel [2:0],, after the data reception of a passage finishes, switch next passage of reception by three transmit port outputs of MCBSP 112.At last, 32 bit data that receive are sent into data compression unit 113, restrain 16 of 13 broken line coded format boil down tos, to mate outside data-bus width according to A.
With reference to Fig. 3 and Fig. 4 owing to receive the data of 8 passages altogether simultaneously, need data quantity stored very big, so with the external expansion interface (XINTF) 115 of DSP 11 with the extension storage space.16 outside growth data bus and 19 outside extended address bus are connected with a slice RAM SRAM 60, the data after the temporary transient store compressed.The serial communication interface of DSP 11 (SCI) 114 is used for establishing a communications link between the ground system; The RXD pin receives the well logging order that ground system issues; Then according to the duty of corresponding instruction control system, the 16 digit wave form data upload that the TXD pin sends are after treatment analyzed and are explained to ground system.
Among the embodiment of the utility model, each road signal conditioning circuit all selects for use ± and low cost, the low-power consumption appearance of 5V power supply use difference amplifier, and closed-loop valtage gain is through the outer meeting resistance adjusting, and single-ended output signal connects the input of analog-digital converter.
Among the embodiment of the utility model, the cycle T that transmits=128 μ s, 12 of the conversion accuracies of analog-digital converter ADC; Outside high-precision voltage reference provides 2.5V reference voltage; Change over clock is the 1MHz sampling pulse that DSP produces, and the duration of sampling pulse, by DSP control, acquired signal periodicity and stacking fold were consistent equally; To each periodic sampling 128 point of input signal, gather at least 1024 moduluss of periodicity and intend induced signal.
Among the embodiment of the utility model; FPGA is in charge of and reads 4 tunnel 12 data signals after the analog-to-digital conversion; High-order mend 0 and expand to 32 bit widths at it, 128 point data that phase sampling weekly obtains are carried out at least 1024 times stack, the signal period number of stacking fold and collection is consistent; Obtain 128 32 data after the stack, it is deposited among the RAM of 128 * 32bit.
Among the embodiment of the utility model; The multiplexer (MUX) of the inner definition of FPGA; 3 bit ports by the buffered serial port of DSP provides are selected signal channel [2:0] control, switch, select different passage output, and through Serial Peripheral Interface (SPI) (SPI) 32 bit data serials are sent to DSP.
Among the embodiment of the utility model, it is Synchronous Sampling Pulse and the synchronous control signal of 1MHz that the timing of DSP produces frequency; Wherein, the break-make of synchronous control signal control 1MHz sampling pulse is that the output of 1MHz sampling pulse is effective between high period at it, and the number of sampling pulse is by the periodicity of sampled signal, the sampling number decision of phase weekly, and the three is consistent.
Among the embodiment of the utility model; DSP receives the data flow that the FPGA serial sends over by multichannel buffered serial port; The inner continuous reception that produces receive clock CLKR and frame synchronizing signal FSR control data of MCBSP; Produce 3 channel selecting signal channel [2:0] again by the GPIO pattern synchronization of three transmit ports of free time, switch the transfer of data of 8 passages.
Among the embodiment of the utility model, DSP uses A to restrain 13 broken line compression coding modes with 16 of the linear boil down tos of 32 bit data, is made up of 4 paragraph sign indicating numbers and 12 section ISNs; Expansion is connected the external RAM unit with temporal data to the data/address bus of DSP with address bus, and asynchronous serial communication mode (SCI) transmitting-receiving order and data are adopted in its communication with ground system.
Among the embodiment of the utility model,, simple in structure by the collection and the processing of FPGA (field programmable gate array) and DSP (digital signal processor) control data.
As shown in Figure 1, the embodiment of the utility model is gathered and digital overlap-add procedure when ADC analog-digital converter etc. has been realized 8 circuit-switched data by 2 FPGA and peripheral configuration circuit, is beneficial to the subsequent treatment of formation signal.4 passages of every FPGA management, the parallel 4 tunnel analog-to-digital results that read carry out the corresponding data signal of same sampled point of each sampling period the stack summation of certain number of times again.
Among the embodiment of the utility model, each channel data is more clear, truer through the useful signal that obtains after the processing such as stack simultaneously, has eliminated interference of noise effectively, has improved efficient.
Contrast the multi-channel data acquisition circuit of present existing array induction logging tool; The embodiment of the utility model adopts the DSP digital signal processor to combine FPGA field programmable gate array structure combining; The formation induction signal of a plurality of passages is gathered and is handled in control simultaneously, has improved the performance and the efficient of system.Every passage is more clear, more directly perceived through the useful signal that obtains after superposeing, compressing, and has eliminated interference of noise effectively, has reflected the electrical conductivity information on stratum more truly, exactly.
Among the embodiment of the utility model; Said DSP module receives the acquisition that ground system sends; Produce an effective sampling control signal of high level; And export the sampling clock of Synchronous Sampling Pulse simultaneously as analog to digital conversion circuit, and the analog-digital converter that starts all passages is simultaneously gathered the induced signal on stratum, and the signal number that needs to gather is by the DSP module controls.The data signal of the every passage analog-to-digital conversion output of said FPGA module parallel receive; Data to each sampled point superpose to improve signal to noise ratio; The sampling number of phase is by the frequency decision of sampling clock weekly, and stacking fold is that periodicity is consistent with the signal number that needs to gather.Said DSP module is carried out processed compressed to the data after the stack summation again, further reduces to deliver to the data volume of ground system, improves efficiency of transmission.The present invention is through experiment and test, and the useful signal that obtains at last is accurate, clear, for analyzing and explaining that the stratum provides reliable basis.
Though the embodiment that the utility model disclosed as above, the embodiment that described content just adopts for the ease of understanding the utility model is not in order to limit the utility model.Technician under any the utility model in the technical field; Under the prerequisite of spirit that does not break away from the utility model and disclosed and scope; Can do any modification and variation what implement in form and on the details; But the scope of patent protection of the utility model still must be as the criterion with the scope that appending claims was defined.
Claims (6)
1. a multi-channel data acquisition circuit that is applied to array induction logging tool is characterized in that, all adopts signal conditioning circuit reception analogue inductive signal and carries out the low noise amplification for every paths; Each signal conditioning circuit connects an analog to digital conversion circuit separately, converts this signal conditioning circuit amplified analog signal into data signal; The superimposed signal circuit that links to each other with each analog to digital conversion circuit, the data signal of each analog to digital conversion circuit output superposeed obtains stack result; The control circuit that links to each other with this analog to digital conversion circuit and superimposed signal circuit is controlled, this stack result of parallel series reception is controlled in this stack this conversion; With the memory circuit that this control circuit links to each other, store this stack result.
2. circuit according to claim 1 is characterized in that, this circuit comprises:
Power supply stabilization circuit; Link to each other with those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit, for those signal conditioning circuits and analog to digital conversion circuit, this superimposed signal circuit, this control circuit and this memory circuit provide operating voltage.
3. circuit according to claim 1 and 2 is characterized in that:
Each signal conditioning circuit comprises difference amplifier.
4. circuit according to claim 3 is characterized in that:
Each self-contained outer meeting resistance that is connected adjustable voltage gain on the difference amplifier of each signal conditioning circuit.
5. circuit according to claim 1 and 2 is characterized in that:
Each analog to digital conversion circuit includes analog-digital converter, and connects a voltage reference circuit jointly, and analog-digital converter converts the signal conditioning circuit amplified analog signal into data signal, and this voltage reference circuit provides reference voltage for those analog-digital converters.
6. circuit according to claim 1 and 2 is characterized in that:
This control circuit comprises the circuit structure that this stack result is carried out processed compressed, and this memory circuitry stores is through this stack result of processed compressed.
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| CN2012200180759U CN202510111U (en) | 2012-01-16 | 2012-01-16 | Multi-channel data acquisition circuit applied to array induction logging instrument |
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| CN103064316A (en) * | 2012-12-24 | 2013-04-24 | 河海大学常州校区 | Synchronous denoising multichannel ultrasonic signal acquisition system |
| CN104343444A (en) * | 2014-10-29 | 2015-02-11 | 任勇 | Time-sharing driven lateral logging method and device |
| CN104481525A (en) * | 2014-11-28 | 2015-04-01 | 中国石油天然气集团公司 | Quick-measurement array induction logging system and method |
| CN104482885A (en) * | 2014-12-04 | 2015-04-01 | 哈尔滨工业大学 | Four-reading-head incremental circular grating coupler |
| CN108803418A (en) * | 2018-06-12 | 2018-11-13 | 上海航天计算机技术研究所 | A kind of AD automated collection systems that FPGA is realized |
| CN110334048A (en) * | 2019-07-17 | 2019-10-15 | 陕西千山航空电子有限责任公司 | A kind of Strong Impact Loading wireless collection storage circuit |
| CN112160744A (en) * | 2020-09-27 | 2021-01-01 | 电子科技大学 | Measuring device for ultra-deep resistivity |
| CN112160746A (en) * | 2020-09-27 | 2021-01-01 | 电子科技大学 | Time domain measuring device for ultra-deep resistivity logging |
| CN112177602A (en) * | 2020-09-27 | 2021-01-05 | 电子科技大学 | Time domain measurement method for ultra-deep resistivity logging |
| CN112241131A (en) * | 2020-09-07 | 2021-01-19 | 河北汉光重工有限责任公司 | AD7609 multichannel analog signal synchronous acquisition system based on FPGA |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103064316A (en) * | 2012-12-24 | 2013-04-24 | 河海大学常州校区 | Synchronous denoising multichannel ultrasonic signal acquisition system |
| CN103064316B (en) * | 2012-12-24 | 2015-01-21 | 河海大学常州校区 | Synchronous denoising multichannel ultrasonic signal acquisition system |
| CN104343444A (en) * | 2014-10-29 | 2015-02-11 | 任勇 | Time-sharing driven lateral logging method and device |
| CN104481525B (en) * | 2014-11-28 | 2017-06-06 | 中国石油天然气集团公司 | A kind of fast survey array induction logging system and its logging method |
| CN104481525A (en) * | 2014-11-28 | 2015-04-01 | 中国石油天然气集团公司 | Quick-measurement array induction logging system and method |
| CN104482885A (en) * | 2014-12-04 | 2015-04-01 | 哈尔滨工业大学 | Four-reading-head incremental circular grating coupler |
| CN104482885B (en) * | 2014-12-04 | 2017-01-25 | 哈尔滨工业大学 | Four-reading-head incremental circular grating coupler |
| CN108803418A (en) * | 2018-06-12 | 2018-11-13 | 上海航天计算机技术研究所 | A kind of AD automated collection systems that FPGA is realized |
| CN110334048A (en) * | 2019-07-17 | 2019-10-15 | 陕西千山航空电子有限责任公司 | A kind of Strong Impact Loading wireless collection storage circuit |
| CN112241131A (en) * | 2020-09-07 | 2021-01-19 | 河北汉光重工有限责任公司 | AD7609 multichannel analog signal synchronous acquisition system based on FPGA |
| CN112160744A (en) * | 2020-09-27 | 2021-01-01 | 电子科技大学 | Measuring device for ultra-deep resistivity |
| CN112160746A (en) * | 2020-09-27 | 2021-01-01 | 电子科技大学 | Time domain measuring device for ultra-deep resistivity logging |
| CN112177602A (en) * | 2020-09-27 | 2021-01-05 | 电子科技大学 | Time domain measurement method for ultra-deep resistivity logging |
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