CN217062065U - Embedded substrate - Google Patents

Abstract

The utility model provides an embedded substrate. The embedded substrate includes: a first dielectric layer; a second dielectric layer on the first dielectric layer, the first and second dielectric layers having a junction surface; a semiconductor die embedded in the first dielectric layer and the second dielectric layer, a distance between an active surface of the semiconductor die and the bonding surface being less than a distance between a back side of the semiconductor die and the bonding surface. The utility model discloses an above-mentioned formula substrate of burying can solve at least that the dielectric layer thickness is inhomogeneous problem on the active face of the pipe core of burying in the substrate.

Description

Embedded substrate

Technical Field

The utility model relates to a semiconductor device technical field specifically, relates to an embedded substrate.

Background

Referring to fig. 1a, in a Semiconductor Embedded component technology (SESUB) for embedding a Semiconductor chip into a package SUBstrate, a first dielectric layer 12, such as a resin film, is first formed on a SUBstrate 10, a SUBstrate support (SUS frame)20 and an active-side-up Die (Die)30 are then placed on an upper surface of the first dielectric layer 12, a second dielectric layer 14, such as a resin film, is then formed, a metal layer 16, such as Copper (Copper), is then formed, and a force is applied to press down the Die 30 to be Embedded into the first dielectric layer 12 and the second dielectric layer 14, and then a position of a Pad 32 on an active side of the Die is determined, and a through hole 40 extending from the metal layer 16 to the Pad 32 is formed by a sand-blasting method, thereby obtaining an Embedded SUBstrate 100.

FIG. 1b is a top view of the substrate holder 20. As shown in fig. 1b, the substrate holder 20 includes a main frame 25 and a grid frame 24. The substrate holder 20 is divided into a plurality of regular work zones 22 surrounded by a mainframe 25. A plurality of grid frames 24 within each work area 22 divide the work area 22 into a plurality of regular mesh openings 26. A plurality of dies 30 are disposed in each active area 22 when the substrate support 20 and dies 30 are disposed on the first dielectric layer 12. The buried substrate 100 may be cut in a subsequent process by the work area 22 as a cutting unit.

In the process of applying a force to press down on the metal layer 16, a portion of the second dielectric layer 14 may overflow the mesh 26 of the substrate holder 20, thereby deteriorating the uniformity of the thickness of the second dielectric layer 14. Second dielectric layer 14 after applying pressure to metal layer 16 second dielectric layer 14, second dielectric layer 14 at the middle of substrate support 20 has a greater thickness, and second dielectric layer 14 at the four borders of substrate support 20 has a lesser thickness. Therefore, the second dielectric layer 14 is easily extruded from the edge of the substrate holder 20 to cause flash. Referring to fig. 1c and 1d, the overflow phenomenon is analyzed with a mesh 26 at the edge of the substrate holder 20 as a reference unit.

Fig. 1c is a top view of the buried substrate 100 at one mesh 26 at the edge of the substrate support 20, which position corresponds to region B in fig. 1B. Fig. 1d is a cross-sectional view taken along line a-a' of fig. 1c, in the process of forming the embedded substrate 100, the substrate 10 is adhered to the carrier 60 by the adhesive layer 50, a part of the surface of the carrier 60 is covered by the substrate 10 and is shown as a covered region 62 in the top view 1c, and another part of the surface of the carrier 60 is exposed outside the substrate 10 and is shown as an exposed region 64 in fig. 1 c. In the process of pressing down the metal layer 16, the second dielectric layer 14 at the edge of the substrate support 20 is squeezed out and overflows to the exposed region 64 of the carrier plate 60, thereby forming an overflow phenomenon at the region a.

The thickness of the second dielectric layer 14 at the edge of the base plate 10 becomes thinner due to the extrusion of the second dielectric layer 14 at the edge of the substrate holder 20, while the second dielectric layer 14 near the center of the base plate 10 becomes relatively thicker. The thickness of the portion of the second dielectric layer 14 over the pad 32a on the active surface of the die 30 is varied, and the overall thickness difference (maximum thickness-minimum thickness) of the second dielectric layer 14 can be up to 26 μm. In the subsequent process of drilling by sandblasting to form the through-hole 40, due to the excessive thickness difference of the second dielectric layer 14, when the holes at the periphery of the substrate 10 have reached a predetermined depth (the pad 32a has been exposed), the holes near the center of the substrate 10 have not yet reached the pad 32a, i.e., a problem of disqualification of the subsequently formed through-hole 40 occurs; conversely, the process parameters of the sandblasting process are adjusted so that the hole near the center of the substrate 10 reaches a predetermined depth (exposing the pad 32a), and the pad 32b corresponding to the hole at the periphery/edge of the substrate 10 is damaged by the over-sandblasting.

SUMMERY OF THE UTILITY MODEL

To solve the problems in the related art, an object of the present invention is to provide a buried substrate, so that a dielectric layer above an active surface of a die buried in the substrate has a uniform thickness.

The utility model provides an embedded substrate, embedded substrate includes: a first dielectric layer; a second dielectric layer on the first dielectric layer, the first and second dielectric layers having a junction surface; and the semiconductor die is embedded in the first dielectric layer and the second dielectric layer, and the distance between the active surface of the semiconductor die and the joint surface is smaller than the distance between the crystal back of the semiconductor die and the joint surface.

In some embodiments, the active surface of the semiconductor die faces a lower surface of the first dielectric layer and the back-of-wafer faces an upper surface of the second dielectric layer, the buried substrate further comprising: a first via extending from a lower surface of the first dielectric layer to the active surface of the semiconductor die.

In some embodiments, the depth of the first via is approximately equal to the distance between the lower surface of the first dielectric layer and the bonding surface.

In some embodiments, the active surface of the semiconductor die is embedded within the first dielectric layer, and the thickness of the semiconductor die within the second dielectric layer is greater than the thickness of the semiconductor die within the first dielectric layer

In some embodiments, the thickness of the second dielectric layer is greater than the thickness of the semiconductor die.

In some implementations, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

In some embodiments, the first dielectric layer and the second dielectric layer comprise the same material.

In some embodiments, the first dielectric layer and the second dielectric layer are different materials.

The utility model discloses an on the other hand still provides another kind of embedded substrate, include: a first dielectric layer; a second dielectric layer on the first dielectric layer; and the semiconductor die is embedded in the first dielectric layer and the second dielectric layer, the active surface of the semiconductor die faces to the lower surface of the first dielectric layer, and the roughness of the lower surface of the first dielectric layer is smaller than that of the upper surface of the second dielectric layer.

In some embodiments, a pad of the semiconductor die on the active surface is buried in the first semiconductor layer and a remaining portion of the semiconductor die is buried in the second semiconductor layer.

In some embodiments, a distance between the active face of the semiconductor die and the interface of the first dielectric layer and the second dielectric layer is less than a distance between the back side of the wafer of the semiconductor die and the interface.

The utility model discloses an on the other hand still provides another kind of embedded substrate, include: a first dielectric layer; a second dielectric layer on the first dielectric layer; the semiconductor tube core is embedded in the first dielectric layer and the second dielectric layer, the active surface of the semiconductor tube core faces to the lower surface of the first dielectric layer, and the crystal back of the semiconductor tube core faces to the upper surface of the second dielectric layer; and a second via extending from a lower surface of the first dielectric layer to an upper surface of the second dielectric layer and having a lateral dimension that gradually decreases, a distance from a junction surface between the first dielectric layer and the second dielectric layer to the lower surface of the first dielectric layer being smaller than a distance from the junction surface to the upper surface of the second dielectric layer.

In some embodiments, a lateral dimension of the second via at the interface is smaller than a lateral dimension of the second via at the lower surface of the first dielectric layer.

In some embodiments, further comprising: a first via extending from a lower surface of the first dielectric layer to a pad on the active surface of the semiconductor die and having a lateral dimension that gradually decreases.

In some embodiments, the second via is disposed around the semiconductor die.

In some embodiments, a distance between the active surface of the semiconductor die and the bonding surface is less than a distance between the back side of the semiconductor die and the bonding surface.

In some embodiments, the roughness of the lower surface of the first dielectric layer is less than the roughness of the upper surface of the second dielectric layer.

In some embodiments, a pad of the semiconductor die on the active surface is buried within the first semiconductor layer and a remaining portion of the semiconductor die is buried within the second semiconductor layer.

In some embodiments, the thickness of the second semiconductor layer is greater than the thickness of the semiconductor die.

In some embodiments, the second via is a hollow structure affixed within the first dielectric layer and the second dielectric layer.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1a to 1d are schematic views illustrating a conventional buried substrate process.

Fig. 2 is a schematic structural diagram of a buried substrate according to an embodiment of the present invention.

Fig. 3a to 3o are schematic diagrams illustrating steps of a method for forming an embedded substrate according to an embodiment of the present invention.

Detailed Description

For a better understanding of the spirit of the embodiments of the present invention, some preferred embodiments of the present invention will be described in detail below.

Embodiments of the present invention will be described in detail below. Throughout the present specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are intended to provide a basic understanding of the invention. The embodiments of the present invention should not be construed as limiting the invention.

An embodiment of the utility model provides an embedded substrate 1000. Fig. 2 is a schematic structural diagram of an embedded substrate 1000 according to an embodiment of the present invention. As shown in fig. 2, the buried substrate 1000 includes a first dielectric layer 100 and a second dielectric layer 200 on the first dielectric layer 100, the first dielectric layer 100 and the second dielectric layer 200 having a junction 150. The semiconductor die 300 is embedded in the first dielectric layer 100 and the second dielectric layer 200, the active surface 310 of the semiconductor die 300 faces the lower surface of the first dielectric layer 100, and the back of the semiconductor die 300 faces the upper surface of the second dielectric layer 200. The flatness of the lower surface of the first dielectric layer 100 is superior to that of the upper surface of the second dielectric layer 200. And, the roughness of the lower surface of the first dielectric layer 100 is less than the roughness of the upper surface of the second dielectric layer 200.

The second dielectric layer 200 may have a problem of poor thickness uniformity due to the flash phenomenon caused by pressure, and the embodiment of the present invention enables the active surface 310 of the semiconductor die 300 to be away from the second dielectric layer 200 with poor thickness uniformity by embedding the semiconductor die 300 into the first dielectric layer 100 and the second dielectric layer 200 in a manner that the active surface 310 is away from the second dielectric layer 200 and faces the first dielectric layer 100.

In some embodiments, the material of the first and second dielectric layers 100 and 200 includes resin (resin), Polyimide (PI), Ajinomotobuild-up film (ABF), polypropylene (PP), and the like. In some embodiments, the materials of the first and second dielectric layers 100 and 200 are the same. In some embodiments, the materials of the first and second dielectric layers 100 and 200 are different. In some embodiments, the thickness of the second dielectric layer 200 is greater than the thickness of the first dielectric layer 100. In some embodiments, the thickness of the second dielectric layer 200 may be 75 μm. In some embodiments, the thickness of the first dielectric layer 100 may be 35 μm.

The active surface 310 of the semiconductor die 300 is embedded within the first dielectric layer 100 and the back side of the semiconductor die 300 is embedded within the second dielectric layer 200. A first distance H1 is between the active surface 310 of the semiconductor die 300 and the bonding surface 150 of the first dielectric layer 100 and the second dielectric layer 200, and a second distance H2 is between the back side of the semiconductor die 300 and the bonding surface 150. In some embodiments, H1 < H2. That is, the distance between the active surface 310 of the semiconductor die 300 and the bonding surface 150 is smaller than the distance between the back side of the semiconductor die 300 and the bonding surface 150. A first distance H1 between active surface 310 of semiconductor die 300 and bonding surface 150 may simultaneously represent the thickness of the portion of semiconductor die 300 within first dielectric layer 100, and a second distance H2 between the back side of semiconductor die 300 and bonding surface 150 may represent the thickness of the portion of semiconductor die 300 within second dielectric layer 200. In embodiments of H1 < H2, the thickness of semiconductor die 300 within first dielectric layer 100 is less than the thickness of semiconductor die 300 within second dielectric layer 200.

A pad 302 is disposed on the active surface 310 of the semiconductor die 300. In some embodiments, the pads 302 of the semiconductor die 300 are buried within the first dielectric layer 100 and the remainder of the semiconductor die 300 is buried within the second dielectric layer 200. That is, in the above embodiment, H1 may be 0. In some embodiments, the thickness of second dielectric layer 200 is greater than the thickness of semiconductor die 300.

In some embodiments, the buried substrate 1000 further includes a first via 400 extending from the lower surface of the first dielectric layer 100 toward the active surface 310 of the semiconductor die 300. The first via 400 extends to the pad 302 of the semiconductor die 300 and is physically and electrically connected with the pad 302 of the semiconductor die 300. The lateral dimension of the first via 400 gradually decreases in a direction from the lower surface of the first dielectric layer 100 to the joint surface 150. In some embodiments, the depth of the first via 400 is approximately equal to the distance from the bottom surface of the first dielectric layer 100 to the bonding surface 150. In some embodiments, the depth of the first via 400 is less than the distance from the bottom surface of the first dielectric layer 100 to the bonding surface 150. In some embodiments, the material of the first via 400 includes a metal material such as copper. In an embodiment of the present invention, the first through hole 400 connected to the active surface 310 of the semiconductor die 300 is disposed in the first dielectric layer 100 having good planar flatness, improving the uniformity of the hole depth of the first through hole 400.

In some embodiments, the buried substrate 1000 also includes a second via 500. The second via 500 extends from the lower surface of the first dielectric layer 100 to the upper surface of the second dielectric layer 200 and the lateral dimension of the second via 500 gradually decreases. The second via 500 is disposed around the semiconductor die 300. In some embodiments, the second via 500 is a hollow structure attached within the first dielectric layer 100 and the second dielectric layer 200, and the third dielectric layer 430 is filled within the second via 500. In some embodiments, the material of the third dielectric layer 430 includes polypropylene (PP). In some embodiments, the second via 500 may also be a solid via similar to the first via 400. In some embodiments, the second via 500 comprises the same material as the first via 400. The second via 500 has a first lateral dimension W1 at the lower surface of the first dielectric layer 100, while the second via 500 also has a second lateral dimension W2 at the interface 150, W1 > W2. In some embodiments, the thickness of the first dielectric layer 100 is less than the thickness of the second dielectric layer 200, and the distance from the bonding surface 150 to the lower surface of the first dielectric layer 100 is less than the distance from the bonding surface 150 to the upper surface of the second dielectric layer 200, i.e., the bonding surface 150 is closer to the lower surface of the first dielectric layer 100. Since the lateral dimension of the second via 500 is larger as approaching the lower surface of the first dielectric layer 100, the lateral dimension W2 of the second via 500 at the joint surface 150 is larger as the joint surface 150 approaches the lower surface of the first dielectric layer 100. The second via 500 having a larger dimension at the interface 150 can resist stress that may exist at the interface 150, and thus, disposing the interface 150 closer to the lower surface of the first dielectric layer 100 (i.e., disposing the thickness of the first dielectric layer 100 less than the thickness of the second dielectric layer 200) can enhance structural stability.

Table 1 is a list of via depths for vias 40 in a conventional arrangement such as that shown in fig. 1 a. Table 2 shows the depth of the first through hole 400 of the present invention. "Mvia" represents a micro Via (micro Via), "Slot Via" represents a groove-like Via formed by merging a plurality of mvias, "USL" represents a specification upper limit of a hole depth, "max." represents a maximum value of a hole depth, "avg." represents an average value of a hole depth, "min." represents a minimum value of a hole depth, "LSL" represents a specification lower limit of a hole depth, and a unit of the values in the table is "μm". As can be seen from Table 1, the maximum hole depth of the conventional through-hole 40 is 35 μm, the minimum hole depth is 8 μm, and the difference in hole depths can reach 27 μm. As can be seen from Table 2, the maximum hole depth of the examples of the present application was 28 μm, the minimum hole depth was 22 μm, and the difference in hole depths was 6 μm. It can be known through the comparison, the embodiment of the utility model discloses a hole depth difference that makes the through-hole that is located on the tube core drops to 6 μm by 27 μm, has greatly improved the too big problem of hole depth difference.

	USL	Max.	Avg.	Min.	LSL
						Mvia
	35	35	24	12	17
						Slot Via	30	29	17	8	12

TABLE 1

	USL	Max.	Avg.	Min.	LSL
						Mvia
	35	26	24	22	17
						Slot Via	30	28	26	24	12

TABLE 2

Fig. 3a to fig. 3o are schematic diagrams illustrating steps of a method for forming an embedded substrate according to an embodiment of the present invention.

As shown in fig. 3a, a release layer 404 is attached to the carrier 402. The carrier 402 and the release layer 404 are then subjected to a thermal bake process. In some embodiments, the carrier plate 402 comprises a steel plate. In some embodiments, the material of the release layer 404 includes a thermal cracking glue.

As shown in fig. 3b, a metal layer 410 is disposed on the release layer 404 using, for example, a lamination process. Metal layer 410 includes a first metal layer 412 bonded to release layer 404 and a second metal layer 414 on first metal layer 412. In some embodiments, first metal layer 412 is 18 μm thick. In some embodiments, the thickness of the second metal layer 414 is 5 μm. In some embodiments, the material of the metal layer 410 includes copper. In some embodiments, the metal layer 410 may be a copper foil. In some embodiments, the material of the metal layer 410 may be other metals.

As shown in fig. 3c, an opening 4102 may be provided in metal layer 410, e.g. using a photolithography process, that extends through metal layer 410 and exposes a portion of the surface of release layer 404. In some embodiments, the photolithography process includes pretreatment, dry film pressing, exposure, development, etching, film stripping, and the like.

As shown in fig. 3d, the first dielectric layer 100 is formed on the upper surface of the metal layer 410 and within the opening 4102, for example, using a pressing process. After the first dielectric layer 100 is formed, the first dielectric layer is continuously heated. A substrate support (not shown) may then be disposed on the first dielectric layer 100. In some embodiments, the material of the substrate holder comprises stainless steel.

As shown in fig. 3e, a semiconductor die 300 is disposed on the first dielectric layer 100. With the active surface 310 of the semiconductor die 300 facing the first dielectric layer 100. After the semiconductor die 300 is mounted, a bonding process and a baking process are performed, and then a plasma cleaning process is performed. In some embodiments, the semiconductor die 300 may be various active or passive components. The active element may be, for example, various chips (a power management chip, a logic function chip, a memory chip, a communication chip, a microprocessor chip, and a graphic chip). The passive element may be, for example, a capacitive element, a resistive element, an inductive element, or the like.

As shown in fig. 3f, a second dielectric layer 200 is formed on the first dielectric layer 100 and the semiconductor die 300, covering the surface of the first dielectric layer 100 and encasing the semiconductor die 300. In some embodiments, the same material as the first dielectric layer 100 is used for the second dielectric layer 200. Then, the second dielectric layer 200 is subjected to a vacuum lamination process, and then a baking process is performed.

As shown in fig. 3g, a metal-film-clad laminate 435 may be disposed on the second dielectric layer 200 using, for example, a stacking process and a press-fitting process. After the pressing process is performed, the second dielectric layer 200 at the edge may have an overflow phenomenon, and the thickness of the second dielectric layer 200 may be uneven, so that the upper surface of the second dielectric layer 200 is uneven, and the first dielectric layer 100 is already in a semi-cured structure at this time, so that the pressing process does not affect the thickness of the first dielectric layer 100. In some embodiments, the lateral dimension of the metal layer 410 is slightly larger than the lateral dimensions of the first dielectric layer 100 and the second dielectric layer 200 to reserve a space for an overflow glue possibly generated in the second dielectric layer 200, so as to prevent the overflow glue from contacting the release layer 404 and the carrier 402 and causing an abnormality in the subsequent board release (the last step in fig. 3 g). The metal-clad laminate 435 includes a second bonding metal layer 432 bonded to the second dielectric layer 200. In some embodiments, the material of the second bonding metal layer 432 includes copper. In some embodiments, metal-Clad film Laminate 435 is a Copper Clad Laminate (CCL). In the above embodiment, the second bonding metal layer 432 includes the third metal layer 4323 adhered to the surface of the second dielectric layer 200 and the fourth metal layer 4324 located on the third metal layer 4323, the thickness of the third metal layer 4323 is 18 μm, and the thickness of the fourth metal layer 4324 is 5 μm. The release layer 404 and the carrier plate 402 are removed after the metal-clad laminate 435 is disposed.

As shown in fig. 3h, a first through-hole 4104 extending from the upper surface of the metal-film-clad laminate 435 to the lower surface of the metal layer 410 is provided at the edge of the resulting structure of fig. 3 g. First metal layer 412 of metal layer 410 is then removed.

As shown in fig. 3i, the second metal layer 414 is patterned using, for example, a photolithography process. The patterned second metal layer 414 exposes a portion of the surface of the first dielectric layer 100. In some embodiments, the photolithography process includes a process flow of pretreatment, dry film pressing, exposure, secondary exposure, development, etching, and film stripping.

A first opening 4106 is formed through the first and second dielectric layers 100 and 200 at a portion of the surface of the exposed first dielectric layer 100. In some embodiments, the opening size of the first opening 4106 gradually decreases in a direction extending from the first dielectric layer 100 to the second dielectric layer 200. The first opening 4106 extends to the second bonding metal layer 432.

A second opening 4108 is opened in the first dielectric layer 100 to expose the pad 302 of the semiconductor die 300. In some embodiments, the opening size of the second opening 4108 gradually decreases in a direction extending from the lower surface of the first dielectric layer 100 to the upper surface of the first dielectric layer 100. Meanwhile, blind holes 4208 are provided in the first dielectric layer 100 around the first opening 4106. In some embodiments, second apertures 4108 and blind holes 4208 can be formed using a sand blasting process.

As shown in fig. 3i, the same metal material as the second metal layer 414 can be disposed in the surface of the second metal layer 414 and the first opening 4106, the second opening 4108 and the blind via 4208 by, for example, electroplating or electroless plating, and the disposed metal material and the second metal layer 414 form the first bonding metal layer 422 on the first dielectric layer 100. Wherein the metal material completely covers the surface of second metal layer 414, completely fills second opening 4108 and blind via 4208, and covers the bottom and sidewalls of first opening 4106. Thereafter, the third metal layer 4323 of the second bonding metal layer 432 of the metal-film clad laminate 435 remains, and the remainder of the metal-film clad laminate 435 is removed.

As shown in fig. 3j, the first bonding metal layer 422 and the third metal layer 4323 are patterned to form a first via 400 and a second via 500. In some embodiments, the second via 500 may be formed as a solid structure similar to the first via 400 (i.e., the metal material fills the first hole 4106). In some embodiments, a photolithography process may be employed to pattern the first bonding metal layer 422 and the third metal layer 4323. In some embodiments, the photolithography process includes pretreatment, dry film pressing, exposure, development, etching, film stripping, and the like.

As shown in fig. 3k, a third dielectric layer 430 is disposed on the first dielectric layer 100 and the first bonding metal layer 422. The third dielectric layer 430 fills the first opening 4106. A fourth dielectric layer 440 is disposed on second dielectric layer 200 and third metal layer 4323. Thereafter, a first cover metal layer 450 is disposed on the third dielectric layer 430. The first cover metal layer 450 includes a first cover layer 451 attached to the surface of the third dielectric layer 430, and a second cover layer 453 on the first cover layer 451. In some embodiments, the first cladding layer 451 is 5 μm thick. In some embodiments, the thickness of the second cladding layer 453 is 18 μm. In some embodiments, the material of the first cladding layer 451 includes copper. In other embodiments, the first cladding layer 451 may be made of other metal materials. In some embodiments, the first cladding layer 451 and the second cladding layer 453 comprise the same metal material. In other embodiments, the first cladding layer 451 and the second cladding layer 453 comprise different metal materials. A second capping metal layer 460 is disposed on the fourth dielectric layer 440. The second cover metal layer 460 includes a third cover layer 461 attached to the surface of the fourth dielectric layer 440 and a fourth cover layer 463 on the third cover layer 461. In some embodiments, the thickness of the third capping layer 461 is 5 μm. In some embodiments, the thickness of the fourth cover layer 463 is 18 μm. In some embodiments, the material of the third capping layer 461 includes copper. In other embodiments, the third capping layer 461 may be made of other metal materials. In some embodiments, the third cover layer 461 and the fourth cover layer 463 comprise the same metal material. In other embodiments, the third and fourth cladding layers 461, 463 comprise different metal materials. In some embodiments, the third dielectric layer 430, the fourth dielectric layer 440, the first capping metal layer 450, and the second capping metal layer 460 are formed using a lamination process. In some embodiments, the material of the third and fourth dielectric layers 430 and 440 includes polypropylene (PP).

In fig. 3a to 3k, a one-unit structure is illustrated, and in actual production, a plurality of unit structures are formed together, and a singulation process (e.g., dicing) is performed after the step of fig. 3k to form the one-unit structure as shown in the figure.

As shown in fig. 3l, a second through hole 4204 penetrating the structure obtained in fig. 3k is formed. The second through hole 4204 is provided at an edge and is located outside the first through hole 4104.

The second cover layer 453 and the fourth cover layer 463 are removed. The first capping layer 451 is patterned to expose a portion of the surface of the third dielectric layer 430. The third capping layer 461 is patterned to expose a portion of the surface of the fourth dielectric layer 440. In some embodiments, the first and third capping layers 451, 461 may be patterned using a photolithography process. In some embodiments, the photolithography process includes pretreatment, dry film pressing, exposure, development, etching, film stripping, and the like.

As shown in fig. 3m, a third opening 4302 is provided at a surface of the exposed third dielectric layer 430. The third opening 4302 extends to the first bonding metal layer 422. A fourth hole 4306 is disposed at a surface of the exposed fourth dielectric layer 440. The fourth hole 4306 extends to the third metal layer 4323.

As shown in fig. 3n, the same metal material as the first capping layer 451 is disposed on the first capping layer 451 to form a third bonding metal layer 452 covering the third dielectric layer 430. The third bonding metal layer 452 fills the third opening 4302 to electrically connect to the first bonding metal layer 422. The same metal material as the third capping layer 461 is covered on the third capping layer 461 to form a fourth bonding metal layer 462 covering the fourth dielectric layer 440. The fourth bonding metal layer 462 fills the fourth hole 4306 to electrically connect to the third metal layer 4323. In some embodiments, the third bonding metal layer 452 and the fourth bonding metal layer 462 may be formed by electroless plating or electroplating.

The third bonding metal layer 452 is patterned to form the first opening 4402 exposing the surface of the third dielectric layer 430. The fourth bonding metal layer 462 is patterned to form a second opening 4406 exposing a surface of the fourth dielectric layer 440. In some embodiments, the third bonding metal layer 452 and the fourth bonding metal layer 462 may be patterned using a photolithography process. In some embodiments, the photolithography process includes pretreatment, dry film pressing, exposure, development, etching, film stripping, and the like.

As shown in fig. 3o, a first solder mask 470 is disposed on the third bonding metal layer 452 and the first opening 4402. And a second solder resist film 480 is disposed on the fourth bonding metal layer 462 and the second opening 4406. In some embodiments, the material of the first solder mask 470 and the second solder mask 480 may be various solder resists, such as paint-like paint.

The first solder resist film 470 is patterned to expose the surface of the third bonding metal layer 452. And the second solder mask 480 is patterned to expose the surface of the fourth bonding metal layer 462. Then obtain the embedded substrate of the embodiment of the utility model.

In the embodiment of the present invention, the active surface 310 of the semiconductor die 300 faces the first dielectric layer 100, the thickness of the first dielectric layer 100 has a higher uniformity, the thickness difference is below 6 μm, and when the second openings 4108 are formed, for example, by a sand blasting process, the second openings 4108 at different positions can reach a predetermined depth without causing damage to the pads 302 of the semiconductor die 300.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A buried substrate, comprising:

a first dielectric layer;

a second dielectric layer on the first dielectric layer, the first and second dielectric layers having a joint face;

a semiconductor die embedded in the first dielectric layer and the second dielectric layer, a distance between an active surface of the semiconductor die and the bonding surface being less than a distance between a back side of the semiconductor die and the bonding surface.

2. The embedded substrate of claim 1, wherein the active surface of the semiconductor die faces a lower surface of the first dielectric layer, and the back-of-crystal faces an upper surface of the second dielectric layer, the embedded substrate further comprising:

a first via extending from a lower surface of the first dielectric layer to the active surface of the semiconductor die.

3. The buried substrate of claim 1, wherein the active face of the semiconductor die is buried within the first dielectric layer, and a thickness of the semiconductor die within the second dielectric layer is greater than a thickness of the semiconductor die within the first dielectric layer.

4. The buried substrate of claim 3, wherein a thickness of the second dielectric layer is greater than a thickness of the semiconductor die.

5. The buried substrate of claim 3, wherein a thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

6. A buried substrate, comprising:

a first dielectric layer;

a second dielectric layer on the first dielectric layer;

a semiconductor die embedded in the first and second dielectric layers, an active surface of the semiconductor die facing a lower surface of the first dielectric layer, a roughness of the lower surface of the first dielectric layer being less than a roughness of an upper surface of the second dielectric layer.

7. A buried substrate, comprising:

a first dielectric layer;

a second dielectric layer on the first dielectric layer;

a semiconductor die embedded in the first dielectric layer and the second dielectric layer, an active surface of the semiconductor die facing a lower surface of the first dielectric layer, a back surface of the semiconductor die facing an upper surface of the second dielectric layer;

a second via extending from a lower surface of the first dielectric layer to an upper surface of the second dielectric layer and having a lateral dimension that gradually decreases, a distance from a junction surface between the first dielectric layer and the second dielectric layer to the lower surface of the first dielectric layer being smaller than a distance from the junction surface to the upper surface of the second dielectric layer.

8. The buried substrate of claim 7, wherein a lateral dimension of the second via at the junction surface is smaller than a lateral dimension of the second via at a lower surface of the first dielectric layer.

9. The buried substrate of claim 7, wherein a distance between the active surface of the semiconductor die and the junction surface is less than a distance between a back side of the semiconductor die and the junction surface.

10. The buried substrate of claim 7, wherein a pad of the semiconductor die on an active surface is buried within the first dielectric layer, and a remaining portion of the semiconductor die is buried within the second dielectric layer; the second dielectric layer has a thickness greater than a thickness of the semiconductor die.

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