CN217034159U - Novel semiconductor photoelectric device test panel - Google Patents
Novel semiconductor photoelectric device test panel Download PDFInfo
- Publication number
- CN217034159U CN217034159U CN202220271207.2U CN202220271207U CN217034159U CN 217034159 U CN217034159 U CN 217034159U CN 202220271207 U CN202220271207 U CN 202220271207U CN 217034159 U CN217034159 U CN 217034159U
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- 238000012360 testing method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 63
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 27
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000605 extraction Methods 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000005693 optoelectronics Effects 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000005137 deposition process Methods 0.000 abstract description 2
- 238000003466 welding Methods 0.000 abstract 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000006072 paste Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The utility model discloses a novel test board for a semiconductor photoelectric device, which belongs to the technical field of semiconductor photoelectric devices and comprises a test substrate, a silicon dioxide film and a line connecting electrode, wherein the silicon dioxide and the test substrate are subjected to alignment treatment, the silicon dioxide film covers the surface of one side of the test substrate, the line connecting electrode, the test substrate and the silicon dioxide film are mutually aligned, and a P electrode and an N electrode on the test substrate can be set to be at the same height by disconnecting the overlapped part of line electrodes and column electrodes, so that the test substrate is covered by the silicon dioxide film in a large area, the steps of photoetching and film deposition processes during the preparation of the test substrate are reduced, the process is simplified, the manufacture of a welding disc is facilitated, and the reliability of electrode connection is increased.
Description
Technical Field
The utility model relates to the technical field of semiconductor photoelectric devices, in particular to a novel semiconductor photoelectric device test board.
Background
At present, the testing technology of semiconductor photoelectric devices at home and abroad still mainly uses the traditional probe station movable testing equipment, and because the mechanical movable probe station is needed to test a single chip in a wafer when testing the chip of the whole wafer, the mechanical movement efficiency is low, the time consumption is long, the loss of mechanical parts is easily caused, and the alignment deviation of long-time work is also increased.
And the preparation process of the test board needs more process steps of photoetching and film deposition, which is more tedious, and then the manufacture of the bonding pad on the test board has more materials and higher thickness requirement, and meanwhile, the connection of the electrodes lacks reliability due to the inconsistent height of the electrodes.
SUMMERY OF THE UTILITY MODEL
The utility model provides a novel test board for a semiconductor photoelectric device, which solves the problems of complicated manufacturing process of the test board and lack of reliability of electrodes during connection.
In order to achieve the purpose, the utility model provides the following technical scheme: the utility model provides a novel semiconductor photoelectric device surveys test panel, includes test substrate and silica film and line connection electrode, the silica film with the test substrate carries out the alignment and handles, the silica film covers test substrate side surface, line connection electrode with test substrate and silica film are each other aligned and are carved.
Preferably, the surface of the test substrate is provided with an electrode pattern, the electrode pattern comprises a plurality of P electrodes, N electrodes, row outgoing lines, column outgoing lines, row outgoing electrodes and column outgoing electrodes, the row outgoing lines and the column outgoing lines are arranged on the test substrate in a matrix manner, the P electrodes are located on the row outgoing lines, the N electrodes are located on the column outgoing lines, the row outgoing electrodes are located at one ends of the row outgoing lines, and the column outgoing electrodes are located at one ends of the column outgoing lines.
Preferably, the P electrode on the row lead line is disconnected from the N electrode on the column lead line at the overlapping position.
Preferably, be equipped with first hole, second hole, third hole and fourth hole on the silica film respectively, first hole with on the test substrate the P electrode with N electrode position corresponds to each other, the second hole with part on the test substrate the position of line lead-out wire corresponds to each other, the third hole with on the test substrate the position of line lead-out electrode corresponds to each other, the fourth hole is located on the test substrate the position of row lead-out electrode corresponds to each other.
Preferably, the row connecting electrode corresponds to a position where the P electrode and the N electrode are disconnected, and the row connecting electrode is connected to a position where the P electrode and the N electrode are disconnected on the row lead-out line.
Preferably, the height of the P electrode is consistent with that of the N electrode, and a pad is arranged at the P electrode and the N electrode.
Preferably, the pad manufacturing process includes an electroplating process.
Preferably, the pad material comprises a metal having a low resistivity.
Preferably, the metal with low resistivity comprises copper and nickel.
Compared with the prior art, the utility model has the beneficial effects that:
1. in the utility model, the overlapped part of the row electrodes and the column electrodes is disconnected, so that the P electrode and the N electrode on the test substrate can be set to be at the same height, the test substrate is covered by the silicon dioxide film in a large area, namely, the insulating layer is covered on the surface of the test substrate in a large area, the implementation of an electroplating process is convenient, compared with the conventional ball planting process, the metal of the bonding pad can be thicker, the metal with low resistance such as copper, nickel and the like can be selected, the photoetching and film deposition process steps during the preparation of the test substrate are reduced, the process is simplified, the bonding pad is convenient to manufacture, and the reliability of electrode connection is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the principles of the utility model and not to limit the utility model.
In the drawings:
FIG. 1 is a first pattern of a test substrate according to the present invention;
FIG. 2 is a second reticle layout of a test substrate of the present invention;
FIG. 3 is a graph of the present invention formed on a test substrate after the alignment of FIGS. 1 and 2;
FIG. 4 is a third reticle layout of a test substrate of the present invention;
FIG. 5 is a graph of the present invention formed on a test substrate after the alignment of FIGS. 3 and 4;
the reference numbers in the figures: 1. testing the substrate; 2. a P electrode; 3. an N electrode; 41. a line outgoing line; 42. a row extraction electrode; 51. a column outgoing line; 52. a column lead-out electrode; 6. a first hole; 7. a second hole; 8. a third aperture; 9. a fourth aperture; 10. the rows connect the electrodes.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
The embodiment is as follows: as shown in fig. 5, a novel test board for semiconductor optoelectronic devices comprises a test substrate 1, a silicon dioxide film and row connecting electrodes 10, wherein the silicon dioxide film is aligned with the test substrate 1, the silicon dioxide film covers one side surface of the test substrate 1, the row connecting electrodes 10 are aligned with the test substrate 1 and the silicon dioxide film, an electrode pattern is arranged on the surface of the test substrate 1, the electrode pattern comprises a plurality of P electrodes 2, N electrodes 3, row outgoing lines 41, column outgoing lines 51, row outgoing lines 42 and column outgoing lines 52, the row outgoing lines 41 and the column outgoing lines 51 are arranged in a matrix on the test substrate 1, the P electrodes 2 are located on the row outgoing lines 41, the N electrodes 3 are located on the column outgoing lines 51, the P electrodes 2 on the row outgoing lines 41 are disconnected from the overlapping positions of the N electrodes 3 on the column outgoing lines 51, the row extraction electrode 42 is located at one end of the row extraction line 41, the column extraction electrode 52 is located at one end of the column extraction line 51, the silicon dioxide film is respectively provided with a first hole 6, a second hole 7, a third hole 8 and a fourth hole 9, the first hole 6 corresponds to the positions of the P electrode 2 and the N electrode 3 on the test substrate 1, the second hole 7 corresponds to the position of the row extraction line 41 on the test substrate 1, the third hole 8 corresponds to the position of the row extraction electrode 42 on the test substrate 1, the fourth hole 9 is located at the position of the column extraction electrode 52 on the test substrate 1, the row connection electrode 10 corresponds to the position of the disconnection of the P electrode 2 and the N electrode 3, and the row connection electrode 10 connects the position of the disconnection of the P electrode 2 and the N electrode 3 on the row extraction line 41, the P electrode 2 with the 3 highly unanimous of N electrode, because P and 3 highly unanimous of N electrode, the large tracts of land is covered by the insulating layer on the survey test panel, and the electroplating process of being convenient for is implemented, and electroplating compares conventional ball planting technology, enables the pad metal thicker, and electrode connection reliability is higher, just the P electrode 2 with 3 departments of N electrode are equipped with the pad, the pad preparation technology includes the electroplating process, the pad material includes the metal that the resistivity is low, the metal that the resistivity is low includes copper, nickel.
The preparation method comprises the following specific steps:
1. the method comprises the steps of simultaneously manufacturing patterns of a P electrode 2, an N electrode 3, a row outgoing line 41, a row outgoing line 42, a column outgoing line 51 and a column outgoing line 52 on a test substrate 1 in an electron beam evaporation mode, wherein the test substrate 1 can be a glass substrate, a silicon substrate or a sapphire substrate, the electrodes and the outgoing lines can be made of metal such as aluminum, gold, silver, nickel and the like, and the thickness of the metal is 1-2 micrometers, as shown in figure 1. Most of the electrode patterns of the test substrate 1 are prepared at one time and are only cut off at the overlapped positions of the row electrodes and the column electrodes, and compared with the conventional preparation, the P electrode 2 and the N electrode 3 have the same height, so that the manufacture of a bonding pad on the electrode is facilitated.
2. Preparing an insulating layer on the test substrate 1, depositing a silicon dioxide film by adopting a PECVD process, wherein the thickness of the film is 1-2 microns, performing a photoetching process on the silicon dioxide film, and corroding silicon dioxide on the P electrode 2 and the N electrode 3 to form a first hole 6; corroding part of the silicon dioxide on the row lead wires 41 to form second holes 7; corroding off silicon dioxide on the row extraction electrode to form a third hole 8; and etching off the silicon dioxide on the column extraction electrode to form a fourth hole 9. Fig. 2 is a diagram of a second plate photolithography mask, and fig. 3 is a diagram formed on the test substrate 1 after the first plate and the second plate are aligned;
3. and (3) manufacturing the line connection electrode 10 on the test substrate 1 by adopting an electron beam evaporation mode, wherein the material is metal such as aluminum, gold, silver, nickel and the like, and the thickness of the metal is 1-2 microns. Fig. 4 shows the pattern (metal) of the third plate of the test board, and fig. 5 shows the final pattern formed on the test substrate 1 after the third plate is aligned with the first and second plates. The row lead wires 41 of the test substrate 1 are thus connected, a large area of the test substrate 1 is covered by the silicon dioxide insulating layer, and reliability is higher;
when in use, the P electrode 2 and the N electrode 3 on the test substrate 1 are subjected to pad fabrication by an electroplating process, and the pads can be made of tin, silver paste, copper, nickel and the like. Because the height of the P electrode 2 is consistent with that of the N electrode 3, a large area on the test substrate 1 is covered by an insulating layer, the implementation of an electroplating process is convenient, compared with a conventional ball planting process, the electroplating process can enable the metal of a bonding pad to be thicker, the reliability of electrode connection is higher, the metal with low resistance rate such as copper, nickel and the like can be selected, then the semiconductor photoelectric device array attached with the semiconductor is inversely placed on the test substrate 1, the bonding pad is closely connected with the electrode of the test substrate 1, the pixels in the array of the test substrate 1 are subjected to line-row scanning through a conventional peripheral driving circuit, the rapid point-by-point test of the semiconductor chip is realized, the test time of the million-level semiconductor chip is reduced to several minutes from the conventional tens of hours, and the test efficiency is greatly improved.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the utility model. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A novel semiconductor photoelectric device test board is characterized in that: the silicon dioxide film and the test substrate are subjected to alignment treatment, the silicon dioxide film covers the surface of one side of the test substrate, and the line connection electrode is mutually aligned with the test substrate and the silicon dioxide film.
2. A novel test board for semiconductor photovoltaic devices as claimed in claim 1, wherein: the test substrate surface is equipped with the electrode pattern, the electrode pattern includes a plurality of P electrode, N electrode, line outgoing line, row outgoing line, line extraction electrode and row extraction electrode, the line outgoing line with it is in to be the matrix arrangement on the test substrate, the P electrode is located on the line outgoing line, the N electrode is located on the row outgoing line, the line extraction electrode is located line outgoing line one end, it is located to be listed as extraction electrode one end.
3. A novel test board for semiconductor photovoltaic devices as claimed in claim 2, wherein: and the lap joint positions of the P electrodes on the row outgoing lines and the N electrodes on the column outgoing lines are disconnected.
4. A novel test board for semiconductor optoelectronic devices as claimed in claim 3, wherein: be equipped with first hole, second hole, third hole and fourth hole on the silica film respectively, first hole with on the test substrate the P electrode with N electrode position corresponds each other, the second hole with part on the test substrate the position of line lead-out wire corresponds each other, the third hole with on the test substrate the position of line lead-out electrode corresponds each other, the fourth hole is located on the test substrate the position of row lead-out electrode corresponds each other.
5. The novel semiconductor optoelectronic device test board as claimed in claim 4, wherein: the row connecting electrode corresponds to the position of the disconnection position of the P electrode and the N electrode, and the row connecting electrode is connected with the position of the disconnection position of the P electrode and the N electrode on the row lead-out wire.
6. A novel test plate for testing semiconductor photoelectric devices as claimed in claim 2, wherein: the height of the P electrode is consistent with that of the N electrode, and a bonding pad is arranged at the position of the P electrode and the position of the N electrode.
7. The novel semiconductor optoelectronic device test board as claimed in claim 6, wherein: the manufacturing process of the bonding pad comprises an electroplating process.
8. A novel test plate for testing semiconductor photoelectric devices as claimed in claim 7, wherein: the pad material includes a low resistivity metal.
9. A novel test board for semiconductor photovoltaic devices as claimed in claim 8, wherein: the low-resistivity metal comprises copper and nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220271207.2U CN217034159U (en) | 2022-02-10 | 2022-02-10 | Novel semiconductor photoelectric device test panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220271207.2U CN217034159U (en) | 2022-02-10 | 2022-02-10 | Novel semiconductor photoelectric device test panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217034159U true CN217034159U (en) | 2022-07-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220271207.2U Expired - Fee Related CN217034159U (en) | 2022-02-10 | 2022-02-10 | Novel semiconductor photoelectric device test panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217034159U (en) |
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2022
- 2022-02-10 CN CN202220271207.2U patent/CN217034159U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20220722 |
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| CF01 | Termination of patent right due to non-payment of annual fee |