CN216981995U - Circuit for reducing SDI output signal jitter - Google Patents
Circuit for reducing SDI output signal jitter Download PDFInfo
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- CN216981995U CN216981995U CN202122844342.XU CN202122844342U CN216981995U CN 216981995 U CN216981995 U CN 216981995U CN 202122844342 U CN202122844342 U CN 202122844342U CN 216981995 U CN216981995 U CN 216981995U
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Abstract
The utility model provides a circuit for reducing SDI output signal jitter, which is low in SDI output signal jitter and meets the SDI standard requirement. A clock signal output interface of the video processor output circuit is connected with a signal input end of the clock chip through a signal transmission lead, and a terminating circuit is connected on the signal transmission lead; one end of the first pull-up resistor is connected with the positive electrode of the power supply, and the other end of the first pull-up resistor is connected with the signal transmission lead; one end of the first pull-down resistor is connected with the negative electrode of the power supply, and the other end of the first pull-down resistor is connected with the signal transmission lead; one end of the second pull-up resistor is connected with the positive electrode of the power supply, and one end of the second pull-down resistor is connected with the negative electrode of the power supply; the other end of the second pull-up resistor is connected with the other end of the second pull-down resistor and then connected to a clock input port of the clock chip; the filter capacitor is connected with the second pull-down resistor in parallel; and the signal output end of the clock chip is connected with a clock signal receiving interface of the SDI sending circuit.
Description
Technical Field
The utility model relates to a circuit for reducing the jitter of an SDI output signal.
Background
The SDI interface is a serial digital video transmission interface and is divided into: SDI, HD-SDI, 3G-SDI, and the HD-SDI interface is a high definition digital input and output port of a broadcasting stage, where HD denotes high definition signals. Because the SDI interface cannot directly transmit the compressed digital signal, the compressed signal recorded by the digital video recorder, the hard disk, and other devices must be decompressed and output through the SDI interface before entering the SDI system. If decompression and compression are repeated, image quality is reduced and time delay is increased, so that digital video recorders in different formats and digital video recorders in different formats are provided with interfaces for directly transmitting compressed digital signals.
In the fields of broadcasting stations, education recording and broadcasting, video conferencing and the like, the HD-SDI and the 3G-SDI are widely applied and are interface specifications which are transmitted under the signal rate condition of 1.485Gb/s or 1.485/1.001Gb/s, 2.97Gb/s or 2.97/1.001Gb/s according to SMPTE292M and SMPTE 424M. The specification specifies data formats, channel coding schemes, signal specifications for coaxial cable interfaces, connector and cable types, fiber optic interfaces, and the like. The SDI interface uses a coaxial cable as a cable standard, and the effective distance is 100M.
The traditional mode SDI sending circuit is greatly influenced by the quality of a clock signal output by a video processor output circuit, when the quality of the clock signal output by the video processor output circuit is poor and the jitter is large, the jitter of the signal output by the SDI is serious, the requirement of SDI specification cannot be met, and the problems of short transmission distance and poor compatibility of the SDI sending circuit in a system are caused.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome the defects in the prior art and provide the circuit for reducing the jitter of the SDI output signal with reasonable structural design, wherein the SDI output signal has low jitter and meets the requirements of SDI specifications.
The technical scheme adopted by the utility model for solving the problems is as follows: a circuit for reducing jitter in an SDI output signal, comprising a video processor output circuit and an SDI transmit circuit, wherein: the clock jitter optimization circuit comprises a termination circuit, a voltage division circuit and a clock chip; a clock signal output interface of the video processor output circuit is connected with a signal input end of the clock chip through a signal transmission lead, and a termination circuit is connected on the signal transmission lead; the termination circuit comprises a first pull-up resistor and a first pull-down resistor; one end of the first pull-up resistor is connected with the positive electrode of the power supply, and the other end of the first pull-up resistor is connected with the signal transmission lead; one end of the first pull-down resistor is connected with the negative electrode of the power supply, and the other end of the first pull-down resistor is connected with the signal transmission lead; the voltage division circuit comprises a second pull-up resistor, a second pull-down resistor and a filter capacitor; one end of the second pull-up resistor is connected with the positive electrode of the power supply, and one end of the second pull-down resistor is connected with the negative electrode of the power supply; the other end of the second pull-up resistor is connected with the other end of the second pull-down resistor and then connected to a clock input port of the clock chip; the filter capacitor is connected with the second pull-down resistor in parallel; and the signal output end of the clock chip is connected with a clock signal receiving interface of the SDI sending circuit.
The video signal output interface of the video processor output circuit is connected with the video signal receiving interface of the SDI sending circuit.
The utility model also comprises a first impedance matching resistor, wherein one end of the first impedance matching resistor is connected with the signal output end of the clock chip, and the other end of the first impedance matching resistor is connected with the clock signal receiving interface of the SDI sending circuit.
The utility model also comprises a second impedance matching resistor, wherein one end of the second impedance matching resistor is connected with the clock signal output interface of the output circuit of the video processor, and the other end of the second impedance matching resistor is connected with the signal input end of the clock chip.
The clock chip of the utility model has the model number RC 31008A.
The termination circuit is a Thevenin termination circuit.
Compared with the prior art, the utility model has the following advantages and effects: the utility model has the advantages of strong adaptability, low jitter of the SDI output signal, conformity with SDI standard requirements and low cost compared with other circuits, and can output the SDI signal which conforms to the standard under the condition of poor quality of the clock signal output by the output circuit of the video processor.
Drawings
Fig. 1 is a schematic circuit diagram of an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below by way of examples with reference to the accompanying drawings, which are illustrative of the present invention and are not to be construed as limiting the present invention.
The embodiment of the utility model comprises a video processor output circuit 1, a clock jitter optimization circuit and an SDI sending circuit 2.
The video processor output circuit 1 is used for outputting a video signal or a clock signal collected by the camera.
The SDI transmission circuit 2 receives the video signal output from the video processor and the clock signal optimized by the clock jitter optimizing circuit and outputs an SDI signal conforming to the SDI standard.
The video signal output interface of the video processor output circuit 1 is connected with the video signal receiving interface of the SDI transmitting circuit 2.
The clock jitter optimization circuit is used for optimizing the clock signal output by the video processor output circuit 1 and providing the optimized clock signal to the SDI sending circuit 2. The clock jitter optimization circuit comprises a termination circuit, a voltage division circuit, a first impedance matching resistor R5, a second impedance matching resistor R6 and a clock chip 3.
The clock signal output interface of the video processor output circuit 1 is connected with the signal input end of the clock chip 3 through a signal transmission wire, and a termination circuit is connected on the signal transmission wire.
The termination circuit is a David termination circuit which comprises a first pull-up resistor R1 and a first pull-down resistor R2; one end of a first pull-up resistor R1 is connected with a power supply anode VCC, and the other end is connected with a signal transmission wire; one end of the first pull-down resistor R2 is connected with the power supply cathode GND, and the other end is connected with the signal transmission wire. The termination circuit is a clock signal matching circuit, and adopts the Thevenin termination matching principle to terminate the clock signal input from the video processor output circuit 1, so that the clock signal meets the input requirement of the clock chip 3.
The voltage division circuit comprises a second pull-up resistor R3, a second pull-down resistor R4 and a filter capacitor C. One end of a second pull-up resistor R3 is connected with a power supply anode VCC, and one end of a second pull-down resistor R4 is connected with a power supply cathode GND; the other end of the second pull-up resistor R3 is connected to the other end of the second pull-down resistor R4 and then connected to the clock input port of the clock chip 3. The connection and working principle of the second pull-up resistor R3 and the second pull-down resistor R4 are also Thevenin principle. The filter capacitor C is connected in parallel with the second pull-down resistor R4. When the input signal is input in a single end, the voltage division circuit generates a reference voltage, and then the reference voltage is sent to the clock input port of the clock chip 3 for signal matching of the clock chip 3 when the input signal is input in the single end.
One end of the first impedance matching resistor R5 is connected to the signal output end of the clock chip 3, the other end of the first impedance matching resistor R5 is connected to the clock signal receiving interface of the SDI sending circuit 2, i.e. the signal output end of the clock chip 3 is connected to the clock signal receiving interface of the SDI sending circuit 2 through the first impedance matching resistor R5. The first impedance matching resistor R5 is used for impedance matching of the output signal of the clock chip 3.
One end of the second impedance matching resistor R6 is connected to the clock signal output interface of the video processor output circuit 1, and the other end is connected to the signal input terminal of the clock chip 3, that is, the clock signal output interface of the video processor output circuit 1 is connected to the signal input terminal of the clock chip 3 through the second impedance matching resistor R6. The second impedance matching resistor R6 is used for impedance matching of the output signal of the video processor output circuit 1.
The clock chip 3 has model number RC 31008A. The clock chip 3 is mainly used for clock jitter attenuation processing to filter jitter noise of an input clock. When the input noise is large, the input noise can be filtered out completely by using a local high-performance oscillator under the condition that the loop bandwidth of the clock chip 3 is narrow, such as dozens of Hz to hundreds of Hz, and the clock chip 3 outputs a clock signal with the performance superior to that of the reference clock jitter.
In addition, it should be noted that the specific embodiments described in the present specification may be different in the components, the shapes of the components, the names of the components, and the like, and the above described contents are merely illustrative of the structures of the present invention. Equivalent or simple changes in the structure, characteristics and principles of the utility model are included in the protection scope of the patent. Various modifications, additions and substitutions for the specific embodiments described may occur to those skilled in the art without departing from the scope of the utility model as defined in the accompanying claims.
Claims (6)
1. A circuit for reducing jitter in an SDI output signal, comprising a video processor output circuit and an SDI transmit circuit, wherein: the clock jitter optimization circuit comprises a termination circuit, a voltage division circuit and a clock chip; a clock signal output interface of the video processor output circuit is connected with a signal input end of the clock chip through a signal transmission lead, and a termination circuit is connected on the signal transmission lead; the termination circuit comprises a first pull-up resistor and a first pull-down resistor; one end of the first pull-up resistor is connected with the positive electrode of the power supply, and the other end of the first pull-up resistor is connected with the signal transmission lead; one end of the first pull-down resistor is connected with the negative electrode of the power supply, and the other end of the first pull-down resistor is connected with the signal transmission lead; the voltage division circuit comprises a second pull-up resistor, a second pull-down resistor and a filter capacitor; one end of the second pull-up resistor is connected with the positive electrode of the power supply, and one end of the second pull-down resistor is connected with the negative electrode of the power supply; the other end of the second pull-up resistor is connected with the other end of the second pull-down resistor and then connected to a clock input port of the clock chip; the filter capacitor is connected with the second pull-down resistor in parallel; and the signal output end of the clock chip is connected with a clock signal receiving interface of the SDI sending circuit.
2. The circuit of claim 1, wherein: and a video signal output interface of the video processor output circuit is connected with a video signal receiving interface of the SDI sending circuit.
3. The circuitry of claim 1 for reducing SDI output signal jitter, wherein: the clock signal receiving circuit further comprises a first impedance matching resistor, one end of the first impedance matching resistor is connected with the signal output end of the clock chip, and the other end of the first impedance matching resistor is connected with a clock signal receiving interface of the SDI sending circuit.
4. The circuitry of claim 1 for reducing SDI output signal jitter, wherein: one end of the second impedance matching resistor is connected with a clock signal output interface of the video processor output circuit, and the other end of the second impedance matching resistor is connected with a signal input end of the clock chip.
5. The circuitry of claim 1 for reducing SDI output signal jitter, wherein: the model of the clock chip is RC 31008A.
6. The circuit of claim 1, wherein: the terminating circuit is a David terminating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122844342.XU CN216981995U (en) | 2021-11-19 | 2021-11-19 | Circuit for reducing SDI output signal jitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122844342.XU CN216981995U (en) | 2021-11-19 | 2021-11-19 | Circuit for reducing SDI output signal jitter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216981995U true CN216981995U (en) | 2022-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122844342.XU Active CN216981995U (en) | 2021-11-19 | 2021-11-19 | Circuit for reducing SDI output signal jitter |
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|---|---|
| CN (1) | CN216981995U (en) |
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2021
- 2021-11-19 CN CN202122844342.XU patent/CN216981995U/en active Active
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