CN203181107U - Device capable of improving high definition video clock signal jitter - Google Patents
Device capable of improving high definition video clock signal jitter Download PDFInfo
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- CN203181107U CN203181107U CN 201320127508 CN201320127508U CN203181107U CN 203181107 U CN203181107 U CN 203181107U CN 201320127508 CN201320127508 CN 201320127508 CN 201320127508 U CN201320127508 U CN 201320127508U CN 203181107 U CN203181107 U CN 203181107U
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Abstract
The utility model relates to a device capable of improving a high definition video clock signal jitter comprising a high definition camera and a serial digital video generation device. The device is characterized in that a video clock signal jitter removing module is disposed between the high definition camera and the serial digital video generation device, and can be used to receive a video data signal of the high definition camera, and can be used for the correction of the clock jitter. The device is advantageous in that the design is reasonable, and the video clock signal jitter removing module is connected between the high definition camera and the serial digital video generation device, and then the jitter noise of the clock signal can be eliminated by using the video clock signal jitter removing module, therefore the serial digital video generator can be used to acquire the high quality high speed serial data, the error rate of the high speed serial digital signal transmission can be reduced, and the effectiveness and the reliability of the high definition video data transmission can be guaranteed.
Description
Technical field
The utility model belongs to field of video monitoring, and especially a kind of have a device that improves HD video clock signal shake.
Background technology
Along with the increase that people require visual effect, the definition of picture is also constantly improving.The digital high-definition signal has very high message transmission rate, and the message transmission rate of HD-SDI reaches 1.485Gb/s, and the message transmission rate of 3G-SDI reaches 2.97Gb/s.Raising along with data rate, clock is a very crucial part, because in high-speed serial data link, clock jitter can have influence on the data dithering of transmitter, transmission line and receiver, increase the error rate of system transmissions, even cause whole transmission course failure.If the high-speed digital circuit in the observation actual environment, you can find many jitter sources, are a primary pollution source as the noise of Switching Power Supply in the backboard, and switching frequency is generally 100kHz to 1MHz.Switching power supply noise may inject the clock signal circuit, and other dither cycle sources may be the interference from data or clock line, or the intermodulation product on clock line.How eliminating these jittering noises that inject clock signal is to guarantee that the high-definition digital video data-signal is at one of normal important technology that shows of receiving terminal.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, provides having of a kind of reasonable in design, stable performance to improve the device of HD video clock signal shake.
The utility model solves existing technical problem and takes following technical scheme to realize:
A kind of have a device that improves HD video clock signal shake, comprise high-definition camera and serial digital video generator, between high-definition camera and serial digital video generator, connect one and receive the video data signal of high-definition camera and the video clock signal that clock jitter is revised is gone to shake module.
And described high-definition camera and video clock signal go to shake between the module and are connected by flat cable.
And, described video clock signal goes to shake module and is connected and composed by LVDS decoder and clock jitter arrester, this LVDS decoder is converted to digital component signal with the LVDS signal of high-definition camera output, clock signal in the digital component signal is connected on the clock jitter arrester, and the clock signal of this clock jitter arrester output non-jitter is connected to the serial digital video generator; Video data signal in the digital component signal and synchronizing signal are connected to the serial digital video generator.
And, described video clock signal goes to shake module and is made of the clock jitter arrester, the clock signal of high-definition camera output is input to the clock jitter arrester, the non-jitter clock signal of this clock jitter arrester output is connected to the serial digital video generator, and video data signal and the synchronizing signal of high-definition camera output are connected to the serial digital video generator.
And the signal of described serial digital video generator input is 16 digital video data-signals, 1 line synchronizing signal, 1 potential field synchronizing signal and 1 bit clock signal, and described serial digital video is output as serial signal.
Advantage of the present utility model and good effect are:
The utility model is input to video clock signal with clock signal and goes to shake in the module, remove to shake the jittering noise that module is eliminated clock signal by video clock signal, the clock signal that obtains non-jitter is input in the serial digital video generator again, thereby make the serial digital video generator obtain high-quality high-speed serial data, reduce the error rate of high-speed serial digital signal transmission, guaranteed validity and the reliability of whole HD video data-signal transmission.
Description of drawings
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing the utility model embodiment is further described.
A kind of have a device that improves HD video clock signal shake, as shown in Figure 1, comprise high-definition camera, receive the video data signal of high-definition camera and the video clock signal that clock jitter is revised is removed to shake module and serial digital video generator, described high-definition camera goes to shake module with video clock signal and is connected by flat cable, and video clock signal goes to shake module and is connected with the serial digital video generator.Below video clock signal is gone to shake module and the serial digital video generator describes respectively:
According to the difference of high-definition camera video format, the composition that video clock signal goes to shake module has following dual mode:
When high-definition camera collection image information is exported with LVDS, video clock signal goes to shake module and is connected and composed by LVDS decoder and clock jitter arrester, the clock signal of LVDS decoder output is connected with the clock jitter arrester, and the output signal of clock jitter arrester is connected with the serial digital video generator; The data-signal of LVDS decoder output is connected with the serial digital video generator with synchronizing signal.The LVDS decoder can adopt CPLD, also can adopt application-specific integrated circuit (ASIC) such as THC63LVD104C, THC63LVDF84, DS90CR288 etc.The module of going video clock signal to shake is intended to remove earlier clock jitter and carries out and go here and there conversion, its processing procedure is: at first the video data signal with camera acquisition converts parallel digital component signal by many to the LVDS signal, by the clock jitter arrester clock signal in the digital component signal is done dithering process then, be input to that output obtains serial digital signal in the serial digital video generator with the non-jitter clock signal that obtains and other data-signals are parallel.Specifically, the image information of high-definition camera collection is transferred to the serial digital video generator module with 4bitLVDS data and 1bitLVDS clock signal through flat wire, the LVDS decoder that video clock signal goes to shake in the module becomes digital component signal comprising the YCbCr of 16bit the LVDS signal decoding, the line synchronizing signal of 1bit, the field sync signal of 1bit and the clock signal of 1bit, the 1bit clock signal is input to the clock jitter arrester, the 1bit non-jitter clock signal of this clock jitter arrester output is connected to the serial digital video generator, the YCbCr of 16bit, the line synchronizing signal of 1bit, the field sync signal of 1bit is transferred to the serial digital video generator, generates the HD-SDI signal by the serial digital video generator at last.
The YCbCr that comprises 16bit when the video of high-definition camera output, the line synchronizing signal of 1bit, during the digital component mode signal of the field sync signal of 1bit and the clock signal of 1bit, video clock signal goes to shake module and only comprises the clock jitter arrester, the 1bit clock signal of high-definition camera output is input to the clock jitter arrester, the 1bit non-jitter clock signal of this clock jitter arrester output is connected to the serial digital video generator, the YCbCr of the 16bit of high-definition camera output, the line synchronizing signal of 1bit, the field sync signal of 1bit is transferred to the serial digital video generator, generates the HD-SDI signal by the serial digital video generator at last.
The clock jitter arrester is clock cleaning chip, can adopt the SM8020XX family chip of U.S. Micrel company also can adopt the LMK03000 chip of semiconductor company of Texas Instruments, its input be the clock signal that has shake, be output as the clock signal of non-jitter, clock signal frequency, the amplitude characteristic of input and output are constant.
The serial digital video generator adopts GV7600 or the GS1572 chip of Gennum company, the clock signal of the digital component mode signal 16 digital video data-signals of its input, 1 line synchronizing signal, 1 potential field synchronizing signal and 1 non-jitter that obtains after clock jitter removing dynamic model piece is handled, it exports serial signal.
In actual applications, video clock signal goes to shake module and the serial digital video generator can design in same backboard, and the video data signal of video camera output is connected in the backboard by flat gentle cable.
It is emphasized that; embodiment described in the utility model is illustrative; rather than it is determinate; therefore the utility model comprises and is not limited to the embodiment described in the embodiment; every by those skilled in the art according to other execution modes that the technical solution of the utility model draws, belong to the scope of the utility model protection equally.
Claims (5)
1. one kind has the device that improves the shake of HD video clock signal, comprise high-definition camera and serial digital video generator, it is characterized in that: between high-definition camera and serial digital video generator, connect one and receive the video data signal of high-definition camera and the video clock signal that clock jitter is revised is gone to shake module.
2. according to the described a kind of device that improves the shake of HD video clock signal that has of claim 1, it is characterized in that: described high-definition camera and video clock signal go to shake between the module and are connected by flat cable.
3. according to claim 1 or 2 described a kind of devices that improve the shake of HD video clock signal that have, it is characterized in that: described video clock signal goes to shake module and is connected and composed by LVDS decoder and clock jitter arrester, this LVDS decoder is converted to digital component signal with the LVDS signal of high-definition camera output, clock signal in the digital component signal is connected on the clock jitter arrester, and the clock signal of this clock jitter arrester output non-jitter is connected to the serial digital video generator; Video data signal in the digital component signal and synchronizing signal are connected to the serial digital video generator.
4. according to claim 1 or 2 described a kind of devices that improve the shake of HD video clock signal that have, it is characterized in that: described video clock signal goes to shake module and is made of the clock jitter arrester, the clock signal of high-definition camera output is input to the clock jitter arrester, the non-jitter clock signal of this clock jitter arrester output is connected to the serial digital video generator, and video data signal and the synchronizing signal of high-definition camera output are connected to the serial digital video generator.
5. according to the described a kind of device that improves the shake of HD video clock signal that has of claim 1, it is characterized in that: the signal of described serial digital video generator input is 16 digital video data-signals, 1 line synchronizing signal, 1 potential field synchronizing signal and 1 bit clock signal, and described serial digital video is output as serial signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320127508 CN203181107U (en) | 2013-03-20 | 2013-03-20 | Device capable of improving high definition video clock signal jitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320127508 CN203181107U (en) | 2013-03-20 | 2013-03-20 | Device capable of improving high definition video clock signal jitter |
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| Publication Number | Publication Date |
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| CN203181107U true CN203181107U (en) | 2013-09-04 |
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| CN 201320127508 Expired - Fee Related CN203181107U (en) | 2013-03-20 | 2013-03-20 | Device capable of improving high definition video clock signal jitter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831274A (en) * | 2017-11-23 | 2019-05-31 | 杭州海康威视数字技术股份有限公司 | A kind of data transmission method and equipment and receiver |
-
2013
- 2013-03-20 CN CN 201320127508 patent/CN203181107U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109831274A (en) * | 2017-11-23 | 2019-05-31 | 杭州海康威视数字技术股份有限公司 | A kind of data transmission method and equipment and receiver |
| CN109831274B (en) * | 2017-11-23 | 2021-07-20 | 杭州海康威视数字技术股份有限公司 | Data transmission method and equipment and receiver |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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Address after: 300384 in Tianjin Binhai Huayuan Industrial Zone (outer ring) eight Haitai Huake Road No. 6 Patentee after: TIANJIN YAAN TECHNOLOGY Co.,Ltd. Address before: 300384 Tianjin city Nankai District Huayuan Industrial Zone Ziyuan Road No. 8 Patentee before: TIANJIN YAAN TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20200120 Granted publication date: 20130904 |
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Date of cancellation: 20230120 Granted publication date: 20130904 |
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Granted publication date: 20130904 |
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