CN112532978B - High-performance audio and video coding device based on HEVC - Google Patents
High-performance audio and video coding device based on HEVC Download PDFInfo
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Abstract
The invention discloses a high-performance audio and video coding device based on HEVC, and belongs to the technical field of audio and video compression. The video coding device comprises an SDI video interface, a PAL video interface, a CameraLink video interface, an HDMI video interface, an audio interface, a synchronous data output interface, a control interface, a return interface, an FPGA and an HEVC coding core board, wherein the FPGA is used for realizing an SDI preprocessing module, a PAL preprocessing module, a CameraLink preprocessing module, an audio coding module, a control instruction analyzing module, a return framing module and a synchronous data output module. The invention has rich compatible video sources, can realize the transmission of the audio from the compression end to the decompression end, and can realize the audio propaganda application from the decompression end to the compression end, thereby realizing the function of low-delay audio and video transmission.
Description
Technical Field
The invention relates to the technical field of audio and video compression, in particular to a high-performance audio and video coding device based on HEVC, which can be used in an unmanned flight system using fixed bandwidth link transmission.
Background
The HEVC algorithm is a latest generation video compression algorithm, and has higher compression efficiency compared with the h.264 algorithm. In unmanned aerial vehicle systems, link resources are very limited, and the requirements on image quality are increasing. Therefore, the HEVC video coding algorithm has great value when applied to the unmanned aircraft system. Under the same video quality, HEVC can save more link resources than h.264 algorithm, and improve the range and anti-interference of the link. On the other hand, the HEVC algorithm in the traditional monitoring field only focuses on compression ratio and not on delay index. In an unmanned aerial vehicle system, a delay index is a very important assessment factor, and the index influences whether an operator can accurately and quickly position a tracking target. Meanwhile, with the development of technology, more and more video sources are introduced into the unmanned aerial vehicle system to play different roles, and the video encoding device needs to be compatible with the video interfaces.
Therefore, the HEVC audio and video compression method with low time delay and the compression equipment with multiple video interfaces are realized, and the method has a wide application prospect in an unmanned aircraft system.
Disclosure of Invention
In view of this, the invention provides a high-performance audio and video coding device based on HEVC, which can greatly improve the compression ratio, save link resources, realize a lower delay index, and meet the requirements of an unmanned aerial vehicle system on multiple video interfaces.
The purpose of the invention is realized as follows:
a high-performance audio and video coding device based on HEVC comprises an SDI video interface, a PAL video interface, a CameraLink video interface, an HDMI video interface, an audio interface, a synchronous data output interface, a control interface, a return interface, an FPGA and an HEVC coding core board, wherein the FPGA is used for realizing an SDI preprocessing module, a PAL preprocessing module, a CameraLink preprocessing module, an audio coding module, a control instruction analysis module, a return framing module and a synchronous data output module;
the SDI video interface receives standard SDI video data, converts externally input high-speed serial SDI video data into 1 pair of differential clocks and 5 pairs of differential data through an SDI video equalizer and an SDI deserializer, and outputs the differential clocks and the 5 pairs of differential data to an SDI preprocessing module of the FPGA;
the PAL video interface receives external standard PAL video data, converts serial analog signals into parallel digital signals through an analog-to-digital conversion chip and outputs the parallel digital signals to a PAL preprocessing module of the FPGA;
the CameraLink video interface receives the CameraLink digital signals, converts 1 pair of differential clocks and 4 pairs of differential data into 1-bit clock and 28-bit parallel data through the DS90CR286AMTD chip, and outputs the data to the CameraLink preprocessing module of the FPGA;
the HDMI video interface analyzes externally input HDMI video data into 1 pair of differential clock and 3 pair of differential data through the HDMR socket and outputs the differential data to the HEVC coding core board;
the audio interface receives external MIC or Line audio input through a TLV320AIC23BPW audio chip and outputs the external MIC or Line audio input to an audio coding module of the FPGA through an I2S interface;
the synchronous data output interface receives data of a synchronous data output module of the FPGA, and the data is converted into synchronous 422 data for output through an SN65HVD1476DGSR chip;
the control interface receives an external asynchronous 422 control signal, converts the external asynchronous 422 control signal into a single-ended signal through an SN65HVD1476DGSR chip and transmits the single-ended signal to a control instruction analysis module of the FPGA;
the report interface receives a report frame output by a report framing module of the FPGA, and converts the report frame into an asynchronous 422 signal through an SN65HVD1476DGSR chip to output;
an SDI preprocessing module of the FPGA receives an SDI differential signal, converts the SDI differential signal into a single-ended signal, extracts effective video data, frame synchronization information and line synchronization information according to a BT1120 video standard, and forms video data in a YUV420 format; simultaneously detecting the format of SDI video input, and outputting SDI video input format information to a report framing module of the FPGA;
a PAL preprocessing module of the FPGA receives PAL parallel data, extracts effective video data, frame synchronization and line synchronization information according to a BT656 video standard, and forms video data in a YUV420 format; meanwhile, whether the input of the PAL video is normal or not is detected, and the information is output to a report framing module of the FPGA;
a Camera Link preprocessing module of the FPGA receives Camera Link parallel data, extracts effective video data, frame synchronization information and line synchronization information according to a standard Camera Link protocol, and forms YUV420 format video data; meanwhile, whether the CameraLink video input is normal or not is detected, and the information is output to a return framing module of the FPGA;
an audio coding module of the FPGA receives original audio data from an I2S interface, audio compression is realized by using a G.729 standard audio compression algorithm, and the compressed audio data enters a synchronous data output module of the FPGA;
a control instruction analysis module of the FPGA receives a control frame from a 422 chip, wherein the control frame has a fixed frame length and comprises three effective parameters of a fixed frame header 2 byte, a coding code rate, a video coding source and a coding frame rate and a checksum; the control instruction analysis module extracts information of coding code rate, video coding source and coding frame rate according to a frame protocol; according to different video sources, YUV420 data corresponding to SDI, PAL and CameraLink videos are respectively selected and sent to an HEVC coding core board; meanwhile, two parameters of the coding rate and the coding frame rate are sent to an HEVC coding core board;
a reporting framing module of the FPGA acquires an SDI video input format of an SDI preprocessing module, PAL video normality or normality information of the PAL preprocessing module, video input normality or normality information of a CameraLink preprocessing module, current coding rate of an HEVC coding core board, a coding video source, a coding frame rate and normality or normality information of an HEVC code stream, forms a reporting frame according to a reporting frame protocol, and sends the reporting frame to a 422 chip; the fixed frame length of the return frame comprises a 2-byte fixed frame header, the parameter information and a check sum;
a synchronous data output module of the FPGA receives a video code stream compressed by an HEVC coding core board, analyzes the code stream according to a protocol of the code stream, detects whether a frame header of the code stream is correct, whether frame counting of the code stream is continuous, whether check of the code stream is normal, whether a clock of the code stream is abnormal, and sends the information to a report framing module; in addition, the compressed audio data is received and packed together with the video code stream to form a frame with a fixed length, and the frame is sent to a 422 chip;
the HEVC coding core board receives video data of the HDMI chip, video compression is directly performed by an HEVC algorithm according to code rate and frame rate parameters preset in a program, and a compressed code stream is sent to a synchronous data output module of the FPGA through an SPI interface.
Furthermore, the HEVC coding core board is in butt joint with the FPGA bottom board through QSS-050-01-F-D-A connectors on hardware.
Furthermore, the HEVC coding core board receives YUV420 data sent by the FPGA through a DVP interface, receives code rate, frame rate and video coding source parameters sent by the FPGA through a UART interface, adjusts parameters of an HEVC algorithm in real time according to the parameters, realizes real-time compression of SDI, PAL and CameraLink videos, and sends the compressed code stream to a synchronous data output module of the FPGA through an SPI interface; if the HDMI video input exists, the HDMI video source is preferentially selected.
Further, the HEVC algorithm in the HEVC coding core board is specifically implemented as follows: inserting an I block in each frame of image, wherein the height and the width of the I block are adjusted through parameters, the rest part is a P block, the I block adopts an intra-frame compression mode, and the P block adopts a reference frame compression mode; the position of the I block is sequentially moved to the right by the width of one I block in the image frame sequence, and when the I block is moved from the leftmost side of the image frame to the rightmost side of the image frame, the current sequence is a GOP combination.
Compared with the background technology, the invention has the following advantages:
1. the invention can be compatible with rich video sources, supports SDI, HDMI and PAL which are commonly used in the market, and supports a Camera Link interface with a user-defined format, and the audio can realize audio compression and audio decompression, thereby realizing the transmission of the audio from a compression end to a decompression end and the audio shouting application from the decompression end to the compression end.
2. The control report interface used in the invention can select a video compression source in real time, switch parameters such as compression code rate, frame rate and the like, and the reported frame parameters embody the working state of each module in detail, thereby facilitating the positioning and troubleshooting of problems.
3. Furthermore, the compression algorithm adopted by the invention is an HEVC algorithm optimized by low delay, needs the support of a hard core at the bottom layer, selects an AR9201 chip to complete the compression work of the part, and outputs an average and stable code stream without generating large fluctuation due to severe change of scenes. The test shows that for a 1080P30 video source, the end-to-end delay is less than 80ms through the limited bandwidth synchronous data transmission (the compression code rate is the same as the synchronous bandwidth). Such low time delay is particularly useful for the unmanned aerial vehicle or missile-borne field that require high to the time delay index, and lower time delay can help the operative employee better location target.
4. The HEVC algorithm used by the method can improve the compression efficiency by 50% compared with the traditional H.264 algorithm, for the same video quality, the HEVC algorithm used by the method can save the code rate by 30% -50% compared with the H.264 algorithm, and for a 1080P30 video source, the HEVC algorithm used by the method can achieve the video quality of the H.264 algorithm with the code rate of 4 Mbps. Due to the ultrahigh compression ratio, the invention can save more bandwidth resources for the system on the unmanned aerial vehicle or missile load, improve the anti-interference performance and stability of the whole system, and can realize the video compression application with higher resolution.
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FIG. 1 is an electrical schematic block diagram of an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
Referring to fig. 1, a high-performance audio/video coding device based on HEVC includes an SDI video interface, a PAL video interface, a CameraLink video interface, an HDMI video interface, an audio interface, a synchronous data output interface, a control interface, a reporting interface, an FPGA, and an HEVC coding core board, where the FPGA is configured to implement an SDI preprocessing module, a PAL preprocessing module, a CameraLink preprocessing module, an audio coding module, a control instruction parsing module, a reporting framing module, and a synchronous data output module.
Specifically, an SDI video interface receives standard SDI video data, converts externally input high-speed serial SDI video data into 1 pair of differential clocks and 5 pairs of differential data through an SDI video equalizer and an SDI deserializer, and outputs the differential clocks and the 5 pairs of differential data to an SDI preprocessing module of an FPGA;
the PAL video interface receives external standard PAL video data, converts the serial analog signal into parallel digital signal through ADV7180 chip, and outputs to the PAL preprocessing module of FPGA;
the CameraLink video interface receives the CameraLink digital signals, converts 1 pair of differential clocks and 4 pairs of differential data into 1-bit clock and 28-bit parallel data through the DS90CR286AMTD chip, and outputs the data to the CameraLink preprocessing module of the FPGA;
the HDMI video interface analyzes externally input HDMI video data into 1 pair of differential clock and 3 pair of differential data through the HDMR socket and outputs the differential data to the HEVC coding core board;
the audio interface receives external MIC or Line audio input through a TLV320AIC23BPW audio chip and outputs the external MIC or Line audio input to an audio coding module of the FPGA through an I2S interface;
the synchronous data output interface receives data of a synchronous data output module of the FPGA, and the data is converted into synchronous 422 data for output through an SN65HVD1476DGSR chip;
the control interface receives an external asynchronous 422 control signal, and the external asynchronous 422 control signal is converted into a single-ended signal through an SN65HVD1476DGSR chip and is sent to a control instruction analysis module of the FPGA;
the report interface receives a report frame of the FPGA and converts the report frame into an asynchronous 422 signal through an SN65HVD1476DGSR chip to output;
an SDI preprocessing module of the FPGA receives an SDI differential signal, converts the SDI differential signal into a single-ended signal, extracts effective video data, frame synchronization information and line synchronization information according to a BT1120 video standard, and forms video data in a YUV420 format; simultaneously detecting the format of SDI video input, and outputting SDI video input format information to a report framing module of the FPGA;
a PAL preprocessing module of the FPGA receives PAL parallel data, extracts effective video data, frame synchronization and line synchronization information according to a BT656 video standard, and forms video data in a YUV420 format; meanwhile, whether the input of the PAL video is normal or not is detected, and the information is output to a report framing module of the FPGA;
a Camera Link preprocessing module of the FPGA receives Camera Link parallel data, extracts effective video data, frame synchronization information and line synchronization information according to a standard Camera Link protocol, and forms YUV420 format video data; meanwhile, whether the CameraLink video input is normal or not is detected, and the information is output to a return framing module of the FPGA;
an audio coding module of the FPGA receives original audio data from an I2S interface, audio compression is realized by using a G.729 standard audio compression algorithm, and the compressed audio data enters a synchronous data output module of the FPGA;
the control instruction analysis module of the FPGA receives a control frame from the 422 chip, wherein the control frame has a fixed frame length and comprises three effective parameters of a fixed frame header of 2 bytes, a coding rate, a video coding source and a coding frame rate and a checksum. And the control instruction analysis module extracts the information of the coding code rate, the video coding source and the coding frame rate according to the frame protocol. According to different video sources, YUV420 data corresponding to SDI, PAL and CameraLink videos are respectively selected and sent to an HEVC coding core board. Simultaneously sending two parameters of the coding rate and the coding frame rate to an HEVC coding core board;
the report framing module of the FPGA acquires information of an SDI video input format of the SDI preprocessing module, whether a PAL video of the PAL preprocessing module is normal, whether a video input of the CameraLink preprocessing module is normal, a current coding rate of an HEVC coding core board, a coding video source, a coding frame rate and whether an HEVC code stream is normal, forms a report frame according to a report frame protocol, and sends the report frame to a 422 chip. The fixed frame length of the return frame comprises a 2-byte fixed frame header, the parameter information and the checksum. When the coding device has a fault, the position and the reason of the fault can be quickly positioned according to the state return information.
A synchronous data output module of the FPGA receives a video code stream compressed by an HEVC coding core board, analyzes the code stream according to a protocol of the code stream, detects information such as whether a frame header of the code stream is correct, whether frame counting of the code stream is continuous, whether check of the code stream is normal, whether a clock of the code stream is abnormal and the like, and sends the information to a report framing module; and receiving compressed audio data, packaging the audio data and the video code stream together to form a frame with a fixed length, and sending the frame to a 422 chip.
The HEVC coding core board receives video data of the HDMI chip, video compression is directly carried out by adopting an HEVC algorithm according to code rate and frame rate parameters preset in a program, and a compressed code stream is sent to a synchronous data output module of the FPGA through an SPI (serial peripheral interface); the HEVC coding core board is butted with the FPGA bottom board on hardware through a QSS-050-01-F-D-A connector; the HEVC coding core board receives YUV420 data sent by the FPGA through a DVP interface, receives compression parameters such as code rate, frame rate and video coding source sent by the FPGA through a UART interface, adjusts parameters of an HEVC algorithm in real time according to the parameters, realizes real-time compression of SDI, PAL and CameraLink videos, and sends the compressed code stream to a synchronous data output module of the FPGA through an SPI interface; if the HDMI video input exists, the HDMI video source is preferentially selected.
The HEVC algorithm adopted by the HEVC coding core board is optimized with low latency, and does not use the conventional IPPP or IBP reference frame mode. Inserting an I block in each frame of image, wherein the height and the width of the I block can be adjusted through parameters, the rest part is a P block, the I block adopts an intra-frame compression mode, and the P block adopts a reference frame compression mode; the position of the I block is sequentially moved to the right by the width of one I block in the image frame sequence, and when the I block is moved from the leftmost side of the image frame to the rightmost side of the image frame, the current sequence is a GOP combination. The compression mode can ensure that the code stream of each frame of image after compression is average, avoids code stream fluctuation caused by IPPP and IBP modes, and the code stream average can ensure low delay of the image transmission system of the limited bandwidth link, and the delay of the image transmission system can be greatly increased due to the code stream fluctuation.
In this example, the HEVC coding core board may adopt an AR9201 core board, and low-latency HEVC standard video compression is completed based on the AR9201 core board. The device is compatible with SDI, PAL, CameraLink and HDMI video sources, and can switch different compression modes, different compression code rates and different frame rates in real time; the audio coding and the audio decoding can be realized simultaneously; in a link with limited bandwidth, the delay of the whole coding system is very low; the real-time reported state information can accurately track the working state of the current device, and when the coding device works abnormally, the fault reason can be quickly positioned through the state information.
In the device, an SDI video interface, a PAL video interface and a CameraLink video interface respectively receive video data in corresponding formats, convert the video data into differential signals or parallel data and send the differential signals or the parallel data to the FPGA, the FPGA carries out YUV420 format video extraction according to a video source specified in a control instruction, and sends the YUV420 video data and information such as a coding frame rate, a code rate and user data in the control instruction to an AR9201 core board. And the AR9201 core board compresses YUV420 video data into a low-delay HEVC code stream by using a specially designed low-delay algorithm, packages the HEVC code stream into a fixed frame format and outputs the HEVC code stream to the FPGA, and after the FPGA receives the AR9201 code stream, judges the working state of the AR9201 according to the frame header and the frame counting information and outputs the code stream through a 422 interface. The FPGA simultaneously detects the working states of SDI, PAL and CameraLink processing modules, frames all the states and outputs the frames, an audio data interface receives external Mic or Line audio input, the audio input is converted into a digital signal and is sent to the FPGA through an I2S interface, the FPGA compresses the audio by using a G729 algorithm, the audio is output through a 422 synchronous interface after the frames are formed, an HDMI video is directly sent to an AR9201 core board without being converted by the FPGA, the highest low-delay HEVC compression of 4Kp30 can be realized, the compressed code stream is forwarded to the FPGA and is output through the 422 synchronous interface.
The invention has the following brief working principle:
the SDI video interface, the PAL video interface, the CameraLink video interface, the HDMI video interface and the audio input/output interface complete the signal conversion of external audio/video data; the FPGA completes the framing of YUV420 video data, audio encoding and decoding, control instruction analysis, state extraction of each module and framing output; the AR9201 core board completes low-delay HEVC algorithm coding, and the 422 chip completes input and output of synchronous data.
The invention has the following installation structure: the coding device in figure 1 is arranged in a shielding box and placed on an onboard transceiving combination to form the invention.
The whole coding device is functionally divided into the FPGA bottom plate and the HEVC coding core plate, the interface circuit is completed on the FPGA bottom plate, and the HEVC coding work is realized on the HEVC core plate. This approach facilitates problem troubleshooting and troubleshooting. In addition, different projects may have different requirements on the interface, and by adopting the structure form, the structure form has better adaptability to different projects.
In a word, the invention can be compatible with rich video sources, supports SDI, HDMI and PAL which are commonly used in the market, and simultaneously supports a Camera Link interface with a user-defined format, and audio can realize audio compression and audio decompression, thereby realizing transmission of audio from a compression end to a decompression end and audio shouting application from the decompression end to the compression end.
In addition, the invention realizes the low-delay coding scheme of the HEVC algorithm, can realize high-quality video compression of various video sources, simultaneously has extremely low coding and decoding delay and transmission delay and excellent error code resistance, supports the G729 audio compression algorithm, can control and detect the video coding and decoding states in real time, and is suitable for a wireless link transmission system with higher requirements on delay indexes. Compared with the H.264 video compression scheme commonly used at present, the HEVC algorithm greatly improves the compression ratio, saves more link resources, achieves a lower time delay index, and meets the requirement of multiple video interfaces in an unmanned aerial vehicle system.
Claims (4)
1. A high-performance audio and video coding device based on HEVC is characterized by comprising an SDI video interface, a PAL video interface, a CameraLink video interface, an HDMI video interface, an audio interface, a synchronous data output interface, a control interface, a return interface, an FPGA and an HEVC coding core board, wherein the FPGA is used for realizing an SDI preprocessing module, a PAL preprocessing module, a CameraLink preprocessing module, an audio coding module, a control instruction analysis module, a return framing module and a synchronous data output module;
the SDI video interface receives standard SDI video data, converts externally input high-speed serial SDI video data into 1 pair of differential clocks and 5 pairs of differential data through an SDI video equalizer and an SDI deserializer, and outputs the differential clocks and the 5 pairs of differential data to an SDI preprocessing module of the FPGA;
the PAL video interface receives external standard PAL video data, converts serial analog signals into parallel digital signals through an analog-to-digital conversion chip and outputs the parallel digital signals to a PAL preprocessing module of the FPGA;
the CameraLink video interface receives the CameraLink digital signals, converts 1 pair of differential clocks and 4 pairs of differential data into 1-bit clock and 28-bit parallel data through the DS90CR286AMTD chip, and outputs the data to the CameraLink preprocessing module of the FPGA;
the HDMI video interface analyzes externally input HDMI video data into 1 pair of differential clock and 3 pair of differential data through the HDMR socket and outputs the differential data to the HEVC coding core board;
the audio interface receives external MIC or Line audio input through a TLV320AIC23BPW audio chip and outputs the external MIC or Line audio input to an audio coding module of the FPGA through an I2S interface;
the synchronous data output interface receives data of a synchronous data output module of the FPGA, and the data is converted into synchronous 422 data for output through an SN65HVD1476DGSR chip;
the control interface receives an external asynchronous 422 control signal, converts the external asynchronous 422 control signal into a single-ended signal through an SN65HVD1476DGSR chip and transmits the single-ended signal to a control instruction analysis module of the FPGA;
the report interface receives a report frame output by a report framing module of the FPGA, and converts the report frame into an asynchronous 422 signal through an SN65HVD1476DGSR chip to output;
an SDI preprocessing module of the FPGA receives an SDI differential signal, converts the SDI differential signal into a single-ended signal, extracts effective video data, frame synchronization information and line synchronization information according to a BT1120 video standard, and forms video data in a YUV420 format; simultaneously detecting the format of SDI video input, and outputting SDI video input format information to a report framing module of the FPGA;
a PAL preprocessing module of the FPGA receives PAL parallel data, extracts effective video data, frame synchronization and line synchronization information according to a BT656 video standard, and forms video data in a YUV420 format; meanwhile, whether the input of the PAL video is normal or not is detected, and the information is output to a report framing module of the FPGA;
a Camera Link preprocessing module of the FPGA receives Camera Link parallel data, extracts effective video data, frame synchronization information and line synchronization information according to a standard Camera Link protocol, and forms YUV420 format video data; meanwhile, whether the CameraLink video input is normal or not is detected, and the information is output to a return framing module of the FPGA;
an audio coding module of the FPGA receives original audio data from an I2S interface, audio compression is realized by using a G.729 standard audio compression algorithm, and the compressed audio data enters a synchronous data output module of the FPGA;
a control instruction analysis module of the FPGA receives a control frame from a 422 chip, wherein the control frame has a fixed frame length and comprises three effective parameters of a fixed frame header 2 byte, a coding code rate, a video coding source and a coding frame rate and a checksum; the control instruction analysis module extracts information of coding code rate, video coding source and coding frame rate according to a frame protocol; according to different video sources, YUV420 data corresponding to SDI, PAL and CameraLink videos are respectively selected and sent to an HEVC coding core board; meanwhile, two parameters of the coding rate and the coding frame rate are sent to an HEVC coding core board;
a reporting framing module of the FPGA acquires an SDI video input format of an SDI preprocessing module, PAL video normality or normality information of the PAL preprocessing module, video input normality or normality information of a CameraLink preprocessing module, current coding rate of an HEVC coding core board, a coding video source, a coding frame rate and normality or normality information of an HEVC code stream, forms a reporting frame according to a reporting frame protocol, and sends the reporting frame to a 422 chip; the fixed frame length of the return frame comprises a 2-byte fixed frame header, the parameter information and a check sum;
a synchronous data output module of the FPGA receives a video code stream compressed by an HEVC coding core board, analyzes the code stream according to a protocol of the code stream, detects whether a frame header of the code stream is correct, whether frame counting of the code stream is continuous, whether check of the code stream is normal, whether a clock of the code stream is abnormal, and sends the information to a report framing module; in addition, the compressed audio data is received and packed together with the video code stream to form a frame with a fixed length, and the frame is sent to a 422 chip;
the HEVC coding core board receives video data of the HDMI chip, video compression is directly performed by an HEVC algorithm according to code rate and frame rate parameters preset in a program, and a compressed code stream is sent to a synchronous data output module of the FPGA through an SPI interface.
2. The high-performance audio-video coding device based on HEVC as claimed in claim 1, wherein the HEVC coding core board is interfaced with the FPGA backplane via QSS-050-01-F-D-a connectors in hardware.
3. The high-performance audio/video coding device based on HEVC as claimed in claim 2, wherein the HEVC coding core board receives YUV420 data sent by FPGA through DVP interface, receives bitrate, frame rate, video coding source parameters sent by FPGA through UART interface, adjusts parameters of HEVC algorithm in real time according to these parameters, realizes real-time compression of SDI, PAL, CameraLink video, and sends the compressed code stream to the synchronous data output module of FPGA through SPI interface; if there is an HDMI video input, an HDMI video source is selected.
4. The high-performance HEVC-based audio-video coding device according to claim 1, wherein HEVC algorithm in the HEVC coding core board is specifically implemented as follows: inserting an I block in each frame of image, wherein the height and the width of the I block are adjusted through parameters, the rest part is a P block, the I block adopts an intra-frame compression mode, and the P block adopts a reference frame compression mode; the position of the I block is sequentially moved to the right by the width of one I block in the image frame sequence, and when the I block is moved from the leftmost side of the image frame to the rightmost side of the image frame, the current sequence is a GOP combination.
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