CN216928561U - Power semiconductor device packaging structure - Google Patents

Abstract

The embodiment of the application discloses power semiconductor device packaging structure includes: the heat dissipation device comprises a power chip, a first heat conduction plate, a first base plate and a first base plate, wherein the size of the first heat conduction plate is larger than that of the power chip, the first heat conduction plate conducts transverse heat conduction and longitudinal heat conduction on heat generated by the power chip, the heat transferred into the first heat conduction plate is distributed in the whole first heat conduction plate, a heat dissipation path of the power chip for generating heat is the first heat conduction plate-the first base plate, and meanwhile the cross-sectional area of a channel when the heat flows through the first base plate and the first base plate is the area of one side of the first heat conduction plate, which is in contact with the first base plate. Compared with the existing packaging structure, the size of the first heat conducting plate is larger than that of the power chip, so that the cross-sectional area of a heat flow channel is increased, and junction-shell thermal resistance is further reduced, and the packaging structure has smaller junction-shell thermal resistance.

Description

Power semiconductor device packaging structure

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a power semiconductor device packaging structure.

Background

In various power systems, such as automobile motor drivers, dc buck-boost systems, photovoltaic inverter systems, etc., various power semiconductor devices are widely used.

In general, in order to facilitate the assembly of a power semiconductor device with various power systems, the power semiconductor device needs to be packaged into a package structure when used. However, for the packaging structure of the power semiconductor device, junction-shell thermal resistance (thermal resistance between a power chip and a bottom plate in the power semiconductor device) is one of important indexes for measuring the packaging quality of the power semiconductor device, and the lower junction-shell thermal resistance can improve the heat dissipation performance of the packaging structure, effectively reduce the working temperature of the power semiconductor device, avoid the damage of the power chip due to overhigh temperature, improve the reliability of the power chip, and further improve the reliability of the packaging structure. Therefore, it is an important research of those skilled in the art to provide a power semiconductor device package structure with low junction-to-case thermal resistance.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, embodiments of the present application provide a package structure of a power semiconductor device, where the package structure has a low junction-to-case thermal resistance.

In order to solve the above problem, the embodiment of the present application provides the following technical solutions:

a power semiconductor device package structure, comprising:

a power chip;

a first heat-conducting plate covering the first surface of the power chip, the first heat-conducting plate having a size larger than that of the power chip;

the first substrate covers one side, away from the first surface of the power chip, of the first heat conducting plate;

the first base plate covers one side, away from the first surface of the power chip, of the first substrate;

wherein, first heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the first heat-conducting plate is whole in the first heat-conducting plate, just first heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order first heat-conducting plate first base plate first bottom plate transmission.

Optionally, the transverse equivalent thermal conductivity of the first heat conducting plate is higher than 1000W/m · K.

Optionally, the first heat conducting plate is a soaking plate or a heat pipe.

Optionally, the power chip module further comprises a pressure head, wherein a groove matched with the power chip in shape is formed in the pressure head, the power chip is embedded in the groove, and the pressure head covers an area, except for the area where the power chip is, in the surface of one side, where the first heat conduction plate is connected with the power chip.

Optionally, the method further includes: the second heat conducting plate, the second substrate and the second bottom plate;

the second heat conducting plate covers the second surface of the power chip, the second substrate covers one side of the second heat conducting plate, which is far away from the second surface of the power chip, the second bottom plate covers one side of the second substrate, which is far away from the second surface of the power chip, the second heat conducting plate is a soaking plate or a heat pipe, the size of the second heat conducting plate is larger than that of the power chip, and the second surface of the power chip is opposite to the first surface of the power chip;

wherein, the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate.

Optionally, the method further includes: the second heat conducting plate, the second substrate, the second bottom plate and the metal lead;

the second surface of the power chip is provided with a first connecting point, one side surface of the first substrate, which is connected with the first heat conducting plate, is provided with a second connecting point, the first connecting point is connected with the second connecting point through the metal lead, so that the power chip is connected with the first substrate through the metal lead, the second heat conducting plate covers the area of the second surface of the power chip except the preset area, the second substrate covers one side of the second heat conducting plate, which deviates from the second surface of the power chip, the second bottom plate covers one side of the second substrate, which deviates from the second surface of the power chip, the second heat conducting plate is a soaking plate or a heat pipe, the size of the second heat conducting plate is larger than that of the power chip, the size of the first substrate is larger than that of the first heat conducting plate, and the second surface of the power chip is opposite to the first surface of the power chip, the preset area is an area where the first connecting point is located, and space is provided for connecting the power chip and the first substrate;

wherein, the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate is realized

Optionally, the method further includes: the second heat conducting plate, the second substrate, the second bottom plate, the metal lead and the gasket;

the second surface of the power chip is provided with a first connecting point, one side surface of the first substrate, which is connected with the first heat conducting plate, is provided with a second connecting point, the first connecting point is connected with the second connecting point through the metal lead, so that the power chip is connected with the first substrate through the metal lead, the gasket is positioned in the area of the second surface of the power chip except the preset area, the second heat conducting plate covers one side of the gasket, which deviates from the second surface of the power chip, of the gasket, the second substrate covers one side of the second heat conducting plate, which deviates from the second surface of the power chip, the second bottom plate covers one side of the second substrate, which deviates from the second surface of the power chip, the second heat conducting plate is a soaking plate or a heat pipe, the size of the second heat conducting plate is larger than the size of the power chip, and the size of the first substrate is larger than the size of the first heat conducting plate, the first surface of the power chip is opposite to the second surface of the power chip, and the preset area is an area where the first connecting point is located and provides a space for connecting the power chip and the first substrate;

the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate.

Optionally, the power chip includes a plurality of sub-chips, and the sub-chips are located on the same first heat-conducting plate, and a side surface of the sub-chips connected to the first heat-conducting plate is coplanar.

Optionally, the method further includes: the plastic package structure comprises a plastic package body and an external shell, wherein the plastic package body wraps all parts in the package structure, and the package structure is located in the external shell.

Compared with the prior art, the technical scheme has the following advantages:

the technical scheme provided by the embodiment of the application comprises the following steps: power chip, first heat-conducting plate, first base plate, first bottom plate, the size of first heat-conducting plate is greater than the size of power chip, and first heat-conducting plate covers the power chip first surface, first base plate covers first heat-conducting plate deviates from one side of power chip first surface, first bottom plate covers first base plate deviates from one side of power chip first surface. Wherein, the first heat conducting plate conducts heat transversely to the heat generated by the power chip, so that the heat transferred to the first heat conducting plate is distributed in the whole first heat conducting plate, and the first heat conducting plate conducts heat longitudinally to the heat generated by the power chip, so that the heat generated by the power chip is transferred through the first heat conducting plate, the first substrate and the first bottom plate in sequence, and the heat transferred to the first heat conducting plate can be transferred to the first bottom plate through the first substrate and dissipated through the first bottom plate, i.e. the heat dissipation path of the heat generated by the power chip is the first heat conducting plate-the first substrate-the first bottom plate, so that the power chip does not directly contact with the first substrate to transfer heat, but sequentially passes through the first heat conducting plate, the first substrate and the first bottom plate to transfer heat, and the heat transferred to the first heat-conducting plate is distributed in the whole first heat-conducting plate, so that the channel cross-sectional area when the heat flows through the first substrate and the first base plate is the area of the first heat-conducting plate in contact with the first substrate, i.e. the channel cross-sectional area when the heat flows through the first substrate and the first base plate is the area of the side of the first heat-conducting plate in contact with the first substrate.

Since the size of the first heat conducting plate is larger than that of the power chip, compared with the existing package structure, the package structure provided in the embodiment of the present application increases the channel cross-sectional area of the heat generated by the power chip when the heat flows through the first substrate and the first bottom plate, that is, the heat flow channel cross-sectional area is increased, and the thickness of the first heat conducting plate is thinner, and the first heat conducting plate further has a longitudinal heat dissipation capability, so that even if a heat dissipation path is increased, the junction-shell of the package structure is not greatly affected, and thus the junction-shell thermal resistance can be reduced under the condition that the heat flow channel cross-sectional area is increased, so that the package structure has a smaller junction-shell thermal resistance, which is beneficial to ensuring the operational reliability of the package structure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another power semiconductor device package structure provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a further power semiconductor device package structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another power semiconductor device package structure provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for the sake of illustration, and the drawings are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background section, it has become a focus of research for those skilled in the art to provide a power semiconductor device package structure with a low junction-to-case thermal resistance.

For the packaging structure of the power semiconductor device, the junction-shell thermal resistance is one of important indexes for measuring the packaging quality of the packaging structure, and the lower junction-shell thermal resistance is helpful for ensuring the reliability of the packaging structure.

The reduction of the junction-shell thermal resistance of the packaging structure is mainly realized by improving the packaging structure, packaging materials, packaging processes and the like, for example, a heat-conducting glue with lower heat conductivity coefficient is prevented from being introduced into a heat transmission path, an aluminum nitride substrate with higher heat conductivity coefficient is used for replacing an aluminum oxide substrate, and a silver sintering process with higher heat conductivity coefficient is used for replacing alloy solder so that the power chip is connected with the substrate and the substrate is connected with the bottom plate. It should be noted that the heat of the power semiconductor device is mainly concentrated on the power chip, and the junction-shell thermal resistance of the package structure is related to the cross-sectional area of the thermal flow channel, and the larger the cross-sectional area of the thermal flow channel is, the smaller the corresponding junction-shell thermal resistance is, wherein the cross-sectional area of the thermal flow channel is the cross-sectional area of the channel when the heat generated by the power chip passes through the substrate, the bottom plate, and the like. In the existing packaging structure, a power chip is connected with a substrate, so that heat generated by the power chip can directly flow into the substrate, then flow into a bottom plate through the substrate and be dissipated, the cross-sectional area of a thermal flow channel is the area of the power chip in contact with the substrate, namely the area of the power chip, and the cross-sectional area of the thermal flow channel is related to the area of the power chip in contact with the substrate.

Therefore, although the heat conductivity coefficient of the packaging structure is improved to a certain extent by the packaging structure, for the manufactured power semiconductor device, the size of the power chip is determined, so that the cross-sectional area of a heat flow channel for heat dissipation of the packaging structure is determined, the junction-shell thermal resistance is limited by the cross-sectional area of the heat flow channel, and the junction-shell thermal resistance cannot be effectively reduced. And, for the package structure with increased substrate and bottom board area, the junction-shell thermal resistance can not be effectively reduced similarly.

In addition, with the miniaturization of semiconductor devices, the size of power chips is getting smaller, for example, power chips formed by using the third generation semiconductor have an area which is only 20% of that of the conventional silicon-based power chip or even lower under the condition of the same power, and in this case, the cross-sectional area of a thermal flow channel is smaller, so that the junction-shell thermal resistance of the package structure is larger, and the influence on the reliability of the package structure is larger.

Based on the above research, an embodiment of the present application provides a package structure of a power semiconductor device, as shown in fig. 1, the package structure includes:

a power chip 10;

the first heat conduction plate 21 is connected with the first surface of the power chip 10 and covers the first surface of the power chip 10; it should be noted that, the size of the first heat conducting plate 21 is larger than the size of the power chip 10, which means that the size of a plane parallel to the first surface of the power chip 10 of the first heat conducting plate 21 is larger than the size of the first surface of the power chip 10; it should be further noted that the first heat conducting plate 21 is connected to the first surface of the power chip 10 by solder paste reflow or nano-silver sintering, but this is not limited in the embodiment of the present application, and is determined as the case may be;

a first substrate 31, wherein the first substrate 31 is connected to a side of the first heat conducting plate 21 away from the first surface of the power chip 10, covers a side of the first heat conducting plate 21 away from the first surface of the power chip 10, and generally the size of the first substrate 31 is larger than that of the first heat conducting plate 21; the first substrate 31 and the first heat conducting plate 21 are connected by solder paste reflow or nano-silver sintering, but this is not limited in the embodiment of the present application, and is determined as the case may be;

and a first bottom plate 41, wherein the first bottom plate 41 is connected to a side of the first substrate 31 away from the first surface of the power chip 10, and covers a side of the first substrate 31 away from the first surface of the power chip 10, and generally, the size of the first bottom plate 41 is equal to or larger than the size of the first substrate 31. It should be noted that the first substrate 31 and the first base plate 41 can transfer heat generated by the power chip 10, and release the heat generated by the power chip 10 through the first base plate 41 to dissipate heat, so in this embodiment of the application, the first substrate 31 is a double-sided metal-coated ceramic substrate with a high thermal conductivity coefficient, such as an aluminum oxide copper-clad plate, an aluminum nitride copper-clad plate, and the like, and the first base plate 41 is a metal base plate. It should be noted that, the first base plate 41 and the first substrate 31 are connected by solder paste reflow or nano silver sintering, but this is not limited in this embodiment of the application, and is determined as the case may be;

the first heat conduction plate 21 conducts heat transversely to the heat generated by the power chip 10, so that the heat transferred to the first heat conduction plate 21 is distributed in the whole first heat conduction plate 21, and the first heat conduction plate 21 conducts heat longitudinally to the heat generated by the power chip 10, so that the heat generated by the power chip 10 is transferred sequentially through the first heat conduction plate 21, the first substrate 31 and the first base plate 41; when the heat generated by the power chip 10 is transferred to the first heat conduction plate 21, the temperature of the area of the first heat conduction plate 21 opposite to the power chip 10 is higher, and the temperature of the area far away from the power chip 10 is gradually and slightly reduced; it should be noted that, the above-mentioned "performing transverse heat conduction on the heat generated by the power chip 10 to realize that the heat transferred to the first heat conducting plate 21 is distributed in the whole first heat conducting plate 21" does not mean that the heat generated by the power chip 10 is transferred to the first heat conducting plate 21 completely, but means that the heat generated by the power chip 10 can be transferred to the first heat conducting plate 21, and specifically how much heat generated by the power chip 10 can be transferred to the first heat conducting plate 21 depends on the performance of the first heat conducting plate 21 itself.

Specifically, in the embodiment of the present application, the package structure includes the first heat conduction plate 21, and the first heat conduction plate 21 conducts the heat generated by the power chip 10 transversely, so as to transfer the heat generated by the power chip 10 to the first heat conduction plate 21, and make the heat transferred to the first heat conduction plate 21 be distributed in the whole first heat conduction plate 21, that is, distributed in the whole first heat conduction plate 21. And the first heat conducting plate 21 also conducts heat longitudinally to the heat generated by the power chip 10, so that the heat generated by the power chip 10 is transferred 41 sequentially through the first heat conducting plate 21, the first substrate 31 and the first base plate, that is, the first heat conducting plate 21 has both transverse heat conducting capability and longitudinal heat conducting capability, so that the heat transferred to the first heat conducting plate 21 is distributed in the whole first heat conducting plate 21, and the energy generated by the power chip 10 can be transferred to the first substrate 31 through the first heat conducting plate 21, then transferred to the first base plate 41 and dissipated through the first base plate 41, so that the heat dissipation path of the heat generated by the power chip 10 is the first heat conducting plate 21-the first substrate 31-the first base plate 41, and thus the power chip 10 does not directly contact with the first substrate 31 to transfer heat, but is transferred into the first substrate 31 through the first heat conductive plate 21.

It is known that the energy transferred to the first heat-conductive plate 21 is distributed throughout the first heat-conductive plate 21 so that the passage sectional area of the heat when passing through the first substrate 31 and the first base plate 41 is the area where the first heat-conductive plate 21 is in contact with the first substrate 31. Since the size of the first substrate 31 is generally relatively large and larger than that of the first heat conduction plate 21, the cross-sectional area of the passage when heat flows through the first substrate 31 and the first bottom plate 41 is the area of the side of the first heat conduction plate 21 in contact with the first substrate 31. Since the size of the first heat conducting plate 21 is larger than that of the power chip 10, compared with the existing package structure, the package structure provided in the embodiment of the present application increases the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the first substrate 31 and the first bottom plate 41, that is, the cross-sectional area of the heat flow channel is increased. It should be noted that the heat dissipation path of the power chip 10 in the package structure provided by the embodiment of the present application is the first heat conduction plate 21, the first substrate 31, and the first bottom plate 41, and the heat dissipation path of the power chip 10 in the existing package structure is the substrate-bottom plate, so that the heat dissipation path of the package structure provided by the present application is increased, but due to the size of the device of the package structure, the thicknesses of the components are usually thinner, and further the thickness of the first heat conduction plate 21 is thinner, the first heat conduction plate 21 further has a longitudinal heat dissipation capability, so that even if the heat dissipation path is increased, the junction-shell thermal resistance of the package structure is not greatly affected, so that the package structure can reduce the junction-shell thermal resistance of the package structure under the condition of increasing the cross-sectional area of the heat flow channel, so that the package structure has a smaller junction-shell thermal resistance, the work reliability of the packaging structure is guaranteed. On the basis of the above embodiment, in a specific embodiment of the present application, the size of the power chip 10 of the package structure is 4mm × 4mm, the size of the first substrate 31 is 30mm × 30mm, the thickness is 1.4mm, the size of the first bottom plate 41 is 30mm × 30mm, the thickness is 2mm, the size of the first heat conduction plate 21 is larger than the size of the power chip 10 and slightly smaller than the size of the first substrate 31, and the junction-shell thermal resistance reduction effect of the package structure is simulated by a finite element modeling method. The results show that although the length of the heat dissipation path of the power chip 10 generating heat is increased compared to the existing package structure, the junction-shell thermal resistance of the package structure is reduced by more than 80%, which indicates that the package structure effectively reduces the junction-shell thermal resistance.

On the basis of the above embodiment, in an embodiment of the present application, the lateral equivalent thermal conductivity of the first heat conducting plate 21 is higher than 1000W/m · K, for example, the lateral equivalent thermal conductivity of the first heat conducting plate 21 is 10000W/m · K, so that the first heat conducting plate 21 has a strong plane heat conduction capability to transfer the heat generated by the power chip 10 to the first heat conducting plate 21, and to make the heat transferred to the first heat conducting plate 21 distributed in the whole first heat conducting plate 21, and distributed as uniformly as possible in the whole first heat conducting plate 21.

Optionally, in an embodiment of the present application, the first heat conducting plate 21 is a heat spreader or a heat pipe, but the embodiment of the present application does not limit this, as the case may be. The material of the soaking plate may be copper or aluminum, but when the material of the soaking plate is other than copper, the soaking plate needs to have chip mounting manufacturability through a surface plating method or the like, so as to enable the power chip 10 to be connected with the soaking plate. For example, the soaking plate is made of aluminum, and when the chip mounting process is solder reflow, the surface of the soaking plate needs to be plated with copper, nickel, tin and the like. For example, the material of the soaking plate is aluminum, and when the chip mounting process is nano silver sintering, copper plating, silver plating and the like are needed on the surface of the soaking plate.

It should be noted that, in the manufacturing process of the package structure, when the power chip 10, the first heat conduction plate 21, the first substrate 31 and the first bottom plate 41 are connected, the package structure is heated, so that the refrigerant inside the first heat conduction plate 21 is heated, gasified, expanded and the like, and the first heat conduction plate 21 generates a large stress, and the stress acts on the power chip 10 and the first substrate 31, which easily causes the deformation of the power chip 10 and the first substrate 31, and further causes the damage of the package structure. Therefore, on the basis of the above embodiments, in an embodiment of the present application, the first heat conducting plate 21 is made of a material with high structural rigidity, which ensures that it will not deform at a high process temperature, such as copper, so as to avoid damage to the package structure. It should be noted that sometimes, the first heat conducting plate 21 of the package structure cannot adopt a material with high rigidity due to the limitation of the application environment, and in order to ensure the reliability of the package structure, it is necessary to counteract the stress generated by the first heat conducting plate 21 due to heat. Therefore, in another embodiment of the present application, as shown in fig. 2, the package structure further includes a pressure head 50, a groove matched with the shape of the power chip 10 is formed on the pressure head 50, the power chip 10 is embedded in the groove, and the pressure head 50 covers an area of the first heat conducting plate 21, except for an area where the power chip 10 is located, on a side surface where the power chip 10 is connected to the first heat conducting plate 10, so that the pressure head 50 can counteract stress generated by the first heat conducting plate 21 due to vaporization and expansion of a refrigerant caused by heating, and damage to the package structure is avoided. It should be noted that the pressing head 50 does not always press against the first heat conduction plate 21, but exists when the power chip 10, the first heat conduction plate 21, the first substrate 31 and the first base plate 41 are heated to contact each other, so as to counteract stress generated by vaporization, expansion and the like of a refrigerant in the process of the first heat conduction plate 21.

To further reduce the junction-to-case thermal resistance of the package structure, in one embodiment of the application, as shown in fig. 3, the package structure further comprises: a second heat conducting plate 22, a second substrate 32 and a second substrate 32, wherein the second heat conducting plate 22 covers the second surface of the power chip 10, the second heat conducting plate 22 is a soaking plate or a heat pipe, the size of the second heat conducting plate 22 is larger than that of the power chip 10, the size of the first substrate 31 is larger than that of the first heat conducting plate 21, the size of the second substrate 32 is generally larger than that of the second heat conducting plate 22, and the size of the second bottom plate 42 is larger than or equal to that of the second substrate 32; the second surface of the power chip 10 is opposite to the first surface of the power chip 10, the second substrate 32 covers one side of the second heat-conducting plate 22 departing from the second surface of the power chip 10, that is, the second substrate 32 is connected to one side of the second heat-conducting plate 22 departing from the second surface of the power chip 10, and the second base plate 42 covers one side of the second substrate 32 departing from the second surface of the power chip 10, that is, the second base plate 42 is connected to one side of the second substrate 32 departing from the second surface of the power chip 10. Wherein the second heat conduction plate 22 conducts heat transversely to the heat generated by the power chip 10, transfers part of the heat generated by the power chip 10 to the second heat conduction plate 22, and realizes that the heat transferred to the second heat conduction plate 22 is distributed in the whole second heat conduction plate 22, and the second heat conduction plate 22 conducts heat longitudinally to the heat generated by the power chip 10, realizes that the heat generated by the power chip 10 is transferred sequentially through the second heat conduction plate 22, the second substrate 32 and the second base plate 42, so that the second heat conduction plate 22 has both transverse heat conduction capability and longitudinal heat conduction capability, so that the heat transferred to the second heat conduction plate 22 is distributed in the whole second heat conduction plate 22, and also allows the heat transferred to the second heat conduction plate 22 to be transferred to the second substrate 32 through the second heat conduction plate 22, then transferred to the second base plate 42 and dissipated through the second base plate 42, so that the heat dissipation path of the power chip 10 generating heat further includes the second heat conduction plate 22, the second substrate 32 and the second base plate 42, and the package structure is a double-sided heat dissipation package structure.

In the embodiment of the present application, the size of the second heat conducting plate 22 is larger than the size of the power chip 10, the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the second substrate 32 and the second bottom plate 42 is the area of the side of the second heat conducting plate 22 contacting with the second substrate 32, so that the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the second substrate 32 and the second bottom plate 42 is increased, and the same reason as that of the above first heat conducting plate 21 for reducing junction-shell resistance is achieved, so that the package structure reduces the junction-shell resistance of the downward heat dissipation path, and simultaneously reduces the junction-shell resistance of the upward heat dissipation path, thereby further reducing the junction-shell resistance. It should be noted that, in the embodiment of the present application, the second substrate 32 is a double-sided metal-coated ceramic substrate with a high thermal conductivity coefficient, such as an aluminum oxide copper-clad plate, an aluminum nitride copper-clad plate, and the like, and the second bottom plate 42 is a metal bottom plate. The second substrate 32 is connected to the second heat conducting plate 22 by solder reflow or nano-silver sintering, and the second base plate 42 is connected to the second substrate 32 by solder reflow or nano-silver sintering, but the embodiment of the present invention is not limited thereto, and is determined as the case may be.

It should be noted that the second heat conducting plate 22 covers the second surface of the power chip 10, and is suitable for a power chip 10 without a control electrode, such as a diode. When the power chip 10 is a MOSFET, an IGBT, or other power chip 10 having a control electrode, in another embodiment of the present application, as shown in fig. 4, the package structure further includes: the second heat conduction plate 22, the second substrate 32, the second base plate 42, the metal leads 23; the second surface of the power chip 10 is provided with a first connection point 11, one side surface of the first substrate 31 connected with the first heat conduction plate 21 is provided with a second connection point 12, the first connection point 11 is connected with the second connection point 12 through the metal lead 23, so that the power chip 10 is connected with the first substrate 31 through the metal lead 23, the second heat conduction plate 22 is adhered with the second surface of the power chip 10 to cover the area of the second surface of the power chip 10 except the preset area, the second heat conduction plate 22 is a soaking plate or a heat pipe with the size larger than that of the power chip 10, the size of the first substrate 31 is larger than that of the first heat conduction plate 21, and usually the size of the second substrate 32 is larger than that of the second heat conduction plate 22, and the size of the second bottom plate 42 is larger than or equal to that of the second substrate 32, the second surface of the power chip 10 is opposite to the first surface of the power chip 10, and the preset area is an area where the first connection point 11 is located, and provides a space for connecting the power chip 10 and the first substrate 31; the second substrate 32 covers a side of the second heat conduction plate 22 departing from the second surface of the power chip 10, that is, the second substrate 32 is connected to a side of the second heat conduction plate 22 departing from the second surface of the power chip 10, and the second bottom plate 42 covers a side of the second substrate 32 departing from the second surface of the power chip 10, that is, the second bottom plate 42 is connected to a side of the second substrate 32 departing from the second surface of the power chip 10.

The second heat conducting plate 22 conducts heat transversely to the heat generated by the power chip 10, and transfers the heat generated by the power chip 10 to the second heat conducting plate 22, so that the heat transferred to the second heat conducting plate 22 is distributed in the whole second heat conducting plate 22, and the second heat conducting plate 22 conducts heat longitudinally to the heat generated by the power chip 10, so that the heat generated by the power chip 10 is sequentially transferred through the second heat conducting plate 22, the second substrate 32 and the second bottom plate 42, and the heat dissipation path of the heat generated by the power chip 10 further comprises the second heat conducting plate 22, the second substrate 32 and the second bottom plate 42, and further the packaging structure is a double-sided heat dissipation packaging structure. In the embodiment of the present application, the size of the second heat conducting plate 22 is larger than that of the power chip 10, so that the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the second substrate 32 and the second bottom plate 42 is increased, and the joint-shell thermal resistance is reduced by the first heat conducting plate 21, so that the package structure reduces the joint-shell thermal resistance of the downward heat dissipation path, and simultaneously reduces the joint-shell thermal resistance of the upward heat dissipation path, thereby further reducing the joint-shell thermal resistance.

On the basis of the foregoing embodiment, in the embodiment of the present application, when the power chip 10 is a MOSFET, an IGBT, or the like having the control electrode power chip 10, the control electrode of the power chip 10 needs to be connected to the first substrate 31 through a metal wire, the preset region is the region where the first connection point 11 is located, the second heat conduction plate 22 is adhered to the second surface of the power chip 10 to cover the region of the second surface of the power chip 10 except the preset region, so that when the second heat conduction plate 22 is connected to the second surface of the power chip 10, the portion where the control electrode (gate or base) of the power chip 10 is connected to the metal wire 23 can be avoided, and the package structure can be applied to the case where the power chip 10 is a MOSFET, an IGBT, or the like having the control electrode power chip 10. Moreover, when the power chip 10 is a MOSFET, an IGBT or the like having a gate power chip 10, it is known that the gate of the power chip 10 needs to be connected to the first substrate 31 through the metal lead 23, so that the first substrate 31 also needs to reserve an area connected to the metal lead 23, and therefore, in the embodiment of the present application, the size of the first substrate 31 is larger than that of the first heat conduction plate 21, so that the first substrate 31 has an area connected to the metal lead 23, and thus the package structure can be applied to the case where the power chip 10 is a MOSFET, an IGBT or the like having a gate power chip 10. It should be noted that the power chip 10 and the first substrate 31 may be connected by a plurality of metal leads 23, and the embodiment of the present application is a simplified schematic diagram and only shows one metal lead, but the number of the metal leads 23 is not limited in the embodiment of the present application, which is determined as the case may be.

It should be noted that, in the above embodiment, when the power chip 10 is a MOSFET, an IGBT, or the like, and has the control electrode power chip 10, in order that the control electrode of the power chip 10 can be connected to the first substrate 31 through the metal lead 23, the second heat conducting plate 22 covers the preset area of the power chip 10, so that the position between the second heat conducting plate 22 and the power chip 10 has a certain offset, such that the distance from one side of the second heat conducting plate 22 to the power chip 10 is relatively large, and the distance from the opposite side is relatively small, such that when the heat generated by the power chip 10 is transferred to the second heat conducting plate 22, the transmission distance from the one side of the power chip 10 to the other side is relatively long, and the transmission distance from the other side of the power chip is relatively short. Since the longer the heat transmission distance is, the poorer the heat conduction effect is, when there is a certain degree of deviation in the position between the second heat conducting plate 22 and the power chip 10, there is a case that the heat transmission distance is large, which is not favorable for the heat transmitted to the second heat conducting plate 22 to be distributed in the whole second heat conducting plate 22, and further affects the reduction effect of junction-shell thermal resistance. In yet another embodiment of the present application, as shown in fig. 5, the package structure further includes: the second heat conduction plate 22, the second substrate 32, the second base plate 42, the metal lead 23, and the spacer 60; the first surface of the power chip 10 is provided with a first connection point 11, one side surface of the first substrate 31, which is connected with the first heat conduction plate 21, is provided with a second connection point 12, the first connection point 11 and the second connection point 12 are connected through the metal lead 23, and the gasket 60 covers the area of the second surface of the power chip 10 except the preset area; the second heat conducting plate 22 covers the side of the spacer 60 away from the second surface of the power chip 10, and has a size larger than that of the power chip 10, the size of the first substrate 31 is larger than that of the first heat conducting plate 21, and generally, the size of the second substrate 32 is larger than that of the second heat conducting plate 22, the size of the second base plate 42 is larger than or equal to that of the second substrate 32, and the predetermined area is the area where the first connecting point 11 is located; the first surface of the power chip 10 is opposite to the second surface of the power chip 10, the second substrate 32 covers one side of the second heat-conducting plate 22 departing from the second surface of the power chip 10, that is, the second substrate 32 is connected to one side of the second heat-conducting plate 22 departing from the second surface of the power chip 10, and the second base plate 42 covers one side of the second substrate 32 departing from the second surface of the power chip 10, that is, the second base plate 42 is connected to one side of the second substrate 32 departing from the second surface of the power chip 10. The second heat conducting plate 22 conducts heat transversely to the heat generated by the power chip 10, so that part of the heat transferred to the second heat conducting plate 22 is distributed in the whole second heat conducting plate 22, and the second heat conducting plate 22 conducts heat longitudinally to the heat generated by the power chip 10, so that the heat generated by the power chip 10 is transferred sequentially through the second heat conducting plate 22, the second substrate 32 and the second bottom plate 42, and therefore the packaging structure reduces junction-shell resistance of a downward heat dissipation path and reduces junction-shell resistance of an upward heat dissipation path, and further reduces junction-shell resistance of the heat dissipation path.

Specifically, in the embodiment of the present application, the package structure includes a pad 60, the pad 60 is located on the second surface of the power chip 10 except for the predetermined area, the second heat conduction plate 22 covers a side of the spacer 60 facing away from the second surface of the power chip 10, so that the power chip 10 and the second heat conduction plate 22 are joined by the spacer 60, so that the second heat conduction plate 22 does not need to avoid the region where the power chip 10 is connected to the metal leads 23, and the heat generated from the power chip 10 is transferred to the second heat conductive plate 22 through the spacer 60, by controlling the relative position between the second heat conduction plate 22 and the spacer 60, the heat generated by the power chip 10 can be facilitated to be transferred to the second heat conduction plate 22, thereby facilitating to ensure the junction-shell thermal resistance reduction effect.

It should be noted that the preset area is an area where the first connection point 11 is located, so that the preset area provides a space for forming the first connection point 11, and the first connection point 11 and the second connection point 12 are connected by a metal lead 23, so that the power chip 10 is connected to the first substrate 31, and further, the preset area provides a space for connecting the power chip 10 to the first substrate 31. It should be further noted that, in the above embodiment, the power chip 10 and the first substrate 31 are connected by one metal lead 23, in other embodiments of the present application, according to actual requirements, the power chip 10 and the first substrate 31 may be connected by a plurality of metal leads 23, and one metal lead corresponds to one first connection point 11 and one second connection point 12, so that the power chip 10 and the first substrate 31 are connected by a plurality of metal leads 23, the second surface of the power chip 10 has the same number of first connection points 11 as the number of metal leads 23, and the side surface of the first substrate 31 connected to the first heat conduction plate 21 has the same number of second connection points 12 as the number of metal leads 23.

For the package structure, no matter the power chip 10 is a power chip without a control electrode, such as a diode, or a power chip with a control electrode, such as a MOSFET, an IGBT, etc., the power chip 10 needs to be connected to the circuit of the first substrate 31, and only when the power chip 10 is a power chip 10 with a control electrode, such as a MOSFET, an IGBT, etc., two electrodes of the power chip 10 are respectively connected to the first substrate 31, one of the two electrodes is directly connected to the first substrate 31 through the lower surface of the power chip 10 (corresponding to the first surface of the power chip 10), and the other electrode is connected to the first substrate 31 through the upper surface of the power chip 10 (corresponding to the second surface of the power chip 10) by a metal lead 23, so that the material of the first heat conduction plate 21 is a material with a good electric conduction capability in order to enable the power chip 10 to be connected to the circuit of the first substrate 31, such as copper, aluminum, etc. In addition, in practical application of the package structure, the power chip 10 may also need to be electrically connected to the second substrate 32, so that the material of the second heat conduction plate 21 is also a material with good conductivity, so that the current path in the package structure is: the first substrate 31 circuit-first heat-conducting plate 21-power chip 10-second heat-conducting plate 22-second substrate 32 circuit, or the first substrate 31 circuit-first heat-conducting plate 21-power chip 10-spacer 60-second heat-conducting plate 22-second substrate 32 circuit. It should be further noted that there may be a circuit pattern on the surfaces of the first substrate 31 and the second substrate 32, and when the surfaces of the first substrate 31 and the second substrate 32 have the circuit pattern and the second heat conduction plate 22 and the first heat conduction plate 21 are made of materials with better conductive capability, in order to avoid affecting the operation of the first substrate 31 and the second substrate 32, the first heat conduction plate 21 is connected to the originally short-circuited portion of the circuit pattern of the first substrate 31, and the second heat conduction plate 22 is connected to the originally short-circuited portion of the circuit pattern of the second substrate 32.

On the basis of the above embodiments, in an embodiment of the present application, the power chip 10 may include one sub-chip, and may also include a plurality of sub-chips, when the power chip 10 includes a plurality of sub-chips connected in parallel, the plurality of sub-chips are located on the same first heat-conducting plate 21, and a side surface of the plurality of sub-chips contacting the first heat-conducting plate 21 is coplanar, so that the plurality of sub-chips are bonded to the same first heat-conducting plate 21. It is known that the second surface of the power chip 10 is connected to the second heat conducting plate 22, and therefore, the plurality of sub-chips are also bonded to the same second heat conducting plate 22, so that when the package structure has a plurality of sub-chips, only one first heat conducting plate 21 and one second heat conducting plate 22 are needed, and a plurality of first heat conducting plates 21 and second heat conducting plates 22 are not needed, so that the package structure can reduce junction-shell thermal resistance, and at the same time, the number of the first heat conducting plates 21 and the second heat conducting plates 22 can be reduced, and the process complexity is reduced. It should be noted that, in the embodiment of the present application, the number of the sub chips is not limited, and is determined as the case may be.

On the basis of any of the above embodiments, in an embodiment of the present application, in order to protect the vulnerable components such as the power chip 10, the metal lead 23, and the like, the package structure further includes a plastic package body and an external casing, the plastic package body covers the components described in any of the above embodiments, that is, the power chip 10, the first heat conduction plate 21, the first substrate 31, and the first bottom plate 41, and when the package structure includes the second heat conduction plate 22, the second substrate 32, the second bottom plate 42, and the gasket 60, the package structure is also covered by the plastic package body, and the package structure provided in the embodiment of the present application includes the power chip 10, the first heat conduction plate 21, the first substrate 31, the first bottom plate 41, the second heat conduction plate 22, the second substrate 32, the second bottom plate 42, and the gasket 60, and may also include other components, and the other components are also covered by the plastic package body, the plastic package structure comprises a plastic package body, a plastic package body and an outer shell, wherein the plastic package body is arranged in the outer shell, and the plastic package body is arranged in the outer shell and is used for covering the plastic package body.

The first heat conduction plate 21 has a plate-like structure, and generally, a surface of the first heat conduction plate 21 connected to the power chip 10 is parallel to and equal in size to a surface of the first heat conduction plate 21 connected to the first substrate 31. The second heat conduction plate 22 has a plate structure, and generally, a surface of the second heat conduction plate 22 connected to the power chip 10 (or the spacer 60) is parallel to and equal to a surface of the second heat conduction plate 22 connected to the second substrate 32.

In summary, the embodiment of the present application provides a power semiconductor device package structure, including: the heat dissipation device comprises a power chip 10, a first heat conduction plate 21, a first substrate 31 and a first bottom plate 41, wherein the size of the first heat conduction plate 21 is larger than that of the power chip 10, the first heat conduction plate 21 conducts transverse heat conduction and longitudinal heat conduction on heat generated by the power chip 10 to realize that the heat transferred to the first heat conduction plate 21 is distributed in the whole first heat conduction plate 21, and the heat generated by the power chip 10 is transferred sequentially through the first heat conduction plate 21, the first substrate 31 and the first bottom plate 41, so that the first heat conduction plate 21 has both transverse heat conduction capability and longitudinal heat conduction capability, a heat dissipation path of heat generated by the power chip 10 is the first heat conduction plate 21-the first substrate 31-the first bottom plate 41, and thus the power chip 10 does not directly contact with the first substrate 31 to transfer heat, but is transferred into the first substrate 31 through the first heat conduction plate 21, so that the cross-sectional area of the passage when heat flows through the first substrate 31 and the first base plate 41 is the area of the side of the first heat conduction plate 21 in contact with the first substrate 31. Because the size of the first heat conducting plate 21 is larger than that of the power chip 10, compared with the existing package structure, the package structure provided in the embodiment of the present application increases the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the first substrate 31 and the first bottom plate 41, that is, the cross-sectional area of the heat flow channel is increased, and the thickness of the first heat conducting plate 21 is generally thinner, so that even if the heat dissipation path is increased, the junction-shell thermal resistance of the package structure can not be greatly affected, and thus the package structure can reduce the junction-shell thermal resistance of the package structure under the condition of increasing the cross-sectional area of the heat flow channel, so that the package structure has smaller junction-shell thermal resistance, which is helpful for ensuring the working reliability of the package structure.

In addition, the package structure further includes: the second heat conducting plate 22, the second substrate 32 and the second bottom plate 42 make the heat dissipation path of the power chip 10 generate heat further include the second heat conducting plate 22-the second substrate 32-the second bottom plate 42, so that the package structure is a double-sided heat dissipation package structure, and the size of the second heat conducting plate 22 is larger than that of the power chip 10, thereby increasing the cross-sectional area of the channel when the heat generated by the power chip 10 flows through the second substrate 32 and the second bottom plate 42, so that the package structure reduces the junction-shell resistance of the downward heat dissipation path, and simultaneously reduces the junction-shell resistance of the upward heat dissipation path, thereby further reducing the junction-shell resistance.

All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A power semiconductor device package structure, comprising:

a power chip;

a first heat-conducting plate covering the first surface of the power chip, the first heat-conducting plate having a size larger than that of the power chip;

the first substrate covers one side, away from the first surface of the power chip, of the first heat conduction plate;

the first bottom plate covers one side, away from the first surface of the power chip, of the first substrate;

wherein, first heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the first heat-conducting plate is whole in the first heat-conducting plate, just first heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order first heat-conducting plate first base plate first bottom plate transmission.

2. The package structure of claim 1, wherein the first heat-conducting plate has a transverse equivalent thermal conductivity higher than 1000W/m-K.

3. The package structure of claim 1, wherein the first thermally conductive plate is a thermal spreader or a heat pipe.

4. The package structure according to claim 1, further comprising a pressure head, wherein the pressure head is provided with a groove having a shape matching the shape of the power chip, the power chip is embedded in the groove, and the pressure head covers a region of a side surface of the first heat conducting plate, which is connected to the power chip, except for the region where the power chip is located.

5. The package structure of claim 1, further comprising: the second heat conducting plate, the second substrate and the second bottom plate;

the second heat conducting plate covers the second surface of the power chip, the second substrate covers one side of the second heat conducting plate, which is far away from the second surface of the power chip, and the second bottom plate covers one side of the second substrate, which is far away from the second surface of the power chip; the second heat conducting plate is a soaking plate or a heat pipe, the size of the second heat conducting plate is larger than that of the power chip, and the second surface of the power chip is opposite to the first surface of the power chip;

wherein, the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate.

6. The package structure of claim 1, further comprising: the second heat conducting plate, the second substrate, the second bottom plate and the metal lead;

the second surface of the power chip is provided with a first connecting point, one side surface of the first substrate, which is connected with the first heat conducting plate, is provided with a second connecting point, and the first connecting point and the second connecting point are connected through the metal lead, so that the power chip is connected with the first substrate through the metal lead; the second heat conduction plate covers the area of the second surface of the power chip except the preset area, the second substrate covers one side of the second heat conduction plate departing from the second surface of the power chip, and the second bottom plate covers one side of the second substrate departing from the second surface of the power chip; the second heat conducting plate is a vapor chamber or a heat pipe, the size of the second heat conducting plate is larger than that of the power chip, the size of the first substrate is larger than that of the first heat conducting plate, the second surface of the power chip is opposite to the first surface of the power chip, and the preset area is an area where the first connecting point is located and provides a space for connecting the power chip and the first substrate;

the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate.

7. The package structure of claim 1, further comprising: the second heat conducting plate, the second substrate, the second bottom plate, the metal lead and the gasket;

the second surface of the power chip is provided with a first connecting point, one side surface of the first substrate, which is connected with the first heat conducting plate, is provided with a second connecting point, and the first connecting point and the second connecting point are connected through the metal lead, so that the power chip is connected with the first substrate through the metal lead; the gasket is positioned on the area of the second surface of the power chip except for the preset area, the second heat-conducting plate covers one side of the gasket, which is far away from the second surface of the power chip, the second substrate covers one side of the second heat-conducting plate, which is far away from the second surface of the power chip, and the second bottom plate covers one side of the second substrate, which is far away from the second surface of the power chip; the second heat conducting plate is a vapor chamber or a heat pipe, the size of the second heat conducting plate is larger than that of the power chip, the size of the first substrate is larger than that of the first heat conducting plate, the first surface of the power chip is opposite to the second surface of the power chip, and the preset area is an area where the first connecting point is located and provides a space for connecting the power chip and the first substrate;

the second heat-conducting plate is right the heat that the power chip produced carries out horizontal heat-conduction, realizes transmitting heat distribution in the second heat-conducting plate is whole in the second heat-conducting plate, and the second heat-conducting plate is right the heat that the power chip produced carries out vertical heat-conduction, realizes the heat that the power chip produced passes through in proper order the second heat-conducting plate the second base plate the transmission of second bottom plate.

8. The package structure of claim 1, wherein the power chip comprises a plurality of sub-chips disposed on the same first heat-conducting plate, and wherein the plurality of sub-chips are coplanar with a side surface of the first heat-conducting plate.

9. The package structure of any one of claims 1-8, further comprising: the plastic package structure comprises a plastic package body and an external shell, wherein the plastic package body wraps all parts in the package structure, and the package structure is located in the external shell.

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