CN216849904U

CN216849904U - Semiconductor packaging structure

Info

Publication number: CN216849904U
Application number: CN202220298713.0U
Authority: CN
Inventors: 杨荣锋
Original assignee: Shenzhen Yongyuan Microelectronics Technology Co ltd
Current assignee: Shenzhen Yongyuan Microelectronics Technology Co ltd
Priority date: 2022-02-14
Filing date: 2022-02-14
Publication date: 2022-06-28
Anticipated expiration: 2032-02-14

Abstract

The utility model discloses a semiconductor packaging structure, which comprises a circuit substrate, wherein a solder bump is fixed at the top end of the circuit substrate; the chip is fixed on the upper surface of the circuit substrate in an inverted mode with the front surface facing downwards, and the bottom end of the chip is electrically connected with the convex pad; the underfill is filled between the solder balls and the circuit substrate and fills gaps between the solder balls and the circuit substrate; the two ends of the electric connection structure are respectively connected and fixed with the convex pad and the bottom antenna layer; the bottom antenna layer is fixed at the top end of the plastic packaging layer, and the plastic packaging layer is fixed at the top end of the underfill; the part of semiconductor chip and underfill contact does not have the right angle, can the concentration of greatly reduced stress to can effectively avoid the fracture of semiconductor chip that stress caused, through the protruding pad structure at middle part, the chip can improve structural stability when placing, and then improves packaging structure's reliability.

Description

Semiconductor packaging structure

Technical Field

The utility model relates to a semiconductor packaging hardware field especially relates to a semiconductor packaging structure.

Background

To seal the semiconductor package, Liquid Encapsulation (LE) or molding is generally used. The LE covers and protects the connectors from mechanical damage and protects the area where the glass cover and die are coupled together from moisture.

With the increasing functional requirements of network application electronic devices, the performance improvement, the lower production cost and the smaller form factor, package structures such as flip chip size package (FCCSP), Wafer Level Chip Size Package (WLCSP), fan-out wafer level chip size package (FOWLCSP), 2.5D chip package, 3D chip package, and the like are widely used. However, the reliability of the package structure is poor due to some matching problems of the structure and the material in each package structure. Taking a semiconductor package structure of chinese patent as an example, the semiconductor package structure includes a circuit substrate 10, a semiconductor chip 11 flip-chip mounted on the circuit substrate 10 via a solder bump 12, and an underfill 13 filled between the circuit substrate 10 and the semiconductor chip 11; in the package structure, after the underfill 13 is filled between the circuit substrate 10 and the semiconductor chip 11, stress is generated in the package structure due to coefficient of thermal expansion mismatch (CTE mismatch) between the underfill 13 and the semiconductor chip 11, the stress is mainly concentrated at a right angle where the semiconductor chip 11 is in contact with the underfill 13, and the concentration of the stress at the right angle of the semiconductor chip 11 causes the semiconductor chip 11 to crack, thereby causing a problem of poor reliability of the semiconductor package structure.

SUMMERY OF THE UTILITY MODEL

In order to overcome the not enough of prior art, the utility model provides a semiconductor package structure, the part of semiconductor chip and underfill contact does not have the right angle, concentration that can greatly reduced stress to can effectively avoid the breaking of semiconductor chip that stress caused, through the protruding pad structure at middle part, the chip can improve structural stability when placing, and then improves package structure's reliability.

In order to solve the technical problem, the utility model provides a following technical scheme: a semiconductor packaging structure comprises a circuit substrate, wherein a solder bump is fixed at the top end of the circuit substrate; the chip is fixed on the upper surface of the circuit substrate in an inverted mode with the front surface facing downwards, and the bottom end of the chip is electrically connected with the convex pad; the underfill is filled between the solder balls and the circuit substrate and fills gaps between the solder balls and the circuit substrate; the two ends of the electric connection structure are respectively connected and fixed with the convex pad and the bottom antenna layer; the bottom antenna layer is fixed at the top end of the plastic packaging layer, and the plastic packaging layer is fixed at the top end of the underfill; and the top antenna layer is fixed at the top end of the bottom antenna layer, and the middle part of the top antenna layer is fixed at the top end of the dielectric layer through a lead frame.

As an optimized technical solution of the present invention, the bottom antenna layer is fixed in the middle of the dielectric layer structure.

As an optimized technical scheme of the utility model, protruding pad is L type structure, and its bottom and solder ball fixed connection, the solder ball is fixed with solder bump spot welding.

As an optimized technical scheme of the utility model, the dielectric layer structure is fixed in the top of plastic envelope layer.

As an optimized technical scheme of the utility model, the material of electric connection structure is Cu.

Compared with the prior art, the utility model discloses the beneficial effect that can reach is:

the utility model discloses an among the semiconductor package structure, there is not the right angle in the part of semiconductor chip and underfill contact, concentration that can greatly reduced stress to can effectively avoid the breaking of the semiconductor chip that stress caused, through the protruding pad structure at middle part, the chip can improve structural stability when placing, and then improves package structure's reliability.

Drawings

FIGS. 1-3 are schematic sectional views of the present invention during the manufacturing process;

fig. 4 is a schematic structural diagram of the antenna layer and the lead frame according to the present invention.

Wherein: 1. a circuit substrate; 2. a solder bump; 3. a solder ball; 4. underfill adhesive; 5. a convex pad; 6. a plastic packaging layer; 7. an electrical connection structure; 8. a chip; 9. a lead frame; 10. a top antenna layer; 11. a bottom antenna layer.

Detailed Description

In order to make the technical means, the creation features, the achievement purposes and the functions of the invention easy to understand, the invention is further explained below with reference to the specific embodiments, but the following embodiments are only the preferred embodiments of the invention, not all. Based on the embodiments in the implementation, other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention. The experimental methods in the following examples are conventional methods unless otherwise specified, and materials, reagents and the like used in the following examples are commercially available unless otherwise specified.

The embodiment is as follows:

as shown in fig. 1-4, the present invention provides a semiconductor package structure,

comprises a circuit substrate 1, a solder bump 2 is fixed on the top end of the circuit substrate 1;

the chip 8 is fixed on the upper surface of the circuit substrate 1 in an inverted mode with the front surface facing downwards, and the bottom end of the chip 8 is electrically connected with the convex pad 5;

the underfill 4 is filled between the solder balls 3 and the circuit substrate 1, and gaps between the solder balls 3 and the circuit substrate 1 are filled with the underfill 4;

the two ends of the electric connection structure 7 are respectively connected and fixed with the convex pad 5 and the bottom antenna layer 11;

the bottom antenna layer 11 is fixed at the top end of the plastic packaging layer 6, and the plastic packaging layer 6 is fixed at the top end of the underfill 4;

and a top antenna layer 10 fixed on the top end of the bottom antenna layer 11, and the middle part of the top antenna layer 10 is fixed on the top end of the dielectric layer through the lead frame 9.

In other embodiments, the bottom-antenna-layer 11 is fixed to the middle of the dielectric layer structure.

In other embodiments, the bump pad 5 has an L-shaped structure, and the bottom end thereof is fixedly connected to the solder ball 3, and the solder ball 3 is fixed to the solder bump 2 by spot welding.

In other embodiments, the dielectric layer structure is fixed on top of the molding layer 6.

In other embodiments, the material of the electrical connection structure 7 is Cu.

Among the semiconductor packaging structure, there is not the right angle in the part of semiconductor chip and 4 contacts of underfill, concentration that can greatly reduced stress to can effectively avoid breaking of semiconductor chip 8 that stress caused, through the protruding pad 5 structure at middle part, chip 8 can improve structural stability when placing, and then improves packaging structure's reliability.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the description in the above embodiments and the description is only the preferred embodiments of the present invention, and is not intended to limit the present invention, and that there may be various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications all fall within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A semiconductor package structure, characterized in that:

the circuit board comprises a circuit substrate (1), wherein a solder bump (2) is fixed at the top end of the circuit substrate (1);

the chip (8) is fixed on the upper surface of the circuit substrate (1) in an inverted mode with the front surface facing downwards, and the bottom end of the chip (8) is electrically connected with the convex pad (5);

the underfill (4) is filled between the solder balls (3) and the circuit substrate (1) and fills gaps between the solder balls (3) and the circuit substrate (1);

the two ends of the electric connection structure (7) are respectively connected and fixed with the convex pad (5) and the bottom antenna layer (11);

the bottom antenna layer (11) is fixed at the top end of the plastic packaging layer (6), and the plastic packaging layer (6) is fixed at the top end of the underfill (4);

and the top antenna layer (10) is fixed at the top end of the bottom antenna layer (11), and the middle part of the top antenna layer (10) is fixed at the top end of the dielectric layer through a lead frame (9).

2. The semiconductor package structure of claim 1, wherein: the bottom antenna layer (11) is fixed in the middle of the dielectric layer structure.

3. The semiconductor package structure of claim 1, wherein: the convex pad (5) is of an L-shaped structure, the bottom end of the convex pad is fixedly connected with the solder ball (3), and the solder ball (3) is fixed with the solder bump (2) in a spot welding manner.

4. The semiconductor package structure of claim 1, wherein: the dielectric layer structure is fixed on the top end of the plastic packaging layer (6).

5. The semiconductor package structure of claim 1, wherein: the electric connection structure (7) is made of Cu.