CN112701107A

CN112701107A - Stack packaging structure, packaging process thereof and electronic product

Info

Publication number: CN112701107A
Application number: CN202011483410.8A
Authority: CN
Inventors: 唐和明; 曹周; 黄源炜; 郑明祥
Original assignee: Great Team Backend Foundry Dongguan Co Ltd
Current assignee: Great Team Backend Foundry Dongguan Co Ltd
Priority date: 2020-12-15
Filing date: 2020-12-15
Publication date: 2021-04-23

Abstract

The invention discloses a stacked packaging structure, which comprises a GaN chip and a control chip, wherein a circuit pattern is arranged on one side of the GaN chip, which is not provided with an electrode, the control chip is electrically connected with the circuit pattern, the circuit pattern is electrically connected with a grid electrode of the GaN chip through a conductive metal penetrating through the GaN chip, and is electrically connected with a lead frame used for fixing the GaN chip through a metal wire. According to the scheme, the control chip is stacked on the back of the GaN chip, the electrode of the control chip and the grid electrode of the GaN chip can be electrically connected through the circuit pattern arranged on the back of the GaN chip and the conductive metal penetrating through the GaN chip, so that the distance between the control chip and the electrode of the GaN chip can be minimized, the inductance is reduced to the maximum extent, and the switching speed is increased.

Description

Stack packaging structure, packaging process thereof and electronic product

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a stacked packaging structure, a packaging process of the butt-joint packaging structure and an electronic product applying the stacked packaging structure.

Background

The third generation semiconductor gallium nitride has wide band gap and electron mobility, has high switching speed and is applied to the field of radio frequency. The GaN HEMT device is mainly applied to the fields of satellite communication, radar detection, 5G communication, terahertz detection and the like. When the GaN chip is applied, a control chip is needed to control the on-off of the GaN chip, the control chip and the grid electrode of the GaN chip need to be electrically connected to realize a control function, the two chips are connected in a metal wire welding mode on the market at present, and the connection mode leads to the generation of inductance due to long distance and small diameter of the metal wire, so that the switching speed is slowed down by the inductance.

Disclosure of Invention

The embodiment of the invention aims to: a package on package structure, a package process thereof and an electronic product are provided, which can solve the above problems in the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

on one hand, the stack packaging structure comprises a GaN chip and a control chip, wherein a circuit pattern is arranged on one side, which is not provided with an electrode, of the GaN chip, the control chip is electrically connected with the circuit pattern, the circuit pattern is electrically connected with a grid electrode of the GaN chip through conductive metal penetrating through the GaN chip, and is electrically connected with a lead frame used for fixing the GaN chip through a metal lead.

As a preferable technical solution of the stack package structure, the GaN chip includes a silicon substrate and a GaN epitaxial layer, and a source, a gate and a drain of the GaN chip are formed on the GaN epitaxial layer.

As a preferable technical solution of the stack package structure, an insulating material layer is disposed on a side of the silicon substrate away from the GaN epitaxial layer, and the circuit pattern is formed on the insulating material layer.

As a preferable technical solution of the stack package structure, the control chip is flip-chip bonded on the circuit pattern by a solder ball.

As a preferable technical solution of the stack package structure, the stack package structure further includes an encapsulation resin, the encapsulation resin encapsulates the control chip, the GaN chip, and the metal wires for electrically connecting the circuit pattern and the lead frame, and the surface of the lead frame not provided with the GaN chip is exposed to the outside of the encapsulation resin.

In another aspect, a package on package process is provided for packaging the package on package structure as described above.

As a preferred technical solution of the stack packaging process, the method comprises the following steps:

step 1, providing a GaN chip, wherein a silicon material is used as a substrate, and a GaN epitaxial layer is arranged on the surface of one side of the silicon material to form the GaN chip;

step 2, arranging an insulating layer, wherein the insulating layer is arranged on the surface of the GaN chip where the electrode is not formed;

step 3, rewiring, wherein a circuit pattern is arranged on the insulating layer by adopting a conductive metal material;

step 4, opening a hole, namely processing a blind hole on the GaN chip, wherein two ends of the blind hole are respectively connected with the circuit pattern and a grid electrode of the GaN chip;

step 5, filling metal, namely filling metal materials in the blind holes to electrically connect the circuit pattern with the grid electrode of the GaN chip;

step 6, welding, namely welding the GaN chip filled with the metal in the step 5 to a lead frame;

step 7, routing, namely welding a metal wire to electrically connect the circuit pattern and the lead frame;

step 8, controlling chip welding, namely inversely welding the control chip to the back surface of the GaN through a tin ball;

and 9, packaging, namely, adopting an epoxy resin material to carry out alignment on the control chip, the GaN chip and the metal wire.

As a preferred technical solution of the stack package process, the opening is implemented by using a through silicon via technology.

As a preferred technical solution of the stack package process, the metal filling is performed by electroplating and/or metal melting.

In another aspect, an electronic product having the package on package structure is provided.

The invention has the beneficial effects that: according to the scheme, the control chip is stacked on the back of the GaN chip, the electrode of the control chip and the grid electrode of the GaN chip can be electrically connected through the circuit pattern arranged on the back of the GaN chip and the conductive metal penetrating through the GaN chip, so that the distance between the control chip and the electrode of the GaN chip can be minimized, the inductance is reduced to the maximum extent, and the switching speed is increased.

Drawings

The invention is explained in more detail below with reference to the figures and examples.

Fig. 1 is a schematic structural diagram of a package on package structure according to an embodiment of the invention.

Fig. 2 is a flow chart of a package on package process according to an embodiment of the invention.

In the figure:

100. a GaN chip; 110. a substrate; 120. a GaN epitaxial layer; 130. a layer of insulating material; 140. a circuit pattern; 150. a source electrode; 160. a gate electrode; 170. a drain electrode; 180. a conductive metal; 200. a control chip; 300. tin balls; 400. an encapsulating resin; 500. a metal wire; 600. a lead frame.

Detailed Description

In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

As shown in fig. 1, the present embodiment provides a stacked package structure, which is mainly applied to a third generation semiconductor GaN chip, the GaN chip has a wide band gap and an electron mobility, the switching speed is fast, and the stacked package structure in the present embodiment is widely applied to the radio frequency field, the stacked package structure includes a GaN chip 100 stacked in a stacked manner and a control chip 200 for performing on-off control on the GaN chip 100, a circuit pattern 140 is disposed on a side of the GaN chip 100 not provided with an electrode, the control chip 200 is electrically connected to the circuit pattern 140, the circuit pattern 140 is electrically connected to a gate 160 of the GaN chip 100 through a conductive metal 180 penetrating through the GaN chip 100, and is electrically connected to a lead frame 600 for fixing the GaN chip 100 through a metal wire 500.

In the scheme, the control chip 200 is stacked on the back surface of the GaN chip 100, and the electrode of the control chip 200 and the gate 160 of the GaN chip 100 can be electrically connected through the circuit pattern 140 arranged on the back surface of the GaN chip 100 and the conductive metal 180 penetrating through the GaN chip 100, so that the distance between the control chip 200 and the electrode of the GaN chip 100 can be minimized, the inductance can be reduced to the maximum extent, and the switching speed can be increased.

Specifically, the GaN chip 100 includes a silicon substrate 110 and a GaN epitaxial layer 120, and a source 150, a gate 160 and a drain 170 of the GaN chip 100 are formed on the GaN epitaxial layer 120. An insulating material layer 130 is disposed on a side of the silicon substrate 110 away from the GaN epitaxial layer 120, and the circuit pattern 140 is formed on the insulating material layer 130.

In this embodiment, the control chip 200 is flip-chip bonded to the circuit pattern 140 via solder balls 300. The flip chip bonding technology is a technology for directly interconnecting an IC chip with a package shell or a wiring substrate in a face-down manner, and compared with other chip interconnection technologies such as Wire Bonding (WB) and Tape Automated Bonding (TAB), the flip chip bonding technology has the advantages of short interconnection line, small parasitic capacitance and parasitic inductance, random arrangement of an I/O electrode of the chip on the surface of the chip and high packaging density, so that the flip chip bonding technology is more suitable for large-scale integrated circuits (LSIs) with high frequency, high speed and high I/O ends, ultra-large-scale integrated circuits (VI.SI) and Application Specific Integrated Circuits (ASICs).

The stack package structure in this embodiment further includes an encapsulation resin 400, and the encapsulation resin 400 encapsulates the control chip 200, the GaN chip 100, and the metal wires 500 for electrically connecting the circuit pattern 140 and the lead frame 600 inside, and the surface of the lead frame not provided with the GaN chip 100 is exposed outside the encapsulation resin 400.

Meanwhile, as shown in fig. 2, the present embodiment further provides a package on package process for packaging the package on package structure as described above.

Specifically, the package-on-package process of the present embodiment includes the following steps:

step 1, providing a GaN chip 100, wherein a silicon material is used as a substrate 110, and a GaN epitaxial layer 120 is arranged on the surface of one side of the silicon material to form the GaN chip 100;

step 2, arranging an insulating layer, wherein the insulating layer is arranged on the surface of the GaN chip 100 where the electrode is not formed;

step 3, rewiring, wherein a circuit pattern 140 is arranged on the insulating layer by adopting a conductive metal 180 material;

step 4, forming a hole, namely processing a blind hole on the GaN chip 100, wherein two ends of the blind hole are respectively connected with the circuit pattern 140 and the grid 160 of the GaN chip 100; specifically, in this embodiment, the cross section of the blind via gradually decreases from the end close to the circuit pattern 140 to the end close to the gate 160 of the GaN chip 100;

step 5, filling metal, namely filling metal materials in the blind holes to electrically connect the circuit pattern 140 and the grid 160 of the GaN chip 100;

step 6, welding, namely welding the GaN chip 100 filled with the metal in the step 5 to the lead frame 600;

step 7, routing, namely welding a metal lead 500 to electrically connect the circuit pattern 140 and the lead frame 600;

step 8, welding the control chip 200, and inversely welding the control chip 200 to the back surface of the GaN through the solder balls 300;

and 9, packaging, namely, adopting epoxy resin materials to carry out alignment on the control chip 200, the GaN chip 100 and the metal lead 500.

Specifically, in the step 4, the blind holes are formed by processing the holes by using a through silicon via technology.

In this embodiment, the metal filling is performed by electroplating.

It should be noted that the manner of filling with metal is not limited to the electroplating process, and in other embodiments, the metal melting manner may be used or a combination of the electroplating and the metal melting manner may be used.

Meanwhile, the embodiment also provides an electronic product having the stacked package structure.

In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.

In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.

The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.

Claims

1. A stack package structure comprises a GaN chip (100) and a control chip (200), wherein a circuit pattern (140) is arranged on one side of the GaN chip (100) not provided with an electrode, the control chip (200) is electrically connected to the circuit pattern (140), and the circuit pattern (140) is electrically connected with a grid electrode (160) of the GaN chip (100) through a conductive metal (180) penetrating through the GaN chip (100) and is electrically connected with a lead frame (600) for fixing the GaN chip (100) through a metal wire (500).

2. The stacked package structure of claim 1, wherein the GaN chip (100) comprises a silicon substrate (110) and a GaN epitaxial layer (120), wherein the GaN epitaxial layer (120) has a source (150), a gate (160) and a drain (170) of the GaN chip (100) formed thereon.

3. The stacked package structure of claim 2, wherein a side of the silicon substrate (110) away from the GaN epitaxial layer (120) is provided with an insulating material layer (130), and the circuit pattern (140) is formed on the insulating material layer (130).

4. The stacked package structure of claim 3, wherein said control chip (200) is flip-chip bonded to said circuit pattern (140) by solder balls (300).

5. The stacked package structure of claim 4, further comprising an encapsulation resin (400), wherein the encapsulation resin (400) encapsulates the control chip (200), the GaN chip (100), and metal wires (500) for electrically connecting the circuit pattern (140) and the lead frame (600) inside, and wherein a surface of the lead frame not provided with the GaN chip (100) is exposed to the outside of the encapsulation resin (400).

6. A package on package process for packaging the package on package structure of any of claims 1-5.

7. The stack packaging process according to claim 6, comprising the steps of:

step 1, providing a GaN chip (100), wherein a silicon material is used as a base material (110), and a GaN epitaxial layer (120) is arranged on the surface of one side of the silicon material to form the GaN chip (100);

step 2, arranging an insulating layer, wherein the insulating layer is arranged on the surface of the GaN chip (100) where no electrode is formed;

step 3, rewiring, wherein a circuit pattern (140) is arranged on the insulating layer by adopting a conductive metal (180) material;

step 4, opening a hole, namely processing a blind hole on the GaN chip (100), wherein two ends of the blind hole are respectively connected with the circuit pattern (140) and a grid electrode (160) of the GaN chip (100);

step 5, filling metal, namely filling metal materials in the blind holes to electrically connect the circuit pattern (140) with a grid (160) of the GaN chip (100);

step 6, welding, namely welding the GaN chip (100) filled with the metal in the step 5 to a lead frame (600);

step 7, routing, namely welding a metal lead (500) to electrically connect the circuit pattern (140) and the lead frame (600);

step 8, controlling chip welding, namely inversely welding the control chip (200) to the back surface of the GaN through a solder ball (300);

and 9, packaging, namely, adopting an epoxy resin material to carry out alignment on the control chip (200), the GaN chip (100) and the metal wire (500).

8. The package on package process of claim 7, wherein the opening is formed by through silicon via technology.

9. The stack packaging process of claim 8, wherein the metal filling is performed by electroplating and/or metal melting.

10. An electronic product having the stacked package structure of any one of claims 1 to 5.